@@ -0,0 +1,90 | |||||
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1 | -- FillFifo.vhd | |||
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2 | library IEEE; | |||
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3 | use IEEE.std_logic_1164.all; | |||
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4 | use IEEE.numeric_std.all; | |||
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5 | ||||
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6 | entity FillFifo is | |||
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7 | generic( | |||
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8 | Data_sz : integer range 1 to 32 := 16; | |||
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9 | Fifo_cnt : integer range 1 to 8 := 5 | |||
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10 | ); | |||
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11 | port( | |||
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12 | clk : in std_logic; | |||
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13 | raz : in std_logic; | |||
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14 | write : out std_logic_vector(Fifo_cnt-1 downto 0); | |||
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15 | reuse : out std_logic_vector(Fifo_cnt-1 downto 0); | |||
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16 | data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0) | |||
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17 | ); | |||
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18 | end entity; | |||
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19 | ||||
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20 | ||||
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21 | architecture ar_FillFifo of FillFifo is | |||
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22 | ||||
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23 | signal i : integer := 0; | |||
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24 | ||||
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25 | type etat is (eX,e0,e00); | |||
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26 | signal ect : etat; | |||
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27 | ||||
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28 | type Tbl is array(natural range <>) of std_logic_vector(Data_sz-1 downto 0); | |||
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29 | ||||
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30 | --constant TblA : Tbl (0 to 255) := (X"FFFF",X"0142",X"0282",X"03C2",X"04FF",X"0638",X"076E",X"08A0",X"09CC",X"0AF2",X"0C11",X"0D29",X"0E39",X"0F40",X"103E",X"1131",X"121A",X"12F8",X"13CA",X"1490",X"1549",X"15F5",X"1694",X"1724",X"17A7",X"181B",X"187F",X"18D5",X"191C",X"1953",X"197A",X"1992",X"199A",X"1992",X"197A",X"1953",X"191C",X"18D5",X"187F",X"181B",X"17A7",X"1724",X"1694",X"15F5",X"1549",X"1490",X"13CA",X"12F8",X"121A",X"1131",X"103E",X"0F40",X"0E39",X"0D29",X"0C11",X"0AF2",X"09CC",X"08A0",X"076E",X"0638",X"04FF",X"03C2",X"0282",X"0142",X"0000",X"FEBE",X"FD7E",X"FC3E",X"FB01",X"F9C8",X"F892",X"F760",X"F634",X"F50E",X"F3EF",X"F2D7",X"F1C7",X"F0C0",X"EFC2",X"EECF",X"EDE6",X"ED08",X"EC36",X"EB70",X"EAB7",X"EA0B",X"E96C",X"E8DC",X"E859",X"E7E5",X"E781",X"E72B",X"E6E4",X"E6AD",X"E686",X"E66E",X"E666",X"E66E",X"E686",X"E6AD",X"E6E4",X"E72B",X"E781",X"E7E5",X"E859",X"E8DC",X"E96C",X"EA0B",X"EAB7",X"EB70",X"EC36",X"ED08",X"EDE6",X"EECF",X"EFC2",X"F0C0",X"F1C7",X"F2D7",X"F3EF",X"F50E",X"F634",X"F760",X"F892",X"F9C8",X"FB01",X"FC3E",X"FD7E",X"FEBE",X"0000",X"0142",X"0282",X"03C2",X"04FF",X"0638",X"076E",X"08A0",X"09CC",X"0AF2",X"0C11",X"0D29",X"0E39",X"0F40",X"103E",X"1131",X"121A",X"12F8",X"13CA",X"1490",X"1549",X"15F5",X"1694",X"1724",X"17A7",X"181B",X"187F",X"18D5",X"191C",X"1953",X"197A",X"1992",X"199A",X"1992",X"197A",X"1953",X"191C",X"18D5",X"187F",X"181B",X"17A7",X"1724",X"1694",X"15F5",X"1549",X"1490",X"13CA",X"12F8",X"121A",X"1131",X"103E",X"0F40",X"0E39",X"0D29",X"0C11",X"0AF2",X"09CC",X"08A0",X"076E",X"0638",X"04FF",X"03C2",X"0282",X"0142",X"0000",X"FEBE",X"FD7E",X"FC3E",X"FB01",X"F9C8",X"F892",X"F760",X"F634",X"F50E",X"F3EF",X"F2D7",X"F1C7",X"F0C0",X"EFC2",X"EECF",X"EDE6",X"ED08",X"EC36",X"EB70",X"EAB7",X"EA0B",X"E96C",X"E8DC",X"E859",X"E7E5",X"E781",X"E72B", | |||
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31 | --X"E6E4",X"E6AD",X"E686",X"E66E",X"E666",X"E66E",X"E686",X"E6AD",X"E6E4",X"E72B",X"E781",X"E7E5",X"E859",X"E8DC",X"E96C",X"EA0B",X"EAB7",X"EB70",X"EC36",X"ED08",X"EDE6",X"EECF",X"EFC2",X"F0C0",X"F1C7",X"F2D7",X"F3EF",X"F50E",X"F634",X"F760",X"F892",X"F9C8",X"FB01",X"FC3E",X"FD7E",X"FEBE"); | |||
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32 | ||||
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33 | constant TblA : Tbl (0 to 255) := (X"0001",X"0001",X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001", | |||
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34 | X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001", | |||
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35 | X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001"); | |||
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36 | ||||
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37 | constant TblB : Tbl (0 to 255) := (X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001", | |||
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38 | X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001", | |||
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39 | X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001"); | |||
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40 | ||||
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41 | constant TblC : Tbl (0 to 255) := (X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001", | |||
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42 | X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001", | |||
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43 | X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001"); | |||
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44 | ||||
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45 | constant TblD : Tbl (0 to 255) := (X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001", | |||
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46 | X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001", | |||
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47 | X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001"); | |||
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48 | ||||
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49 | constant TblE : Tbl (0 to 255) := (X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001", | |||
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50 | X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001", | |||
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51 | X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001"); | |||
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52 | ||||
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53 | begin | |||
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54 | ||||
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55 | process(clk,raz) | |||
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56 | begin | |||
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57 | if(raz='0')then | |||
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58 | i <= 0; | |||
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59 | Write <= (others => '1'); | |||
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60 | Reuse <= (others => '0'); | |||
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61 | ect <= e00; | |||
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62 | ||||
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63 | elsif(clk'event and clk='1')then | |||
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64 | ||||
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65 | case ect is | |||
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66 | ||||
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67 | when e00 => | |||
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68 | Write <= (others => '0'); | |||
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69 | ect <= e0; | |||
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70 | ||||
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71 | when e0 => | |||
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72 | if(i=255)then | |||
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73 | Write <= (others => '1'); | |||
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74 | Reuse <= (others => '1'); | |||
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75 | ect <= eX; | |||
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76 | else | |||
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77 | i <= i+1; | |||
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78 | ect <= e0; | |||
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79 | end if; | |||
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80 | ||||
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81 | when eX => | |||
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82 | null; | |||
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83 | ||||
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84 | end case; | |||
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85 | end if; | |||
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86 | end process; | |||
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87 | ||||
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88 | data <= TblE(i) & TblD(i) & TblC(i) & TblB(i) & TblA(i); | |||
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89 | ||||
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90 | end architecture; No newline at end of file |
@@ -15,28 +15,35 | |||||
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
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16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 |
------------------------------------------------------------------------------ |
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18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Alexis Jeandet |
|
19 | -- Author : Alexis Jeandet | |
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
21 | ---------------------------------------------------------------------------- |
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21 | ------------------------------------------------------------------------------ | |
22 | library ieee; |
|
22 | library ieee; | |
23 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
24 | use IEEE.numeric_std.all; |
|
24 | use IEEE.numeric_std.all; | |
25 |
|
25 | |||
26 | entity RAM_CEL is |
|
26 | entity RAM_CEL is | |
27 | port( WD : in std_logic_vector(15 downto 0); RD : out |
|
27 | generic(DataSz : integer range 1 to 32 := 8; | |
28 | std_logic_vector(15 downto 0);WEN, REN : in std_logic; |
|
28 | abits : integer range 2 to 12 := 8); | |
29 |
|
|
29 | port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out | |
30 |
std_logic_vector( |
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30 | std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic; | |
|
31 | WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in | |||
|
32 | std_logic_vector(abits-1 downto 0);RWCLK, RESET : in std_logic | |||
31 | ) ; |
|
33 | ) ; | |
32 | end RAM_CEL; |
|
34 | end RAM_CEL; | |
33 |
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35 | |||
34 |
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36 | |||
35 |
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37 | |||
36 | architecture ar_RAM_CEL of RAM_CEL is |
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38 | architecture ar_RAM_CEL of RAM_CEL is | |
37 | type RAMarrayT is array (0 to 255) of std_logic_vector(15 downto 0); |
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39 | ||
38 | signal RAMarray : RAMarrayT:=(others => X"0000"); |
|
40 | constant VectInit : std_logic_vector(DataSz-1 downto 0):=(others => '0'); | |
39 | signal RD_int : std_logic_vector(15 downto 0); |
|
41 | constant MAX : integer := 2**(abits); | |
|
42 | ||||
|
43 | type RAMarrayT is array (0 to MAX-1) of std_logic_vector(DataSz-1 downto 0); | |||
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44 | ||||
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45 | signal RAMarray : RAMarrayT:=(others => VectInit); | |||
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46 | signal RD_int : std_logic_vector(DataSz-1 downto 0); | |||
40 |
|
47 | |||
41 | begin |
|
48 | begin | |
42 |
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49 | |||
@@ -46,8 +53,8 RD_int <= RAMarray(to_integer(unsigned | |||||
46 | process(RWclk,reset) |
|
53 | process(RWclk,reset) | |
47 | begin |
|
54 | begin | |
48 | if reset = '0' then |
|
55 | if reset = '0' then | |
49 | RD <= (X"0000"); |
|
56 | RD <= VectInit; | |
50 |
rst:for i in 0 to |
|
57 | rst:for i in 0 to MAX-1 loop | |
51 | RAMarray(i) <= (others => '0'); |
|
58 | RAMarray(i) <= (others => '0'); | |
52 | end loop; |
|
59 | end loop; | |
53 |
|
60 |
@@ -204,17 +204,15 PACKAGE iir_filter IS | |||||
204 | ) ; |
|
204 | ) ; | |
205 | END COMPONENT; |
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205 | END COMPONENT; | |
206 |
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206 | |||
207 |
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|
207 | COMPONENT RAM_CEL is | |
208 | GENERIC ( |
|
208 | generic(DataSz : integer range 1 to 32 := 8; | |
209 | Sample_SZ : INTEGER); |
|
209 | abits : integer range 2 to 12 := 8); | |
210 | PORT ( |
|
210 | port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out | |
211 | WD : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); |
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211 | std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic; | |
212 | RD : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); |
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212 | WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in | |
213 | WEN, REN : IN STD_LOGIC; |
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213 | std_logic_vector(abits-1 downto 0);RWCLK, RESET : in std_logic | |
214 | WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
214 | ) ; | |
215 | RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
215 | end COMPONENT; | |
216 | RWCLK, RESET : IN STD_LOGIC); |
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|||
217 | END COMPONENT; |
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|||
218 |
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216 | |||
219 | COMPONENT RAM_CEL_N |
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217 | COMPONENT RAM_CEL_N | |
220 | GENERIC ( |
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218 | GENERIC ( |
@@ -57,21 +57,29 signal Matrix_Param : std_logic_vect | |||||
57 | signal Write_reg : std_logic; |
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57 | signal Write_reg : std_logic; | |
58 | signal Data_cpt : integer; |
|
58 | signal Data_cpt : integer; | |
59 | signal MAX : integer; |
|
59 | signal MAX : integer; | |
|
60 | signal pong_reg : std_logic; | |||
60 |
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61 | |||
|
62 | type etat is (idle0,idle1,pong0,pong1); | |||
|
63 | signal ect : etat; | |||
61 |
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64 | |||
62 | begin |
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65 | begin | |
63 |
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66 | |||
64 | process (clkm,rstn) |
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67 | process (clkm,rstn) | |
65 | begin |
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68 | begin | |
66 | if(rstn='0')then |
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69 | if(rstn='0')then | |
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70 | ect <= idle0; | |||
67 | Valid <= '0'; |
|
71 | Valid <= '0'; | |
|
72 | pong_reg <= '0'; | |||
|
73 | header_val <= '0'; | |||
|
74 | header(5 downto 0) <= (others => '0'); | |||
68 | Write_reg <= '0'; |
|
75 | Write_reg <= '0'; | |
69 | Data_cpt <= 0; |
|
76 | Data_cpt <= 0; | |
70 |
MAX <= |
|
77 | MAX <= 128; | |
71 |
|
78 | |||
72 |
|
79 | |||
73 | elsif(clkm' event and clkm='1')then |
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80 | elsif(clkm' event and clkm='1')then | |
74 | Write_reg <= Matrix_Write; |
|
81 | Write_reg <= Matrix_Write; | |
|
82 | pong_reg <= pong; | |||
75 |
|
83 | |||
76 | if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then |
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84 | if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then | |
77 | MAX <= 128; |
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85 | MAX <= 128; | |
@@ -79,33 +87,102 begin | |||||
79 | MAX <= 256; |
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87 | MAX <= 256; | |
80 | end if; |
|
88 | end if; | |
81 |
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89 | |||
|
90 | -- if(Write_reg = '0' and Matrix_Write = '1')then | |||
|
91 | -- if(Data_cpt = MAX)then | |||
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92 | -- Data_cpt <= 0; | |||
|
93 | -- Valid <= '1'; | |||
|
94 | -- header_val <= '1'; | |||
|
95 | -- else | |||
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96 | -- Data_cpt <= Data_cpt + 1; | |||
|
97 | -- Valid <= '0'; | |||
|
98 | -- end if; | |||
|
99 | -- end if; | |||
|
100 | ||||
82 | if(Write_reg = '0' and Matrix_Write = '1')then |
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101 | if(Write_reg = '0' and Matrix_Write = '1')then | |
83 |
|
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102 | Data_cpt <= Data_cpt + 1; | |
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103 | Valid <= '0'; | |||
|
104 | elsif(Data_cpt = MAX)then | |||
84 |
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105 | Data_cpt <= 0; | |
85 |
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106 | Valid <= '1'; | |
86 |
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107 | header_val <= '1'; | |
87 |
|
|
108 | else | |
88 | Data_cpt <= Data_cpt + 1; |
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|||
89 |
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109 | Valid <= '0'; | |
90 |
|
|
110 | end if; | |
91 | end if; |
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|||
92 |
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111 | |||
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112 | -- if(header_ack = '1')then | |||
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113 | -- header_val <= '0'; | |||
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114 | -- end if; | |||
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115 | ||||
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116 | -- if(emptyIN = "10")then | |||
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117 | -- ping <= '0'; | |||
|
118 | -- elsif(emptyIN = "01")then | |||
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119 | -- ping <= '1'; | |||
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120 | -- else | |||
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121 | -- ping <= ping; | |||
|
122 | -- end if; | |||
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123 | ||||
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124 | ||||
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125 | case ect is | |||
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126 | ||||
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127 | when idle0 => | |||
93 | if(header_ack = '1')then |
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128 | if(header_ack = '1')then | |
94 | header_val <= '0'; |
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129 | header_val <= '0'; | |
|
130 | --if(pong = '1')then | |||
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131 | ect <= pong0; | |||
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132 | --elsif(pong = '0')then | |||
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133 | --ect <= pong1; | |||
|
134 | --end if; | |||
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135 | end if; | |||
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136 | ||||
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137 | when pong0 => | |||
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138 | header(1 downto 0) <= Matrix_Type; | |||
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139 | header(5 downto 2) <= Matrix_Param; | |||
|
140 | if(emptyIN(0) = '1')then | |||
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141 | ect <= idle1; | |||
95 | end if; |
|
142 | end if; | |
96 |
|
143 | |||
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144 | when idle1 => | |||
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145 | if(header_ack = '1')then | |||
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146 | header_val <= '0'; | |||
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147 | ect <= pong1; | |||
|
148 | end if; | |||
|
149 | ||||
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150 | when pong1 => | |||
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151 | header(1 downto 0) <= Matrix_Type; | |||
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152 | header(5 downto 2) <= Matrix_Param; | |||
|
153 | if(emptyIN(1) = '1')then | |||
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154 | ect <= idle0; | |||
|
155 | end if; | |||
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156 | ||||
|
157 | end case; | |||
97 | end if; |
|
158 | end if; | |
98 | end process; |
|
159 | end process; | |
99 |
|
160 | |||
100 | Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4)); |
|
161 | Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4)); | |
101 |
|
162 | |||
102 | header(1 downto 0) <= Matrix_Type; |
|
163 | --header(1 downto 0) <= Matrix_Type; | |
103 | header(5 downto 2) <= Matrix_Param; |
|
164 | --header(5 downto 2) <= Matrix_Param; | |
104 | header(31 downto 6) <= (others => '0'); |
|
165 | header(31 downto 6) <= (others => '0'); | |
105 |
|
166 | |||
106 | dataOUT <= dataIN(Data_sz-1 downto 0) when pong = '0' else dataIN((2*Data_sz)-1 downto Data_sz); |
|
167 | with ect select | |
107 | emptyOUT <= emptyIN(0) when pong = '0' else emptyIN(1); |
|
168 | dataOUT <= dataIN(Data_sz-1 downto 0) when pong0, | |
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169 | dataIN(Data_sz-1 downto 0) when idle0, | |||
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170 | dataIN((2*Data_sz)-1 downto Data_sz) when pong1, | |||
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171 | dataIN((2*Data_sz)-1 downto Data_sz) when idle1, | |||
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172 | (others => '0') when others; | |||
108 |
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173 | |||
109 | RenOUT <= '1' & RenIN when pong = '0' else RenIN & '1'; |
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174 | with ect select | |
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175 | emptyOUT <= emptyIN(0) when pong0, | |||
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176 | emptyIN(0) when idle0, | |||
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177 | emptyIN(1) when pong1, | |||
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178 | emptyIN(1) when idle1, | |||
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179 | '1' when others; | |||
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180 | ||||
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181 | with ect select | |||
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182 | RenOUT <= '1' & RenIN when pong0, | |||
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183 | '1' & RenIN when idle0, | |||
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184 | RenIN & '1' when pong1, | |||
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185 | RenIN & '1' when idle1, | |||
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186 | "11" when others; | |||
110 |
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187 | |||
111 | end architecture; No newline at end of file |
|
188 | end architecture; |
@@ -103,6 +103,7 ARCHITECTURE Behavioral OF lpp_dma_ip IS | |||||
103 | ----------------------------------------------------------------------------- |
|
103 | ----------------------------------------------------------------------------- | |
104 | ----------------------------------------------------------------------------- |
|
104 | ----------------------------------------------------------------------------- | |
105 | TYPE state_DMAWriteBurst IS (IDLE, |
|
105 | TYPE state_DMAWriteBurst IS (IDLE, | |
|
106 | CHECK_COMPONENT_TYPE, | |||
106 | TRASH_FIFO, |
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107 | TRASH_FIFO, | |
107 | WAIT_HEADER_ACK, |
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108 | WAIT_HEADER_ACK, | |
108 | SEND_DATA, |
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109 | SEND_DATA, | |
@@ -182,8 +183,7 BEGIN | |||||
182 | END PROCESS debug_info; |
|
183 | END PROCESS debug_info; | |
183 |
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184 | |||
184 |
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185 | |||
185 | matrix_type <= header(1 DOWNTO 0); |
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186 | ||
186 | component_type <= header(5 DOWNTO 2); |
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|||
187 |
|
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187 | ||
188 |
|
|
188 | send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE | |
189 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE |
|
189 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE | |
@@ -191,8 +191,8 BEGIN | |||||
191 | '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE |
|
191 | '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE | |
192 | '0'; |
|
192 | '0'; | |
193 |
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193 | |||
194 | header_check_ok <= '0' WHEN component_type = "1111" ELSE |
|
194 | header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" | |
195 |
'1' WHEN component_type = "0000" AND component_type_pre = " |
|
195 | '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE | |
196 | '1' WHEN component_type = component_type_pre + "0001" ELSE |
|
196 | '1' WHEN component_type = component_type_pre + "0001" ELSE | |
197 | '0'; |
|
197 | '0'; | |
198 |
|
198 | |||
@@ -208,6 +208,8 BEGIN | |||||
208 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) |
|
208 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) | |
209 | BEGIN -- PROCESS DMAWriteBurst_p |
|
209 | BEGIN -- PROCESS DMAWriteBurst_p | |
210 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
210 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
|
211 | matrix_type <= (others => '0'); | |||
|
212 | component_type <= (others => '0'); | |||
211 | state <= IDLE; |
|
213 | state <= IDLE; | |
212 | header_ack <= '0'; |
|
214 | header_ack <= '0'; | |
213 | ready_matrix_f0_0 <= '0'; |
|
215 | ready_matrix_f0_0 <= '0'; | |
@@ -216,7 +218,7 BEGIN | |||||
216 | ready_matrix_f2 <= '0'; |
|
218 | ready_matrix_f2 <= '0'; | |
217 | error_anticipating_empty_fifo <= '0'; |
|
219 | error_anticipating_empty_fifo <= '0'; | |
218 | error_bad_component_error <= '0'; |
|
220 | error_bad_component_error <= '0'; | |
219 |
component_type_pre <= " |
|
221 | component_type_pre <= "0000"; | |
220 | fifo_ren_trash <= '1'; |
|
222 | fifo_ren_trash <= '1'; | |
221 | component_send <= '0'; |
|
223 | component_send <= '0'; | |
222 | address <= (OTHERS => '0'); |
|
224 | address <= (OTHERS => '0'); | |
@@ -227,6 +229,9 BEGIN | |||||
227 |
|
229 | |||
228 | CASE state IS |
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230 | CASE state IS | |
229 | WHEN IDLE => |
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231 | WHEN IDLE => | |
|
232 | matrix_type <= header(1 DOWNTO 0); | |||
|
233 | --component_type <= header(5 DOWNTO 2); | |||
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234 | ||||
230 | ready_matrix_f0_0 <= '0'; |
|
235 | ready_matrix_f0_0 <= '0'; | |
231 | ready_matrix_f0_1 <= '0'; |
|
236 | ready_matrix_f0_1 <= '0'; | |
232 | ready_matrix_f1 <= '0'; |
|
237 | ready_matrix_f1 <= '0'; | |
@@ -234,9 +239,14 BEGIN | |||||
234 | error_bad_component_error <= '0'; |
|
239 | error_bad_component_error <= '0'; | |
235 | header_select <= '1'; |
|
240 | header_select <= '1'; | |
236 | IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN |
|
241 | IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN | |
|
242 | matrix_type <= header(1 DOWNTO 0); | |||
|
243 | component_type <= header(5 DOWNTO 2); | |||
|
244 | component_type_pre <= component_type; | |||
|
245 | state <= CHECK_COMPONENT_TYPE; | |||
|
246 | END IF; | |||
|
247 | ||||
|
248 | WHEN CHECK_COMPONENT_TYPE => | |||
237 | IF header_check_ok = '1' THEN |
|
249 | IF header_check_ok = '1' THEN | |
238 | header_data <= header; |
|
|||
239 | component_type_pre <= header(5 DOWNTO 2); |
|
|||
240 | header_ack <= '1'; |
|
250 | header_ack <= '1'; | |
241 | -- |
|
251 | -- | |
242 | header_send <= '1'; |
|
252 | header_send <= '1'; | |
@@ -248,13 +258,14 BEGIN | |||||
248 | state <= WAIT_HEADER_ACK; |
|
258 | state <= WAIT_HEADER_ACK; | |
249 | ELSE |
|
259 | ELSE | |
250 | error_bad_component_error <= '1'; |
|
260 | error_bad_component_error <= '1'; | |
251 |
component_type_pre <= " |
|
261 | component_type_pre <= "0000"; | |
252 | header_ack <= '1'; |
|
262 | header_ack <= '1'; | |
253 | state <= TRASH_FIFO; |
|
263 | state <= TRASH_FIFO; | |
254 | END IF; |
|
264 | END IF; | |
255 | END IF; |
|
265 | ||
256 |
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266 | |||
257 | WHEN TRASH_FIFO => |
|
267 | WHEN TRASH_FIFO => | |
|
268 | header_ack <= '0'; | |||
258 | error_bad_component_error <= '0'; |
|
269 | error_bad_component_error <= '0'; | |
259 | error_anticipating_empty_fifo <= '0'; |
|
270 | error_anticipating_empty_fifo <= '0'; | |
260 | IF fifo_empty = '1' THEN |
|
271 | IF fifo_empty = '1' THEN | |
@@ -265,6 +276,7 BEGIN | |||||
265 | END IF; |
|
276 | END IF; | |
266 |
|
277 | |||
267 | WHEN WAIT_HEADER_ACK => |
|
278 | WHEN WAIT_HEADER_ACK => | |
|
279 | header_ack <= '0'; | |||
268 | header_send <= '0'; |
|
280 | header_send <= '0'; | |
269 | IF header_send_ko = '1' THEN |
|
281 | IF header_send_ko = '1' THEN | |
270 | state <= TRASH_FIFO; |
|
282 | state <= TRASH_FIFO; | |
@@ -279,7 +291,7 BEGIN | |||||
279 | WHEN SEND_DATA => |
|
291 | WHEN SEND_DATA => | |
280 | IF fifo_empty = '1' THEN |
|
292 | IF fifo_empty = '1' THEN | |
281 | state <= IDLE; |
|
293 | state <= IDLE; | |
282 | IF component_type = "1110" THEN |
|
294 | IF component_type = "1110" THEN --"1110" -- JC | |
283 | CASE matrix_type IS |
|
295 | CASE matrix_type IS | |
284 | WHEN "00" => ready_matrix_f0_0 <= '1'; |
|
296 | WHEN "00" => ready_matrix_f0_0 <= '1'; | |
285 | WHEN "01" => ready_matrix_f0_1 <= '1'; |
|
297 | WHEN "01" => ready_matrix_f0_1 <= '1'; | |
@@ -287,6 +299,7 BEGIN | |||||
287 | WHEN "11" => ready_matrix_f2 <= '1'; |
|
299 | WHEN "11" => ready_matrix_f2 <= '1'; | |
288 | WHEN OTHERS => NULL; |
|
300 | WHEN OTHERS => NULL; | |
289 | END CASE; |
|
301 | END CASE; | |
|
302 | ||||
290 | END IF; |
|
303 | END IF; | |
291 | ELSE |
|
304 | ELSE | |
292 | component_send <= '1'; |
|
305 | component_send <= '1'; |
@@ -33,7 +33,7 library lpp; | |||||
33 | use lpp.lpp_amba.all; |
|
33 | use lpp.lpp_amba.all; | |
34 | use lpp.apb_devices_list.all; |
|
34 | use lpp.apb_devices_list.all; | |
35 | use lpp.lpp_memory.all; |
|
35 | use lpp.lpp_memory.all; | |
36 |
|
36 | use lpp.iir_filter.all; | ||
37 |
|
37 | |||
38 | entity APB_FIFO is |
|
38 | entity APB_FIFO is | |
39 | generic ( |
|
39 | generic ( | |
@@ -47,6 +47,7 generic ( | |||||
47 | Data_sz : integer := 16; |
|
47 | Data_sz : integer := 16; | |
48 | Addr_sz : integer := 9; |
|
48 | Addr_sz : integer := 9; | |
49 | Enable_ReUse : std_logic := '0'; |
|
49 | Enable_ReUse : std_logic := '0'; | |
|
50 | Mem_use : integer := use_RAM; | |||
50 | R : integer := 1; |
|
51 | R : integer := 1; | |
51 | W : integer := 1 |
|
52 | W : integer := 1 | |
52 | ); |
|
53 | ); | |
@@ -175,7 +176,7 Full <= sFull; | |||||
175 |
|
176 | |||
176 | fifos: for i in 0 to FifoCnt-1 generate |
|
177 | fifos: for i in 0 to FifoCnt-1 generate | |
177 | FIFO0 : lpp_fifo |
|
178 | FIFO0 : lpp_fifo | |
178 | generic map (tech,Enable_ReUse,Data_sz,Addr_sz) |
|
179 | generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz) | |
179 | port map(rst,sReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i)); |
|
180 | port map(rst,sReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i)); | |
180 | end generate; |
|
181 | end generate; | |
181 |
|
182 |
@@ -24,12 +24,14 use IEEE.std_logic_1164.all; | |||||
24 | use IEEE.numeric_std.all; |
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24 | use IEEE.numeric_std.all; | |
25 | library lpp; |
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25 | library lpp; | |
26 | use lpp.lpp_memory.all; |
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26 | use lpp.lpp_memory.all; | |
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27 | use lpp.iir_filter.all; | |||
27 | library techmap; |
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28 | library techmap; | |
28 | use techmap.gencomp.all; |
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29 | use techmap.gencomp.all; | |
29 |
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30 | |||
30 | entity lppFIFOxN is |
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31 | entity lppFIFOxN is | |
31 | generic( |
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32 | generic( | |
32 | tech : integer := 0; |
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33 | tech : integer := 0; | |
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34 | Mem_use : integer := use_RAM; | |||
33 | Data_sz : integer range 1 to 32 := 8; |
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35 | Data_sz : integer range 1 to 32 := 8; | |
34 | Addr_sz : integer range 1 to 32 := 8; |
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36 | Addr_sz : integer range 1 to 32 := 8; | |
35 | FifoCnt : integer := 1; |
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37 | FifoCnt : integer := 1; | |
@@ -56,7 +58,7 begin | |||||
56 |
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58 | |||
57 | fifos: for i in 0 to FifoCnt-1 generate |
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59 | fifos: for i in 0 to FifoCnt-1 generate | |
58 | FIFO0 : lpp_fifo |
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60 | FIFO0 : lpp_fifo | |
59 | generic map (tech,Enable_ReUse,Data_sz,Addr_sz) |
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61 | generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz) | |
60 | port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open); |
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62 | port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open); | |
61 | end generate; |
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63 | end generate; | |
62 |
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64 |
@@ -31,6 +31,7 use techmap.gencomp.all; | |||||
31 | entity lpp_fifo is |
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31 | entity lpp_fifo is | |
32 | generic( |
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32 | generic( | |
33 | tech : integer := 0; |
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33 | tech : integer := 0; | |
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34 | Mem_use : integer := use_RAM; | |||
34 | Enable_ReUse : std_logic := '0'; |
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35 | Enable_ReUse : std_logic := '0'; | |
35 | DataSz : integer range 1 to 32 := 8; |
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36 | DataSz : integer range 1 to 32 := 8; | |
36 | abits : integer range 2 to 12 := 8 |
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37 | abits : integer range 2 to 12 := 8 | |
@@ -75,12 +76,17 begin | |||||
75 | -- /!\ syncram_2p Write et Read actif a l'�tat haut /!\ |
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76 | -- /!\ syncram_2p Write et Read actif a l'�tat haut /!\ | |
76 | -- A l'inverse de RAM_CEL !!! |
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77 | -- A l'inverse de RAM_CEL !!! | |
77 | --================================================================================== |
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78 | --================================================================================== | |
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79 | memRAM : IF Mem_use = use_RAM GENERATE | |||
78 | SRAM : syncram_2p |
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80 | SRAM : syncram_2p | |
79 | generic map(tech,abits,DataSz) |
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81 | generic map(tech,abits,DataSz) | |
80 | port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata); |
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82 | port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata); | |
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83 | END GENERATE; | |||
81 | --================================================================================== |
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84 | --================================================================================== | |
82 | --RAM0: entity work.RAM_CEL |
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85 | memCEL : IF Mem_use = use_CEL GENERATE | |
83 | -- port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn); |
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86 | CRAM : RAM_CEL | |
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87 | generic map(DataSz,abits) | |||
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88 | port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn); | |||
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89 | END GENERATE; | |||
84 | --================================================================================== |
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90 | --================================================================================== | |
85 |
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91 | |||
86 | --============================= |
|
92 | --============================= |
@@ -26,6 +26,7 use grlib.amba.all; | |||||
26 | use std.textio.all; |
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26 | use std.textio.all; | |
27 | library lpp; |
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27 | library lpp; | |
28 | use lpp.lpp_amba.all; |
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28 | use lpp.lpp_amba.all; | |
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29 | use lpp.iir_filter.all; | |||
29 | library gaisler; |
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30 | library gaisler; | |
30 | use gaisler.misc.all; |
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31 | use gaisler.misc.all; | |
31 | use gaisler.memctrl.all; |
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32 | use gaisler.memctrl.all; | |
@@ -48,6 +49,7 generic ( | |||||
48 | Data_sz : integer := 16; |
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49 | Data_sz : integer := 16; | |
49 | Addr_sz : integer := 9; |
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50 | Addr_sz : integer := 9; | |
50 | Enable_ReUse : std_logic := '0'; |
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51 | Enable_ReUse : std_logic := '0'; | |
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52 | Mem_use : integer := use_RAM; | |||
51 | R : integer := 1; |
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53 | R : integer := 1; | |
52 | W : integer := 1 |
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54 | W : integer := 1 | |
53 | ); |
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55 | ); | |
@@ -74,6 +76,7 end component; | |||||
74 | component lpp_fifo is |
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76 | component lpp_fifo is | |
75 | generic( |
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77 | generic( | |
76 | tech : integer := 0; |
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78 | tech : integer := 0; | |
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79 | Mem_use : integer := use_RAM; | |||
77 | Enable_ReUse : std_logic := '0'; |
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80 | Enable_ReUse : std_logic := '0'; | |
78 | DataSz : integer range 1 to 32 := 8; |
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81 | DataSz : integer range 1 to 32 := 8; | |
79 | abits : integer range 2 to 12 := 8 |
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82 | abits : integer range 2 to 12 := 8 | |
@@ -98,6 +101,7 end component; | |||||
98 | component lppFIFOxN is |
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101 | component lppFIFOxN is | |
99 | generic( |
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102 | generic( | |
100 | tech : integer := 0; |
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103 | tech : integer := 0; | |
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104 | Mem_use : integer := use_RAM; | |||
101 | Data_sz : integer range 1 to 32 := 8; |
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105 | Data_sz : integer range 1 to 32 := 8; | |
102 | Addr_sz : integer range 1 to 32 := 8; |
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106 | Addr_sz : integer range 1 to 32 := 8; | |
103 | FifoCnt : integer := 1; |
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107 | FifoCnt : integer := 1; | |
@@ -117,35 +121,17 port( | |||||
117 | ); |
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121 | ); | |
118 | end component; |
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122 | end component; | |
119 |
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123 | |||
120 |
component |
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124 | component FillFifo is | |
121 | generic( |
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125 | generic( | |
122 | tech : integer := 0; |
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|||
123 |
Data_sz |
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126 | Data_sz : integer range 1 to 32 := 16; | |
124 |
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127 | Fifo_cnt : integer range 1 to 8 := 5 | |
125 | Enable_ReUse : std_logic := '0' |
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|||
126 | ); |
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128 | ); | |
127 | port( |
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129 | port( | |
128 | rst : in std_logic; |
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129 | wclk : in std_logic; |
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130 | rclk : in std_logic; |
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131 | ReUse : in std_logic_vector(4 downto 0); |
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132 | wen : in std_logic_vector(4 downto 0); |
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133 | ren : in std_logic_vector(4 downto 0); |
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134 | wdata : in std_logic_vector((5*Data_sz)-1 downto 0); |
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135 | rdata : out std_logic_vector((5*Data_sz)-1 downto 0); |
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136 | full : out std_logic_vector(4 downto 0); |
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137 | empty : out std_logic_vector(4 downto 0) |
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138 | ); |
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|||
139 | end component; |
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140 |
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||||
141 | component Bridge is |
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142 | port( |
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143 |
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130 | clk : in std_logic; | |
144 |
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131 | raz : in std_logic; | |
145 | EmptyUp : in std_logic; |
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132 | write : out std_logic_vector(Fifo_cnt-1 downto 0); | |
146 | FullDwn : in std_logic; |
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133 | reuse : out std_logic_vector(Fifo_cnt-1 downto 0); | |
147 | WriteDwn : out std_logic; |
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134 | data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0) | |
148 | ReadUp : out std_logic |
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|||
149 | ); |
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135 | ); | |
150 | end component; |
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136 | end component; | |
151 |
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137 |
@@ -11,7 +11,8 USE techmap.gencomp.ALL; | |||||
11 |
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11 | |||
12 | ENTITY lpp_top_acq IS |
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12 | ENTITY lpp_top_acq IS | |
13 | GENERIC( |
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13 | GENERIC( | |
14 | tech : INTEGER := 0 |
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14 | tech : INTEGER := 0; | |
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15 | Mem_use : integer := use_RAM | |||
15 | ); |
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16 | ); | |
16 | PORT ( |
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17 | PORT ( | |
17 | -- ADS7886 |
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18 | -- ADS7886 | |
@@ -143,7 +144,7 BEGIN | |||||
143 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 |
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144 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 | |
144 | GENERIC MAP ( |
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145 | GENERIC MAP ( | |
145 | tech => 0, |
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146 | tech => 0, | |
146 |
Mem_use => use |
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147 | Mem_use => Mem_use, | |
147 | Sample_SZ => 18, |
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148 | Sample_SZ => 18, | |
148 | Coef_SZ => Coef_SZ, |
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149 | Coef_SZ => Coef_SZ, | |
149 | Coef_Nb => 25, -- TODO |
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150 | Coef_Nb => 25, -- TODO |
@@ -16,7 +16,8 PACKAGE lpp_top_lfr_pkg IS | |||||
16 |
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16 | |||
17 | COMPONENT lpp_top_acq |
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17 | COMPONENT lpp_top_acq | |
18 | GENERIC( |
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18 | GENERIC( | |
19 | tech : INTEGER := 0 |
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19 | tech : INTEGER := 0; | |
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20 | Mem_use : integer := use_RAM | |||
20 | ); |
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21 | ); | |
21 | PORT ( |
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22 | PORT ( | |
22 | -- ADS7886 |
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23 | -- ADS7886 |
1 | NO CONTENT: file was removed |
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NO CONTENT: file was removed |
1 | NO CONTENT: file was removed |
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NO CONTENT: file was removed |
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