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Working bbone GPMC_interface interface
Jeandet Alexis -
r282:252bd09e4210 alexis
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1 library ieee;
1 library ieee;
2 use ieee.std_logic_1164.all;
2 use ieee.std_logic_1164.all;
3 use IEEE.numeric_std.all;
3 use IEEE.numeric_std.all;
4 library grlib, techmap;
4 library grlib, techmap;
5 use grlib.amba.all;
5 use grlib.amba.all;
6 use grlib.amba.all;
6 use grlib.amba.all;
7 use grlib.stdlib.all;
7 use grlib.stdlib.all;
8 use techmap.gencomp.all;
8 use techmap.gencomp.all;
9 use techmap.allclkgen.all;
9 use techmap.allclkgen.all;
10 library gaisler;
10 library gaisler;
11 use gaisler.memctrl.all;
11 use gaisler.memctrl.all;
12 use gaisler.leon3.all;
12 use gaisler.leon3.all;
13 use gaisler.uart.all;
13 use gaisler.uart.all;
14 use gaisler.misc.all;
14 use gaisler.misc.all;
15 library esa;
15 library esa;
16 use esa.memoryctrl.all;
16 use esa.memoryctrl.all;
17 --use gaisler.sim.all;
17 --use gaisler.sim.all;
18 library lpp;
18 library lpp;
19 use lpp.lpp_ad_conv.all;
19 use lpp.lpp_ad_conv.all;
20 use lpp.lpp_amba.all;
20 use lpp.lpp_amba.all;
21 use lpp.apb_devices_list.all;
21 use lpp.apb_devices_list.all;
22 use lpp.general_purpose.all;
22 use lpp.general_purpose.all;
23 use lpp.lpp_cna.all;
23 use lpp.lpp_cna.all;
24
24
25 Library UNISIM;
25 Library UNISIM;
26 use UNISIM.vcomponents.all;
26 use UNISIM.vcomponents.all;
27
27
28
28
29 use work.config.all;
29 use work.config.all;
30 --==================================================================
30 --==================================================================
31 --
31 --
32 --
32 --
33 -- FPGA FREQ = 100MHz
33 -- FPGA FREQ = 100MHz
34 --
34 --
35 --
35 --
36 --==================================================================
36 --==================================================================
37
37
38 entity BeagleSynth is
38 entity BeagleSynth is
39 generic (
39 generic (
40 fabtech : integer := CFG_FABTECH;
40 fabtech : integer := CFG_FABTECH;
41 memtech : integer := CFG_MEMTECH;
41 memtech : integer := CFG_MEMTECH;
42 padtech : integer := CFG_PADTECH;
42 padtech : integer := CFG_PADTECH;
43 clktech : integer := CFG_CLKTECH
43 clktech : integer := CFG_CLKTECH
44 );
44 );
45 port (
45 port (
46 reset : in std_ulogic;
46 reset : in std_ulogic;
47 clk : in std_ulogic;
47 clk : in std_ulogic;
48 DAC_nCLR : out std_ulogic;
48 DAC_nCLR : out std_ulogic;
49 DAC_nCS : out std_ulogic;
49 DAC_nCS : out std_ulogic;
50 CAL_IN_SCK : out std_ulogic;
50 CAL_IN_SCK : out std_ulogic;
51 DAC_SDI : out std_logic_vector(7 downto 0);
51 DAC_SDI : out std_logic_vector(7 downto 0);
52 TXD : out std_ulogic;
52 TXD : out std_ulogic;
53 RXD : in std_ulogic;
53 RXD : in std_ulogic;
54 urxd1 : in std_ulogic;
54 urxd1 : in std_ulogic;
55 utxd1 : out std_ulogic;
55 utxd1 : out std_ulogic;
56 LED : out std_ulogic_vector(2 downto 0);
56 LED : out std_ulogic_vector(2 downto 0);
57 --------------------------------------------------------
57 --------------------------------------------------------
58 ---- Beaglebone GPMC
58 ---- Beaglebone GPMC
59 --------------------------------------------------------
59 --------------------------------------------------------
60 GPMC_AD : inout std_logic_vector(15 downto 0);
60 GPMC_AD : inout std_logic_vector(15 downto 0);
61 GPMC_A : in std_logic_vector(19 downto 0);
61 GPMC_A : in std_logic_vector(19 downto 0);
62 GPMC_CLK_MUX0 : in std_logic;
62 GPMC_CLK_MUX0 : in std_logic;
63 GPMC_WEN : in std_logic;
63 GPMC_WEN : in std_logic;
64 GPMC_OEN_REN : in std_logic;
64 GPMC_OEN_REN : in std_logic;
65 GPMC_ADVN_ALE : in std_logic;
65 GPMC_ADVN_ALE : in std_logic;
66 GPMC_CSN : in std_logic_vector(2 downto 0);
66 GPMC_CSN : in std_logic_vector(2 downto 0);
67 GPMC_BE0N_CLE : in std_logic;
67 GPMC_BE0N_CLE : in std_logic;
68 GPMC_BE1N : in std_logic;
68 GPMC_BE1N : in std_logic;
69 GPMC_WAIT0 : out std_logic;
69 GPMC_WAIT0 : out std_logic;
70 GPMC_WPN : in std_logic;
70 GPMC_WPN : in std_logic;
71
71
72 --------------------------------------------------------
72 --------------------------------------------------------
73 ---- SDRAM
73 ---- SDRAM
74 ---- For SDRAM config have a look on leon3-altera-ep1c20
74 ---- For SDRAM config have a look on leon3-altera-ep1c20
75 ---- design from GRLIB, the IS42S32400E is similar to
75 ---- design from GRLIB, the IS42S32400E is similar to
76 ---- MT48LC4M32B2.
76 ---- MT48LC4M32B2.
77 --------------------------------------------------------
77 --------------------------------------------------------
78 sdcke : out std_logic; -- clk en
78 sdcke : out std_logic; -- clk en
79 sdcsn : out std_logic; -- chip sel
79 sdcsn : out std_logic; -- chip sel
80 sdwen : out std_logic; -- write en
80 sdwen : out std_logic; -- write en
81 sdrasn : out std_logic; -- row addr stb
81 sdrasn : out std_logic; -- row addr stb
82 sdcasn : out std_logic; -- col addr stb
82 sdcasn : out std_logic; -- col addr stb
83 sddqm : out std_logic_vector (3 downto 0); -- data i/o mask
83 sddqm : out std_logic_vector (3 downto 0); -- data i/o mask
84 sdclk : out std_logic; -- sdram clk output
84 sdclk : out std_logic; -- sdram clk output
85 sdba : out std_logic_vector (1 downto 0); -- bank select address
85 sdba : out std_logic_vector (1 downto 0); -- bank select address
86 Address : out std_logic_vector(11 downto 0); -- sdram address
86 Address : out std_logic_vector(11 downto 0); -- sdram address
87 Data : inout std_logic_vector(31 downto 0) -- optional sdram data
87 Data : inout std_logic_vector(31 downto 0) -- optional sdram data
88 );
88 );
89 end;
89 end;
90
90
91 architecture rtl of BeagleSynth is
91 architecture rtl of BeagleSynth is
92 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
92 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
93 CFG_GRETH+CFG_AHB_JTAG;
93 CFG_GRETH+CFG_AHB_JTAG;
94 constant maxahbm : integer := maxahbmsp;
94 constant maxahbm : integer := maxahbmsp;
95 constant IOAEN : integer := CFG_CAN;
95 constant IOAEN : integer := CFG_CAN;
96 constant boardfreq : integer := 100000;
96 constant boardfreq : integer := 100000;
97
97
98 signal clk2x : std_ulogic;
98 signal clk2x : std_ulogic;
99 signal lclk : std_ulogic;
99 signal lclk : std_ulogic;
100 signal clkm : std_ulogic;
100 signal clkm : std_ulogic;
101 signal rstn : std_ulogic;
101 signal rstn : std_ulogic;
102 signal rst : std_ulogic;
102 signal rst : std_ulogic;
103 signal rstraw : std_ulogic;
103 signal rstraw : std_ulogic;
104 signal pciclk : std_ulogic;
104 signal pciclk : std_ulogic;
105 signal sdclkl : std_ulogic;
105 signal sdclkl : std_ulogic;
106 signal sdclkl_DDR2 : std_ulogic;
106 signal sdclkl_DDR2 : std_ulogic;
107 signal cgi : clkgen_in_type;
107 signal cgi : clkgen_in_type;
108 signal cgo : clkgen_out_type;
108 signal cgo : clkgen_out_type;
109
109
110
110
111 signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0);
111 signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0);
112 signal smpclk : std_logic;
112 signal smpclk : std_logic;
113 signal smpclk_reg : std_logic;
113 signal smpclk_reg : std_logic;
114 signal DAC_SDO : std_logic;
114 signal DAC_SDO : std_logic;
115
115
116 signal GPMC_SLAVE_STATUS : std_logic_vector(15 downto 0);
116 signal GPMC_SLAVE_STATUS : std_logic_vector(15 downto 0);
117 signal GPMC_SLAVE_DATA : std_logic_vector(15 downto 0);
117 signal GPMC_SLAVE_DATA : std_logic_vector(15 downto 0);
118 signal GPMC_SLAVE_ADDRESS : std_logic_vector(19 downto 0);
118 signal GPMC_SLAVE_ADDRESS : std_logic_vector(19 downto 0);
119 signal GPMC_SLAVE_WEN : std_logic;
119 signal GPMC_SLAVE_WEN : std_logic;
120
120
121 signal gpmc_clk : std_logic;
121 signal gpmc_clk : std_logic;
122
122
123 attribute keep : boolean;
123 attribute keep : boolean;
124 attribute syn_keep : boolean;
124 attribute syn_keep : boolean;
125 attribute syn_preserve : boolean;
125 attribute syn_preserve : boolean;
126 attribute syn_keep of clkm : signal is true;
126 attribute syn_keep of clkm : signal is true;
127 attribute syn_preserve of clkm : signal is true;
127 attribute syn_preserve of clkm : signal is true;
128 attribute keep of clkm : signal is true;
128 attribute keep of clkm : signal is true;
129 begin
129 begin
130
130
131 DAC_nCLR <= '1';
131 DAC_nCLR <= '1';
132
132
133
133
134 resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
134 resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
135 rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw);
135 rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw);
136
136
137 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk);
137 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk);
138
138
139 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
139 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
140 clkgen0 : clkgen -- clock generator
140 clkgen0 : clkgen -- clock generator
141 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq)
141 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq)
142 port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open);
142 port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open);
143
143
144
144
145 DAC0 : entity work.beagleSigGen
145 DAC0 : entity work.beagleSigGen
146 generic map(
146 generic map(
147 memtech,
147 memtech,
148 padtech,
148 padtech,
149 clktech
149 clktech
150 )
150 )
151 Port map(
151 Port map(
152 clk => clkm,
152 clk => clkm,
153 rstn => rstn,
153 rstn => rstn,
154 CAL_IN_SCK => CAL_IN_SCK,
154 CAL_IN_SCK => CAL_IN_SCK,
155 DAC_nCS => DAC_nCS,
155 DAC_nCS => DAC_nCS,
156 DAC_SDI => DAC_SDI,
156 DAC_SDI => DAC_SDI,
157 address => GPMC_SLAVE_ADDRESS(3 downto 1),
157 address => GPMC_SLAVE_ADDRESS(19 downto 1),
158 DATA => GPMC_SLAVE_DATA,
158 DATA => GPMC_SLAVE_DATA,
159 WEN => GPMC_SLAVE_WEN,
159 WEN => GPMC_SLAVE_WEN,
160 REN_debug => open,
160 REN_debug => open,
161 FIFO_FULL => GPMC_SLAVE_STATUS(7 downto 0),
161 FIFO_FULL => GPMC_SLAVE_STATUS(7 downto 0),
162 FIFO_EMPTY => GPMC_SLAVE_STATUS(15 downto 8)
162 FIFO_EMPTY => GPMC_SLAVE_STATUS(15 downto 8)
163 );
163 );
164
164
165
165
166
166
167 --LED(0) <= GPMC_SLAVE_ADDRESS(1);
167 LED(0) <= GPMC_SLAVE_STATUS(0);
168 --LED(1) <= GPMC_SLAVE_ADDRESS(2);
168 LED(1) <= GPMC_SLAVE_STATUS(8);
169 LED(2) <= GPMC_SLAVE_WEN;
169 LED(2) <= GPMC_SLAVE_WEN;
170
170
171 gpmc_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (GPMC_CLK_MUX0, gpmc_clk);
171 gpmc_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (GPMC_CLK_MUX0, gpmc_clk);
172 GPMCS0: entity work.GPMC_SLAVE
172 GPMCS0: entity work.GPMC_SLAVE
173 generic map(memtech,padtech)
173 generic map(memtech,padtech)
174 Port map(
174 Port map(
175 clk => clkm,
175 clk => clkm,
176 reset => rstn,
176 reset => rstn,
177 STATUS => GPMC_SLAVE_STATUS,
177 STATUS => GPMC_SLAVE_STATUS,
178 DATA => GPMC_SLAVE_DATA,
178 DATA => GPMC_SLAVE_DATA,
179 ADDRESS => GPMC_SLAVE_ADDRESS,
179 ADDRESS => GPMC_SLAVE_ADDRESS,
180 WEN => GPMC_SLAVE_WEN,
180 WEN => GPMC_SLAVE_WEN,
181 SMP_CKL => LED(0),
181 SMP_CKL => open,
182 SMP_WEN => LED(1),
182 SMP_WEN => open,
183 GPMC_AD => GPMC_AD,
183 GPMC_AD => GPMC_AD,
184 GPMC_A => GPMC_A,
184 GPMC_A => GPMC_A,
185 GPMC_CLK => gpmc_clk,
185 GPMC_CLK => gpmc_clk,
186 GPMC_WEN => GPMC_WEN,
186 GPMC_WEN => GPMC_WEN,
187 GPMC_OEN_REN => GPMC_OEN_REN,
187 GPMC_OEN_REN => GPMC_OEN_REN,
188 GPMC_ADVN_ALE => GPMC_ADVN_ALE,
188 GPMC_ADVN_ALE => GPMC_ADVN_ALE,
189 GPMC_CSN => GPMC_CSN,
189 GPMC_CSN => GPMC_CSN,
190 GPMC_BE0N_CLE => GPMC_BE0N_CLE,
190 GPMC_BE0N_CLE => GPMC_BE0N_CLE,
191 GPMC_BE1N => GPMC_BE1N,
191 GPMC_BE1N => GPMC_BE1N,
192 GPMC_WAIT0 => GPMC_WAIT0,
192 GPMC_WAIT0 => GPMC_WAIT0,
193 GPMC_WPN => GPMC_WPN
193 GPMC_WPN => GPMC_WPN
194 );
194 );
195
195
196 end rtl;
196 end rtl;
197
197
198
198
199
199
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@@ -1,330 +1,243
1 library ieee;
1 library ieee;
2 use ieee.std_logic_1164.all;
2 use ieee.std_logic_1164.all;
3 use IEEE.numeric_std.all;
3 use IEEE.numeric_std.all;
4 library grlib, techmap;
4 library grlib, techmap;
5 use grlib.amba.all;
5 use grlib.amba.all;
6 use grlib.amba.all;
6 use grlib.amba.all;
7 use grlib.stdlib.all;
7 use grlib.stdlib.all;
8 use techmap.gencomp.all;
8 use techmap.gencomp.all;
9 use techmap.allclkgen.all;
9 use techmap.allclkgen.all;
10 library gaisler;
10 library gaisler;
11 use gaisler.memctrl.all;
11 use gaisler.memctrl.all;
12 use gaisler.leon3.all;
12 use gaisler.leon3.all;
13 use gaisler.uart.all;
13 use gaisler.uart.all;
14 use gaisler.misc.all;
14 use gaisler.misc.all;
15 library esa;
15 library esa;
16 use esa.memoryctrl.all;
16 use esa.memoryctrl.all;
17 --use gaisler.sim.all;
17 --use gaisler.sim.all;
18 library lpp;
18 library lpp;
19 use lpp.lpp_ad_conv.all;
19 use lpp.lpp_ad_conv.all;
20 use lpp.lpp_amba.all;
20 use lpp.lpp_amba.all;
21 use lpp.apb_devices_list.all;
21 use lpp.apb_devices_list.all;
22 use lpp.general_purpose.all;
22 use lpp.general_purpose.all;
23 use lpp.lpp_cna.all;
23 use lpp.lpp_cna.all;
24 use lpp.lpp_memory.all;
24 use lpp.lpp_memory.all;
25
25
26 Library UNISIM;
26 Library UNISIM;
27 use UNISIM.vcomponents.all;
27 use UNISIM.vcomponents.all;
28
28
29 use work.config.all;
29 use work.config.all;
30
30
31 entity beagleSigGen is
31 entity beagleSigGen is
32 generic (
32 generic (
33 memtech : integer := CFG_MEMTECH;
33 memtech : integer := CFG_MEMTECH;
34 padtech : integer := CFG_PADTECH;
34 padtech : integer := CFG_PADTECH;
35 clktech : integer := CFG_CLKTECH
35 clktech : integer := CFG_CLKTECH
36 );
36 );
37 Port (
37 Port (
38 clk : in STD_LOGIC;
38 clk : in STD_LOGIC;
39 rstn : in STD_LOGIC;
39 rstn : in STD_LOGIC;
40 CAL_IN_SCK : out std_ulogic;
40 CAL_IN_SCK : out std_ulogic;
41 DAC_nCS : out std_ulogic;
41 DAC_nCS : out std_ulogic;
42 DAC_SDI : out std_logic_vector(7 downto 0);
42 DAC_SDI : out std_logic_vector(7 downto 0);
43 address : in std_logic_vector(2 downto 0);
43 address : in std_logic_vector(18 downto 0);
44 DATA : in std_logic_vector(15 downto 0);
44 DATA : in std_logic_vector(15 downto 0);
45 REN_debug : out std_logic;
45 REN_debug : out std_logic;
46 WEN : in std_logic;
46 WEN : in std_logic;
47 FIFO_FULL : out std_logic_vector(7 downto 0);
47 FIFO_FULL : out std_logic_vector(7 downto 0);
48 FIFO_EMPTY : out std_logic_vector(7 downto 0)
48 FIFO_EMPTY : out std_logic_vector(7 downto 0)
49 );
49 );
50 end beagleSigGen;
50 end beagleSigGen;
51
51
52 architecture Behavioral of beagleSigGen is
52 architecture Behavioral of beagleSigGen is
53
53
54 subtype TAB16 is std_logic_vector(15 downto 0);
55 type FIFOout_t is array(7 downto 0) of TAB16;
54
56
55 signal FIFO_FULL_net : std_logic_vector(7 downto 0);
57 signal FIFO_FULL_net : std_logic_vector(7 downto 0);
56 signal FIFO_EMPTY_net : std_logic_vector(7 downto 0);
58 signal FIFO_EMPTY_net : std_logic_vector(7 downto 0);
57 signal FIFO_WEN : std_logic_vector(7 downto 0);
58 signal FIFO_REN : std_logic;
59
59
60
60 signal FIFO_WEN : std_logic_vector(7 downto 0);
61 subtype TAB16 is std_logic_vector(15 downto 0);
61 signal FIFO_REN : std_logic;
62 type FIFOout_t is array(7 downto 0) of TAB16;
63
62
64 signal FIFO_out : FIFOout_t;
63 signal FIFO_out : FIFOout_t;
64
65 signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0);
65 signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0);
66 signal smpclk : std_logic;
66 signal smpclk : std_logic;
67 signal smpclk_reg : std_logic;
67 signal smpclk_reg : std_logic;
68 signal DAC_SDO : std_logic;
68 signal DAC_SDO : std_logic;
69 signal DATA_reg : std_logic_vector(15 downto 0);
69 signal DATA_reg : std_logic_vector(15 downto 0);
70
70
71 Constant clk_TRIGER_MAX : integer := (150000000/(2*4096))+1;
72 signal clk_TRIGER : integer range 0 to clk_TRIGER_MAX := clk_TRIGER_MAX;
73 signal cpt1 : integer;
74 signal clk_TRIGER_load : std_logic;
75
71 begin
76 begin
72
77
73
78
74
79
75 FIFO_FULL <= FIFO_FULL_net;
80 FIFO_FULL <= FIFO_FULL_net;
76 FIFO_EMPTY <= FIFO_EMPTY_net;
81 FIFO_EMPTY <= FIFO_EMPTY_net;
77
82
78 fron_fifo1: lpp_fifo
83 FIFOlp : FOR I IN 0 to 7 GENERATE
79 generic map(
84 front_fifoN: lpp_fifo
80 tech => memtech,
81 Mem_use => 1, --use RAM not CELS
82 DataSz => 16,
83 AddrSz => 8
84 )
85 port map(
86 rstn => rstn,
87 ReUse => '0',
88 rclk => clk,
89 ren => FIFO_REN,
90 rdata => FIFO_out(0),
91 empty => FIFO_EMPTY_net(0),
92 raddr => open,
93 wclk => clk,
94 wen => FIFO_WEN(0),
95 wdata => DATA_reg,
96 full => FIFO_FULL_net(0),
97 waddr => open
98 );
99 fron_fifo2: lpp_fifo
100 generic map(
85 generic map(
101 tech => memtech,
86 tech => memtech,
102 Mem_use => 1, --use RAM not CELS
87 Mem_use => 1, --use RAM not CELS
103 DataSz => 16,
88 DataSz => 16,
104 AddrSz => 8
89 AddrSz => 12
105 )
106 port map(
107 rstn => rstn,
108 ReUse => '0',
109 rclk => clk,
110 ren => FIFO_REN,
111 rdata => FIFO_out(1),
112 empty => FIFO_EMPTY_net(1),
113 raddr => open,
114 wclk => clk,
115 wen => FIFO_WEN(1),
116 wdata => DATA_reg,
117 full => FIFO_FULL_net(1),
118 waddr => open
119 );
120 fron_fifo3: lpp_fifo
121 generic map(
122 tech => memtech,
123 Mem_use => 1, --use RAM not CELS
124 DataSz => 16,
125 AddrSz => 8
126 )
127 port map(
128 rstn => rstn,
129 ReUse => '0',
130 rclk => clk,
131 ren => FIFO_REN,
132 rdata => FIFO_out(2),
133 empty => FIFO_EMPTY_net(2),
134 raddr => open,
135 wclk => clk,
136 wen => FIFO_WEN(2),
137 wdata => DATA_reg,
138 full => FIFO_FULL_net(2),
139 waddr => open
140 );
141 fron_fifo4: lpp_fifo
142 generic map(
143 tech => memtech,
144 Mem_use => 1, --use RAM not CELS
145 DataSz => 16,
146 AddrSz => 8
147 )
90 )
148 port map(
91 port map(
149 rstn => rstn,
92 rstn => rstn,
150 ReUse => '0',
93 ReUse => '0',
151 rclk => clk,
94 rclk => clk,
152 ren => FIFO_REN,
95 ren => FIFO_REN,
153 rdata => FIFO_out(3),
96 rdata => FIFO_out(I),
154 empty => FIFO_EMPTY_net(3),
97 empty => FIFO_EMPTY_net(I),
155 raddr => open,
156 wclk => clk,
157 wen => FIFO_WEN(3),
158 wdata => DATA_reg,
159 full => FIFO_FULL_net(3),
160 waddr => open
161 );
162 fron_fifo5: lpp_fifo
163 generic map(
164 tech => memtech,
165 Mem_use => 1, --use RAM not CELS
166 DataSz => 16,
167 AddrSz => 8
168 )
169 port map(
170 rstn => rstn,
171 ReUse => '0',
172 rclk => clk,
173 ren => FIFO_REN,
174 rdata => FIFO_out(4),
175 empty => FIFO_EMPTY_net(4),
176 raddr => open,
177 wclk => clk,
178 wen => FIFO_WEN(4),
179 wdata => DATA_reg,
180 full => FIFO_FULL_net(4),
181 waddr => open
182 );
183 fron_fifo6: lpp_fifo
184 generic map(
185 tech => memtech,
186 Mem_use => 1, --use RAM not CELS
187 DataSz => 16,
188 AddrSz => 8
189 )
190 port map(
191 rstn => rstn,
192 ReUse => '0',
193 rclk => clk,
194 ren => FIFO_REN,
195 rdata => FIFO_out(5),
196 empty => FIFO_EMPTY_net(5),
197 raddr => open,
98 raddr => open,
198 wclk => clk,
99 wclk => clk,
199 wen => FIFO_WEN(5),
100 wen => FIFO_WEN(I),
200 wdata => DATA_reg,
101 wdata => DATA_reg,
201 full => FIFO_FULL_net(5),
102 full => FIFO_FULL_net(I),
202 waddr => open
103 waddr => open
203 );
104 );
204 fron_fifo7: lpp_fifo
105 END GENERATE;
205 generic map(
106
206 tech => memtech,
107 --FIFOlp : FOR I IN 0 to 7 GENERATE
207 Mem_use => 1, --use RAM not CELS
108 --front_fifoN: FIFO_pipeline
208 DataSz => 16,
109 --generic map(
209 AddrSz => 8
110 -- tech => memtech,
210 )
111 -- fifoCount => 8,
211 port map(
112 -- Mem_use => 1, --use RAM not CELS
212 rstn => rstn,
113 -- DataSz => 16,
213 ReUse => '0',
114 -- abits => 10
214 rclk => clk,
115 -- )
215 ren => FIFO_REN,
116 --port map(
216 rdata => FIFO_out(6),
117 -- rstn => rstn,
217 empty => FIFO_EMPTY_net(6),
118 -- ReUse => '0',
218 raddr => open,
119 -- rclk => clk,
219 wclk => clk,
120 -- ren => FIFO_REN,
220 wen => FIFO_WEN(6),
121 -- rdata => FIFO_out(I),
221 wdata => DATA_reg,
122 -- empty => FIFO_EMPTY_net(I),
222 full => FIFO_FULL_net(6),
123 -- raddr => open,
223 waddr => open
124 -- wclk => clk,
224 );
125 -- wen => FIFO_WEN(I),
225 fron_fifo8: lpp_fifo
126 -- wdata => DATA_reg,
226 generic map(
127 -- full => FIFO_FULL_net(I),
227 tech => memtech,
128 -- waddr => open
228 Mem_use => 1, --use RAM not CELS
129 --);
229 DataSz => 16,
130 --END GENERATE;
230 AddrSz => 8
131
231 )
232 port map(
233 rstn => rstn,
234 ReUse => '0',
235 rclk => clk,
236 ren => FIFO_REN,
237 rdata => FIFO_out(7),
238 empty => FIFO_EMPTY_net(7),
239 raddr => open,
240 wclk => clk,
241 wen => FIFO_WEN(7),
242 wdata => DATA_reg,
243 full => FIFO_FULL_net(7),
244 waddr => open
245 );
246
132
247 REN_debug <= FIFO_REN;
133 REN_debug <= FIFO_REN;
248
134
249 process(clk,rstn)
135 process(clk,rstn)
250 begin
136 begin
251 if rstn = '0' then
137 if rstn = '0' then
252 DATA_reg <= (others => '0');
138 DATA_reg <= (others => '0');
253 FIFO_WEN <= (others => '0');
139 FIFO_WEN <= (others => '1');
140 clk_TRIGER <= clk_TRIGER_MAX;
141 clk_TRIGER_load <= '0';
254 elsif clk'event and clk = '1' then
142 elsif clk'event and clk = '1' then
255 if WEN = '0' then
143 if WEN = '0' then
256 DATA_reg <= DATA;
144 DATA_reg <= DATA;
257 case address is
145 case address(3 downto 0) is
258 when "000"=>
146 when "0000"=>
259 FIFO_WEN <= "11111110";
147 FIFO_WEN <= "11111110";
260 when "001"=>
148 when "0001"=>
261 FIFO_WEN <= "11111101";
149 FIFO_WEN <= "11111101";
262 when "010"=>
150 when "0010"=>
263 FIFO_WEN <= "11111011";
151 FIFO_WEN <= "11111011";
264 when "011"=>
152 when "0011"=>
265 FIFO_WEN <= "11110111";
153 FIFO_WEN <= "11110111";
266 when "100"=>
154 when "0100"=>
267 FIFO_WEN <= "11101111";
155 FIFO_WEN <= "11101111";
268 when "101"=>
156 when "0101"=>
269 FIFO_WEN <= "11011111";
157 FIFO_WEN <= "11011111";
270 when "110"=>
158 when "0110"=>
271 FIFO_WEN <= "10111111";
159 FIFO_WEN <= "10111111";
272 when "111"=>
160 when "0111"=>
273 FIFO_WEN <= "01111111";
161 FIFO_WEN <= "01111111";
274 when others =>
162 when others =>
275 FIFO_WEN <= "11111111";
163 FIFO_WEN <= "11111111";
276 end case;
164 end case;
165 else
166 FIFO_WEN <= "11111111";
167 end if;
168 if WEN = '0' then
169 if address(3 downto 0) = "1000" then
170 clk_TRIGER <= to_integer(unsigned(DATA));
171 clk_TRIGER_load <= '1';
172 end if;
173 else
174 clk_TRIGER_load <= '0';
277 end if;
175 end if;
278 end if;
176 end if;
279 end process;
177 end process;
280
178
281 all_bits: FOR I in 15 downto 0 GENERATE
179 all_bits: FOR I in 15 downto 0 GENERATE
282 all_chans: FOR J in 7 downto 0 GENERATE
180 all_chans: FOR J in 7 downto 0 GENERATE
283 DAC_DATA(J,I) <= FIFO_out(J)(I);
181 DAC_DATA(J,I) <= FIFO_out(J)(I);
284 end GENERATE;
182 end GENERATE;
285 end GENERATE;
183 end GENERATE;
286
184
287
185
288
186
289 process(clk,rstn)
187 process(clk,rstn)
290 begin
188 begin
291 if rstn = '0' then
189 if rstn = '0' then
292 FIFO_REN <= '1';
190 FIFO_REN <= '1';
293 smpclk_reg <= '0';
191 smpclk_reg <= '0';
294 elsif clk'event and clk = '1' then
192 elsif clk'event and clk = '1' then
295 smpclk_reg <= smpclk;
193 smpclk_reg <= smpclk;
296 if smpclk = '1' and smpclk_reg = '0' then
194 if smpclk = '1' and smpclk_reg = '0' and FIFO_EMPTY_net = X"00" then
297 FIFO_REN <= '0';
195 FIFO_REN <= '0' ;
298 else
196 else
299 FIFO_REN <= '1';
197 FIFO_REN <= '1';
300 end if;
198 end if;
301 end if;
199 end if;
302 end process;
200 end process;
303
201
304
202
305 DAC0 : DAC8581
203 DAC0 : DAC8581
306 generic map(150,8)
204 generic map(150,8)
307 Port map(
205 Port map(
308 clk => clk,
206 clk => clk,
309 rstn => rstn,
207 rstn => rstn,
310 smpclk => smpclk,
208 smpclk => smpclk,
311 sclk => CAL_IN_SCK,
209 sclk => CAL_IN_SCK,
312 csn => DAC_nCS,
210 csn => DAC_nCS,
313 sdo => DAC_SDI,
211 sdo => DAC_SDI,
314 smp_in => DAC_DATA
212 smp_in => DAC_DATA
315 );
213 );
316
214
317
215
318
216
319 smpclk0: Clk_divider
217 --smpclk0: Clk_divider
320 GENERIC map(OSC_freqHz => 150000000,
218 -- GENERIC map(OSC_freqHz => 150000000,
321 TargetFreq_Hz => 256000)
219 -- TargetFreq_Hz => 256000)
322 PORT map(
220 -- PORT map(
323 clk => clk,
221 -- clk => clk,
324 reset => rstn,
222 -- reset => rstn,
325 clk_divided => smpclk
223 -- clk_divided => smpclk
326 );
224 -- );
225
226 process(rstn,clk)
227 begin
228 if rstn = '0' then
229 cpt1 <= 0;
230 smpclk <= '0';
231 elsif clk'event and clk = '1' then
232 if cpt1 = clk_TRIGER or clk_TRIGER_load = '1' then
233 smpclk <= not smpclk;
234 cpt1 <= 0;
235 else
236 cpt1 <= cpt1 + 1;
237 end if;
238 end if;
239 end process;
327
240
328
241
329 end Behavioral;
242 end Behavioral;
330
243
Show file before | Show file after | Hide comments
@@ -1,105 +1,105
1 -- FIFO_pipeline.vhd
1 -- FIFO_pipeline.vhd
2 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
5 --
5 --
6 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
9 -- (at your option) any later version.
10 --
10 --
11 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
15 --
15 --
16 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 ------------------------------------------------------------------------------
19 ------------------------------------------------------------------------------
20 -- Author : Alexis Jeandet
20 -- Author : Alexis Jeandet
21 -- Mail : alexis.jeandet@member.fsf.org
21 -- Mail : alexis.jeandet@member.fsf.org
22 ------------------------------------------------------------------------------
22 ------------------------------------------------------------------------------
23 library IEEE;
23 library IEEE;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 use IEEE.numeric_std.all;
25 use IEEE.numeric_std.all;
26 library lpp;
26 library lpp;
27 use lpp.lpp_memory.all;
27 use lpp.lpp_memory.all;
28 use lpp.iir_filter.all;
28 use lpp.iir_filter.all;
29 library techmap;
29 library techmap;
30 use techmap.gencomp.all;
30 use techmap.gencomp.all;
31
31
32 entity FIFO_pipeline is
32 entity FIFO_pipeline is
33 generic(
33 generic(
34 tech : integer := 0;
34 tech : integer := 0;
35 Mem_use : integer := use_RAM;
35 Mem_use : integer := use_RAM;
36 fifoCount : integer range 2 to 100 := 8;
36 fifoCount : integer range 2 to 100 := 8;
37 DataSz : integer range 1 to 32 := 8;
37 DataSz : integer range 1 to 32 := 8;
38 abits : integer range 2 to 12 := 8
38 abits : integer range 2 to 12 := 8
39 );
39 );
40 port(
40 port(
41 rstn : in std_logic;
41 rstn : in std_logic;
42 ReUse : in std_logic;
42 ReUse : in std_logic;
43 rclk : in std_logic;
43 rclk : in std_logic;
44 ren : in std_logic;
44 ren : in std_logic;
45 rdata : out std_logic_vector(DataSz-1 downto 0);
45 rdata : out std_logic_vector(DataSz-1 downto 0);
46 empty : out std_logic;
46 empty : out std_logic;
47 raddr : out std_logic_vector(abits-1 downto 0);
47 raddr : out std_logic_vector(abits-1 downto 0);
48 wclk : in std_logic;
48 wclk : in std_logic;
49 wen : in std_logic;
49 wen : in std_logic;
50 wdata : in std_logic_vector(DataSz-1 downto 0);
50 wdata : in std_logic_vector(DataSz-1 downto 0);
51 full : out std_logic;
51 full : out std_logic;
52 waddr : out std_logic_vector(abits-1 downto 0)
52 waddr : out std_logic_vector(abits-1 downto 0)
53 );
53 );
54 end entity;
54 end entity;
55
55
56 architecture Ar_FIFO_pipeline of FIFO_pipeline is
56 architecture Ar_FIFO_pipeline of FIFO_pipeline is
57
57
58 type FIFO_DATA_t is array(NATURAL RANGE <>) of std_logic_vector(DataSz-1 downto 0);
58 type FIFO_DATA_t is array(NATURAL RANGE <>) of std_logic_vector(DataSz-1 downto 0);
59
59
60
60
61 Signal DATAi : FIFO_DATA_t(fifoCount downto 0);
61 Signal DATAi : FIFO_DATA_t(fifoCount downto 0);
62 Signal FULL_RENi,WEN_EMPTYi : std_logic_vector(fifoCount downto 0);
62 Signal FULL_RENi,WEN_EMPTYi : std_logic_vector(fifoCount downto 0);
63
63
64 begin
64 begin
65
65
66
66
67 fifos : for i in 0 to fifoCount-1 generate
67 fifos : for i in 0 to fifoCount-1 generate
68 fifo0 : lpp_fifo
68 fifo0 : lpp_fifo
69 generic map(
69 generic map(
70 tech => tech,
70 tech => tech,
71 Mem_use => Mem_use,
71 Mem_use => Mem_use,
72 Enable_ReUse => '0',
72 Enable_ReUse => '0',
73 DataSz => DataSz,
73 DataSz => DataSz,
74 abits => abits
74 AddrSz => abits
75 )
75 )
76 port map(
76 port map(
77 rstn => rstn,
77 rstn => rstn,
78 ReUse => '0',
78 ReUse => '0',
79 rclk => rclk,
79 rclk => rclk,
80 ren => FULL_RENi(i+1),
80 ren => FULL_RENi(i+1),
81 rdata => DATAi(i+1),
81 rdata => DATAi(i+1),
82 empty => WEN_EMPTYi(i+1),
82 empty => WEN_EMPTYi(i+1),
83 raddr => open,
83 raddr => open,
84 wclk => wclk,
84 wclk => wclk,
85 wen => WEN_EMPTYi(i),
85 wen => WEN_EMPTYi(i),
86 wdata => DATAi(i),
86 wdata => DATAi(i),
87 full => FULL_RENi(i),
87 full => FULL_RENi(i),
88 waddr => open
88 waddr => open
89 );
89 );
90
90
91 end generate;
91 end generate;
92
92
93 WEN_EMPTYi(0) <= wen;
93 WEN_EMPTYi(0) <= wen;
94 DATAi(0) <= wdata;
94 DATAi(0) <= wdata;
95 full <= FULL_RENi(0);
95 full <= FULL_RENi(0);
96
96
97
97
98 empty <= WEN_EMPTYi(fifoCount);
98 empty <= WEN_EMPTYi(fifoCount);
99 rdata <= DATAi(fifoCount);
99 rdata <= DATAi(fifoCount);
100 FULL_RENi(fifoCount) <= ren;
100 FULL_RENi(fifoCount) <= ren;
101
101
102 end ar_FIFO_pipeline;
102 end ar_FIFO_pipeline;
103
103
104
104
105
105
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