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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library grlib, techmap;
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use grlib.amba.all;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use techmap.gencomp.all;
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use techmap.allclkgen.all;
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library gaisler;
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use gaisler.memctrl.all;
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use gaisler.leon3.all;
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use gaisler.uart.all;
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use gaisler.misc.all;
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library esa;
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use esa.memoryctrl.all;
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--use gaisler.sim.all;
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library lpp;
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use lpp.lpp_ad_conv.all;
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use lpp.lpp_amba.all;
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use lpp.apb_devices_list.all;
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use lpp.general_purpose.all;
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use lpp.lpp_cna.all;
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Library UNISIM;
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use UNISIM.vcomponents.all;
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use work.config.all;
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--==================================================================
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--
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--
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-- FPGA FREQ = 100MHz
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--
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--
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--==================================================================
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entity BeagleSynth is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH
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);
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port (
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reset : in std_ulogic;
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clk : in std_ulogic;
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DAC_nCLR : out std_ulogic;
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DAC_nCS : out std_ulogic;
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CAL_IN_SCK : out std_ulogic;
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DAC_SDI : out std_logic_vector(7 downto 0);
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TXD : out std_ulogic;
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RXD : in std_ulogic;
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urxd1 : in std_ulogic;
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utxd1 : out std_ulogic;
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LED : out std_ulogic_vector(2 downto 0);
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--------------------------------------------------------
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---- Beaglebone GPMC
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--------------------------------------------------------
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GPMC_AD : inout std_logic_vector(15 downto 0);
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GPMC_A : in std_logic_vector(19 downto 0);
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GPMC_CLK_MUX0 : in std_logic;
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GPMC_WEN : in std_logic;
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GPMC_OEN_REN : in std_logic;
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GPMC_ADVN_ALE : in std_logic;
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GPMC_CSN : in std_logic_vector(2 downto 0);
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GPMC_BE0N_CLE : in std_logic;
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GPMC_BE1N : in std_logic;
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GPMC_WAIT0 : out std_logic;
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GPMC_WPN : in std_logic;
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--------------------------------------------------------
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---- SDRAM
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---- For SDRAM config have a look on leon3-altera-ep1c20
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---- design from GRLIB, the IS42S32400E is similar to
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---- MT48LC4M32B2.
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--------------------------------------------------------
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sdcke : out std_logic; -- clk en
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sdcsn : out std_logic; -- chip sel
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sdwen : out std_logic; -- write en
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sdrasn : out std_logic; -- row addr stb
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sdcasn : out std_logic; -- col addr stb
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sddqm : out std_logic_vector (3 downto 0); -- data i/o mask
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sdclk : out std_logic; -- sdram clk output
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sdba : out std_logic_vector (1 downto 0); -- bank select address
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Address : out std_logic_vector(11 downto 0); -- sdram address
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Data : inout std_logic_vector(31 downto 0) -- optional sdram data
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);
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end;
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architecture rtl of BeagleSynth is
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constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
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CFG_GRETH+CFG_AHB_JTAG;
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constant maxahbm : integer := maxahbmsp;
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constant IOAEN : integer := CFG_CAN;
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constant boardfreq : integer := 100000;
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signal clk2x : std_ulogic;
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signal lclk : std_ulogic;
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signal clkm : std_ulogic;
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signal rstn : std_ulogic;
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signal rst : std_ulogic;
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signal rstraw : std_ulogic;
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signal pciclk : std_ulogic;
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signal sdclkl : std_ulogic;
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signal sdclkl_DDR2 : std_ulogic;
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signal cgi : clkgen_in_type;
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signal cgo : clkgen_out_type;
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signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0);
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signal smpclk : std_logic;
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signal smpclk_reg : std_logic;
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signal DAC_SDO : std_logic;
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signal GPMC_SLAVE_STATUS : std_logic_vector(15 downto 0);
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signal GPMC_SLAVE_DATA : std_logic_vector(15 downto 0);
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signal GPMC_SLAVE_ADDRESS : std_logic_vector(19 downto 0);
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signal GPMC_SLAVE_WEN : std_logic;
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signal gpmc_clk : std_logic;
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attribute keep : boolean;
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attribute syn_keep : boolean;
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attribute syn_preserve : boolean;
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attribute syn_keep of clkm : signal is true;
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attribute syn_preserve of clkm : signal is true;
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attribute keep of clkm : signal is true;
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begin
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DAC_nCLR <= '1';
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resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
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rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw);
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clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk);
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cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
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clkgen0 : clkgen -- clock generator
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generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq)
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port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open);
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DAC0 : entity work.beagleSigGen
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generic map(
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memtech,
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padtech,
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clktech
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)
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Port map(
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clk => clkm,
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rstn => rstn,
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CAL_IN_SCK => CAL_IN_SCK,
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DAC_nCS => DAC_nCS,
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DAC_SDI => DAC_SDI,
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address => GPMC_SLAVE_ADDRESS(19 downto 1),
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DATA => GPMC_SLAVE_DATA,
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WEN => GPMC_SLAVE_WEN,
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REN_debug => open,
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FIFO_FULL => GPMC_SLAVE_STATUS(7 downto 0),
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FIFO_EMPTY => GPMC_SLAVE_STATUS(15 downto 8)
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);
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LED(0) <= GPMC_SLAVE_STATUS(0);
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LED(1) <= GPMC_SLAVE_STATUS(8);
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LED(2) <= GPMC_SLAVE_WEN;
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gpmc_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (GPMC_CLK_MUX0, gpmc_clk);
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GPMCS0: entity work.GPMC_SLAVE
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generic map(memtech,padtech)
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Port map(
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clk => clkm,
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reset => rstn,
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STATUS => GPMC_SLAVE_STATUS,
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DATA => GPMC_SLAVE_DATA,
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ADDRESS => GPMC_SLAVE_ADDRESS,
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WEN => GPMC_SLAVE_WEN,
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SMP_CKL => open,
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SMP_WEN => open,
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GPMC_AD => GPMC_AD,
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GPMC_A => GPMC_A,
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GPMC_CLK => gpmc_clk,
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GPMC_WEN => GPMC_WEN,
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GPMC_OEN_REN => GPMC_OEN_REN,
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GPMC_ADVN_ALE => GPMC_ADVN_ALE,
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GPMC_CSN => GPMC_CSN,
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GPMC_BE0N_CLE => GPMC_BE0N_CLE,
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GPMC_BE1N => GPMC_BE1N,
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GPMC_WAIT0 => GPMC_WAIT0,
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GPMC_WPN => GPMC_WPN
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);
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end rtl;
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