##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » VHD_Lib
RSS

Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

ADD LPP_CNA (and CAL to LFR-em)
pellion -
r531:1e4a9714222a JC
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,7
1 lpp_cna.vhd
2 APB_LFR_CAL.vhd
3 RAM_READER.vhd
4 RAM_WRITER.vhd
5 SPI_DAC_DRIVER.vhd
6 dynamic_freq_div.vhd
7 lfr_cal_driver.vhd
Show file before | Show file after | Hide comments
@@ -1,18 +1,27
1 1 vendor VENDOR_LPP 19
2 2
3 3 device ROCKET_TM 1
4 4 device otherCore 2
5 5 device LPP_SIMPLE_DIODE 3
6 6 device LPP_MULTI_DIODE 4
7 7 device LPP_LCD_CTRLR 5
8 8 device LPP_UART 6
9 9 device LPP_CNA 7
10 10 device LPP_APB_ADC 8
11 11 device LPP_CHENILLARD 9
12 12 device LPP_IIR_CEL_FILTER 10
13 13 device LPP_FIFO_PID 11
14 14 device LPP_FFT 12
15 15 device LPP_MATRIX 13
16 16 device LPP_DELAY 14
17 17 device LPP_USB 15
18 18 device LPP_BALISE 16
19 device LPP_DMA_TYPE 17
20 device LPP_BOOTLOADER_TYPE 18
21 device LPP_LFR 19
22 device LPP_CLKSETTING 20
23 device LPP_LFR_HK_DEVICE 21
24 device LPP_LFR_MANAGEMENT 22
25 device LPP_DEBUG_DMA A0
26 device LPP_DEBUG_LFR A1
27 device LPP_DEBUG_LFR_ID A2
Show file before | Show file after | Hide comments
@@ -1,122 +1,122
1 1 set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout
2 2 set_io clk100MHz -pinname B3 -fixed yes -DIRECTION Inout
3 3 set_io reset -pinname N18 -fixed yes -DIRECTION Inout
4 4
5 5 set_io {address[0]} -pinname H16 -fixed yes -DIRECTION Inout
6 6 set_io {address[1]} -pinname J15 -fixed yes -DIRECTION Inout
7 7 set_io {address[2]} -pinname B18 -fixed yes -DIRECTION Inout
8 8 set_io {address[3]} -pinname C17 -fixed yes -DIRECTION Inout
9 9 set_io {address[4]} -pinname C18 -fixed yes -DIRECTION Inout
10 10 set_io {address[5]} -pinname U2 -fixed yes -DIRECTION Inout
11 11 set_io {address[6]} -pinname U3 -fixed yes -DIRECTION Inout
12 12 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
13 13 set_io {address[8]} -pinname N11 -fixed yes -DIRECTION Inout
14 14 set_io {address[9]} -pinname R13 -fixed yes -DIRECTION Inout
15 15 set_io {address[10]} -pinname V13 -fixed yes -DIRECTION Inout
16 16 set_io {address[11]} -pinname U13 -fixed yes -DIRECTION Inout
17 17 set_io {address[12]} -pinname V15 -fixed yes -DIRECTION Inout
18 18 set_io {address[13]} -pinname V16 -fixed yes -DIRECTION Inout
19 19 set_io {address[14]} -pinname V17 -fixed yes -DIRECTION Inout
20 20 set_io {address[15]} -pinname N1 -fixed yes -DIRECTION Inout
21 21 set_io {address[16]} -pinname R3 -fixed yes -DIRECTION Inout
22 22 set_io {address[17]} -pinname P4 -fixed yes -DIRECTION Inout
23 23 set_io {address[18]} -pinname N3 -fixed yes -DIRECTION Inout
24 24 set_io {address[19]} -pinname M7 -fixed yes -DIRECTION Inout
25 25
26 26 set_io {data[0]} -pinname P17 -fixed yes -DIRECTION Inout
27 27 set_io {data[1]} -pinname R18 -fixed yes -DIRECTION Inout
28 28 set_io {data[2]} -pinname T18 -fixed yes -DIRECTION Inout
29 29 set_io {data[3]} -pinname J13 -fixed yes -DIRECTION Inout
30 30 set_io {data[4]} -pinname T13 -fixed yes -DIRECTION Inout
31 31 set_io {data[5]} -pinname T12 -fixed yes -DIRECTION Inout
32 32 set_io {data[6]} -pinname R12 -fixed yes -DIRECTION Inout
33 33 set_io {data[7]} -pinname T11 -fixed yes -DIRECTION Inout
34 34 set_io {data[8]} -pinname N2 -fixed yes -DIRECTION Inout
35 35 set_io {data[9]} -pinname P1 -fixed yes -DIRECTION Inout
36 36 set_io {data[10]} -pinname R1 -fixed yes -DIRECTION Inout
37 37 set_io {data[11]} -pinname T1 -fixed yes -DIRECTION Inout
38 38 set_io {data[12]} -pinname M4 -fixed yes -DIRECTION Inout
39 39 set_io {data[13]} -pinname K1 -fixed yes -DIRECTION Inout
40 40 set_io {data[14]} -pinname J1 -fixed yes -DIRECTION Inout
41 41 set_io {data[15]} -pinname H1 -fixed yes -DIRECTION Inout
42 42 set_io {data[16]} -pinname H15 -fixed yes -DIRECTION Inout
43 43 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
44 44 set_io {data[18]} -pinname H13 -fixed yes -DIRECTION Inout
45 45 set_io {data[19]} -pinname G12 -fixed yes -DIRECTION Inout
46 46 set_io {data[20]} -pinname V14 -fixed yes -DIRECTION Inout
47 47 set_io {data[21]} -pinname N9 -fixed yes -DIRECTION Inout
48 48 set_io {data[22]} -pinname M13 -fixed yes -DIRECTION Inout
49 49 set_io {data[23]} -pinname M15 -fixed yes -DIRECTION Inout
50 50 set_io {data[24]} -pinname J17 -fixed yes -DIRECTION Inout
51 51 set_io {data[25]} -pinname K15 -fixed yes -DIRECTION Inout
52 52 set_io {data[26]} -pinname J14 -fixed yes -DIRECTION Inout
53 53 set_io {data[27]} -pinname U18 -fixed yes -DIRECTION Inout
54 54 set_io {data[28]} -pinname H18 -fixed yes -DIRECTION Inout
55 55 set_io {data[29]} -pinname J18 -fixed yes -DIRECTION Inout
56 56 set_io {data[30]} -pinname G17 -fixed yes -DIRECTION Inout
57 57 set_io {data[31]} -pinname F18 -fixed yes -DIRECTION Inout
58 58
59 59 set_io nSRAM_BE0 -pinname U12 -fixed yes -DIRECTION Inout
60 60 set_io nSRAM_BE1 -pinname K18 -fixed yes -DIRECTION Inout
61 61 set_io nSRAM_BE2 -pinname K12 -fixed yes -DIRECTION Inout
62 62 set_io nSRAM_BE3 -pinname F17 -fixed yes -DIRECTION Inout
63 63 set_io nSRAM_WE -pinname D18 -fixed yes -DIRECTION Inout
64 64 set_io nSRAM_CE -pinname M6 -fixed yes -DIRECTION Inout
65 65 set_io nSRAM_OE -pinname N12 -fixed yes -DIRECTION Inout
66 66
67 67 set_io spw1_din -pinname D6 -fixed yes -DIRECTION Inout
68 68 set_io spw1_sin -pinname C6 -fixed yes -DIRECTION Inout
69 69 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
70 70 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
71 71
72 72 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
73 73 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
74 74 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
75 75 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
76 76
77 77 set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout
78 78 set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout
79 79 set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout
80 80
81 81 set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout
82 82 set_io TAG2 -pinname K13 -fixed yes -DIRECTION Inout
83 83 set_io TAG3 -pinname L16 -fixed yes -DIRECTION Inout
84 84 set_io TAG4 -pinname L15 -fixed yes -DIRECTION Inout
85 85 #set_io TAG5 -pinname M16 -fixed yes -DIRECTION Inout
86 86 #set_io TAG6 -pinname L13 -fixed yes -DIRECTION Inout
87 #set_io TAG7 -pinname P6 -fixed yes -DIRECTION Inout
87 #set_io TAG7 -pinname P6 -fixed yes -DIRECTION Inout
88 88 set_io TAG8 -pinname R6 -fixed yes -DIRECTION Inout
89 89 #set_io TAG9 -pinname T4 -fixed yes -DIRECTION Inout
90 90
91 91 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
92 92
93 93 set_io {ADC_OEB_bar_CH[0]} -pinname A13 -fixed yes -DIRECTION Inout
94 94 set_io {ADC_OEB_bar_CH[1]} -pinname A14 -fixed yes -DIRECTION Inout
95 95 set_io {ADC_OEB_bar_CH[2]} -pinname A10 -fixed yes -DIRECTION Inout
96 96 set_io {ADC_OEB_bar_CH[3]} -pinname B10 -fixed yes -DIRECTION Inout
97 97 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
98 98 set_io {ADC_OEB_bar_CH[5]} -pinname D13 -fixed yes -DIRECTION Inout
99 99 set_io {ADC_OEB_bar_CH[6]} -pinname A11 -fixed yes -DIRECTION Inout
100 100 set_io {ADC_OEB_bar_CH[7]} -pinname B12 -fixed yes -DIRECTION Inout
101 101
102 102 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
103 103
104 104 set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout
105 105 set_io ADC_OEB_bar_HK -pinname D14 -fixed yes -DIRECTION Inout
106 106 set_io {HK_SEL[0]} -pinname A2 -fixed yes -DIRECTION Inout
107 107 set_io {HK_SEL[1]} -pinname C3 -fixed yes -DIRECTION Inout
108 108
109 109 set_io {ADC_data[0]} -pinname A16 -fixed yes -DIRECTION Inout
110 110 set_io {ADC_data[1]} -pinname B16 -fixed yes -DIRECTION Inout
111 111 set_io {ADC_data[2]} -pinname A17 -fixed yes -DIRECTION Inout
112 112 set_io {ADC_data[3]} -pinname C12 -fixed yes -DIRECTION Inout
113 113 set_io {ADC_data[4]} -pinname B17 -fixed yes -DIRECTION Inout
114 114 set_io {ADC_data[5]} -pinname C13 -fixed yes -DIRECTION Inout
115 115 set_io {ADC_data[6]} -pinname D15 -fixed yes -DIRECTION Inout
116 116 set_io {ADC_data[7]} -pinname E15 -fixed yes -DIRECTION Inout
117 117 set_io {ADC_data[8]} -pinname D16 -fixed yes -DIRECTION Inout
118 118 set_io {ADC_data[9]} -pinname F16 -fixed yes -DIRECTION Inout
119 119 set_io {ADC_data[10]} -pinname F15 -fixed yes -DIRECTION Inout
120 120 set_io {ADC_data[11]} -pinname G16 -fixed yes -DIRECTION Inout
121 121 set_io {ADC_data[12]} -pinname F13 -fixed yes -DIRECTION Inout
122 122 set_io {ADC_data[13]} -pinname G13 -fixed yes -DIRECTION Inout
Show file before | Show file after | Hide comments
@@ -1,444 +1,455
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY LFR_em IS
49 49
50 50 PORT (
51 51 clk100MHz : IN STD_ULOGIC;
52 52 clk49_152MHz : IN STD_ULOGIC;
53 53 reset : IN STD_ULOGIC;
54 54
55 55 -- TAG --------------------------------------------------------------------
56 56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 58 -- UART APB ---------------------------------------------------------------
59 59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 61 -- RAM --------------------------------------------------------------------
62 62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 64 nSRAM_BE0 : OUT STD_LOGIC;
65 65 nSRAM_BE1 : OUT STD_LOGIC;
66 66 nSRAM_BE2 : OUT STD_LOGIC;
67 67 nSRAM_BE3 : OUT STD_LOGIC;
68 68 nSRAM_WE : OUT STD_LOGIC;
69 69 nSRAM_CE : OUT STD_LOGIC;
70 70 nSRAM_OE : OUT STD_LOGIC;
71 71 -- SPW --------------------------------------------------------------------
72 72 spw1_din : IN STD_LOGIC;
73 73 spw1_sin : IN STD_LOGIC;
74 74 spw1_dout : OUT STD_LOGIC;
75 75 spw1_sout : OUT STD_LOGIC;
76 76 spw2_din : IN STD_LOGIC;
77 77 spw2_sin : IN STD_LOGIC;
78 78 spw2_dout : OUT STD_LOGIC;
79 79 spw2_sout : OUT STD_LOGIC;
80 80 -- ADC --------------------------------------------------------------------
81 81 bias_fail_sw : OUT STD_LOGIC;
82 82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 83 ADC_smpclk : OUT STD_LOGIC;
84 84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 -- DAC --------------------------------------------------------------------
86 DAC_SDO : OUT STD_LOGIC;
87 DAC_SCK : OUT STD_LOGIC;
88 DAC_SYNC : OUT STD_LOGIC;
89 DAC_CAL_EN : OUT STD_LOGIC;
85 90 -- HK ---------------------------------------------------------------------
86 91 HK_smpclk : OUT STD_LOGIC;
87 92 ADC_OEB_bar_HK : OUT STD_LOGIC;
88 93 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
89 94 ---------------------------------------------------------------------------
90 95 TAG8 : OUT STD_LOGIC;
91 96 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
92 97 );
93 98
94 99 END LFR_em;
95 100
96 101
97 102 ARCHITECTURE beh OF LFR_em IS
98 103 SIGNAL clk_50_s : STD_LOGIC := '0';
99 104 SIGNAL clk_25 : STD_LOGIC := '0';
100 105 SIGNAL clk_24 : STD_LOGIC := '0';
101 106 -----------------------------------------------------------------------------
102 107 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
103 108 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
104 109
105 110 -- CONSTANTS
106 111 CONSTANT CFG_PADTECH : INTEGER := inferred;
107 112 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
108 113 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
109 114 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
110 115
111 116 SIGNAL apbi_ext : apb_slv_in_type;
112 117 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
113 118 SIGNAL ahbi_s_ext : ahb_slv_in_type;
114 119 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
115 120 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
116 121 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
117 122
118 123 -- Spacewire signals
119 124 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
120 125 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
121 126 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
122 127 SIGNAL spw_rxtxclk : STD_ULOGIC;
123 128 SIGNAL spw_rxclkn : STD_ULOGIC;
124 129 SIGNAL spw_clk : STD_LOGIC;
125 130 SIGNAL swni : grspw_in_type;
126 131 SIGNAL swno : grspw_out_type;
127 132
128 133 --GPIO
129 134 SIGNAL gpioi : gpio_in_type;
130 135 SIGNAL gpioo : gpio_out_type;
131 136
132 137 -- AD Converter ADS7886
133 138 SIGNAL sample : Samples14v(8 DOWNTO 0);
134 139 SIGNAL sample_s : Samples(8 DOWNTO 0);
135 140 SIGNAL sample_val : STD_LOGIC;
136 141 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
137 142
138 143 -----------------------------------------------------------------------------
139 144 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
140 145
141 146 -----------------------------------------------------------------------------
142 147 SIGNAL rstn : STD_LOGIC;
143 148
144 149 SIGNAL LFR_soft_rstn : STD_LOGIC;
145 150 SIGNAL LFR_rstn : STD_LOGIC;
146 151
147 152 SIGNAL ADC_smpclk_s : STD_LOGIC;
148 153 -----------------------------------------------------------------------------
149 154 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 155
151 156 BEGIN -- beh
152 157
153 158 -----------------------------------------------------------------------------
154 159 -- CLK
155 160 -----------------------------------------------------------------------------
156 161 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
157 162
158 163 PROCESS(clk100MHz)
159 164 BEGIN
160 165 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
161 166 clk_50_s <= NOT clk_50_s;
162 167 END IF;
163 168 END PROCESS;
164 169
165 170 PROCESS(clk_50_s)
166 171 BEGIN
167 172 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
168 173 clk_25 <= NOT clk_25;
169 174 END IF;
170 175 END PROCESS;
171 176
172 177 PROCESS(clk49_152MHz)
173 178 BEGIN
174 179 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
175 180 clk_24 <= NOT clk_24;
176 181 END IF;
177 182 END PROCESS;
178 183
179 184 -----------------------------------------------------------------------------
180 185
181 186 PROCESS (clk_25, rstn)
182 187 BEGIN -- PROCESS
183 188 IF rstn = '0' THEN -- asynchronous reset (active low)
184 189 led(0) <= '0';
185 190 led(1) <= '0';
186 191 led(2) <= '0';
187 192 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
188 193 led(0) <= '0';
189 194 led(1) <= '1';
190 195 led(2) <= '1';
191 196 END IF;
192 197 END PROCESS;
193 198
194 199 --
195 200 leon3_soc_1 : leon3_soc
196 201 GENERIC MAP (
197 202 fabtech => apa3e,
198 203 memtech => apa3e,
199 204 padtech => inferred,
200 205 clktech => inferred,
201 206 disas => 0,
202 207 dbguart => 0,
203 208 pclow => 2,
204 209 clk_freq => 25000,
205 210 IS_RADHARD => 0,
206 211 NB_CPU => 1,
207 212 ENABLE_FPU => 1,
208 213 FPU_NETLIST => 0,
209 214 ENABLE_DSU => 1,
210 215 ENABLE_AHB_UART => 1,
211 216 ENABLE_APB_UART => 1,
212 217 ENABLE_IRQMP => 1,
213 218 ENABLE_GPT => 1,
214 219 NB_AHB_MASTER => NB_AHB_MASTER,
215 220 NB_AHB_SLAVE => NB_AHB_SLAVE,
216 221 NB_APB_SLAVE => NB_APB_SLAVE,
217 222 ADDRESS_SIZE => 20,
218 223 USES_IAP_MEMCTRLR => 0)
219 224 PORT MAP (
220 225 clk => clk_25,
221 226 reset => rstn,
222 227 errorn => OPEN,
223 228
224 229 ahbrxd => TAG1,
225 230 ahbtxd => TAG3,
226 231 urxd1 => TAG2,
227 232 utxd1 => TAG4,
228 233
229 234 address => address,
230 235 data => data,
231 236 nSRAM_BE0 => nSRAM_BE0,
232 237 nSRAM_BE1 => nSRAM_BE1,
233 238 nSRAM_BE2 => nSRAM_BE2,
234 239 nSRAM_BE3 => nSRAM_BE3,
235 240 nSRAM_WE => nSRAM_WE,
236 241 nSRAM_CE => nSRAM_CE_s,
237 242 nSRAM_OE => nSRAM_OE,
238 243 nSRAM_READY => '0',
239 244 SRAM_MBE => OPEN,
240 245
241 246 apbi_ext => apbi_ext,
242 247 apbo_ext => apbo_ext,
243 248 ahbi_s_ext => ahbi_s_ext,
244 249 ahbo_s_ext => ahbo_s_ext,
245 250 ahbi_m_ext => ahbi_m_ext,
246 251 ahbo_m_ext => ahbo_m_ext);
247 252
248 253
249 254 nSRAM_CE <= nSRAM_CE_s(0);
250 255
251 256 -------------------------------------------------------------------------------
252 257 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
253 258 -------------------------------------------------------------------------------
254 259 apb_lfr_management_1 : apb_lfr_management
255 260 GENERIC MAP (
261 tech => apa3e,
256 262 pindex => 6,
257 263 paddr => 6,
258 264 pmask => 16#fff#,
259 265 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
260 266 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
261 267 PORT MAP (
262 268 clk25MHz => clk_25,
263 269 clk24_576MHz => clk_24, -- 49.152MHz/2
264 270 resetn => rstn,
265 271 grspw_tick => swno.tickout,
266 272 apbi => apbi_ext,
267 273 apbo => apbo_ext(6),
268 274
269 275 HK_sample => sample_s(8),
270 276 HK_val => sample_val,
271 277 HK_sel => HK_SEL,
272 278
279 DAC_SDO => DAC_SDO,
280 DAC_SCK => DAC_SCK,
281 DAC_SYNC => DAC_SYNC,
282 DAC_CAL_EN => DAC_CAL_EN,
283
273 284 coarse_time => coarse_time,
274 285 fine_time => fine_time,
275 286 LFR_soft_rstn => LFR_soft_rstn
276 287 );
277 288
278 289 -----------------------------------------------------------------------
279 290 --- SpaceWire --------------------------------------------------------
280 291 -----------------------------------------------------------------------
281 292
282 293 -- SPW_EN <= '1';
283 294
284 295 spw_clk <= clk_50_s;
285 296 spw_rxtxclk <= spw_clk;
286 297 spw_rxclkn <= NOT spw_rxtxclk;
287 298
288 299 -- PADS for SPW1
289 300 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
290 301 PORT MAP (spw1_din, dtmp(0));
291 302 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
292 303 PORT MAP (spw1_sin, stmp(0));
293 304 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
294 305 PORT MAP (spw1_dout, swno.d(0));
295 306 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
296 307 PORT MAP (spw1_sout, swno.s(0));
297 308 -- PADS FOR SPW2
298 309 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
299 310 PORT MAP (spw2_din, dtmp(1));
300 311 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
301 312 PORT MAP (spw2_sin, stmp(1));
302 313 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
303 314 PORT MAP (spw2_dout, swno.d(1));
304 315 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
305 316 PORT MAP (spw2_sout, swno.s(1));
306 317
307 318 -- GRSPW PHY
308 319 --spw1_input: if CFG_SPW_GRSPW = 1 generate
309 320 spw_inputloop : FOR j IN 0 TO 1 GENERATE
310 321 spw_phy0 : grspw_phy
311 322 GENERIC MAP(
312 323 tech => apa3e,
313 324 rxclkbuftype => 1,
314 325 scantest => 0)
315 326 PORT MAP(
316 327 rxrst => swno.rxrst,
317 328 di => dtmp(j),
318 329 si => stmp(j),
319 330 rxclko => spw_rxclk(j),
320 331 do => swni.d(j),
321 332 ndo => swni.nd(j*5+4 DOWNTO j*5),
322 333 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
323 334 END GENERATE spw_inputloop;
324 335
325 336 -- SPW core
326 337 sw0 : grspwm GENERIC MAP(
327 338 tech => apa3e,
328 339 hindex => 1,
329 340 pindex => 5,
330 341 paddr => 5,
331 342 pirq => 11,
332 343 sysfreq => 25000, -- CPU_FREQ
333 344 rmap => 1,
334 345 rmapcrc => 1,
335 346 fifosize1 => 16,
336 347 fifosize2 => 16,
337 348 rxclkbuftype => 1,
338 349 rxunaligned => 0,
339 350 rmapbufs => 4,
340 351 ft => 0,
341 352 netlist => 0,
342 353 ports => 2,
343 354 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
344 355 memtech => apa3e,
345 356 destkey => 2,
346 357 spwcore => 1
347 358 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
348 359 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
349 360 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
350 361 )
351 362 PORT MAP(rstn, clk_25, spw_rxclk(0),
352 363 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
353 364 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
354 365 swni, swno);
355 366
356 367 swni.tickin <= '0';
357 368 swni.rmapen <= '1';
358 369 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
359 370 swni.tickinraw <= '0';
360 371 swni.timein <= (OTHERS => '0');
361 372 swni.dcrstval <= (OTHERS => '0');
362 373 swni.timerrstval <= (OTHERS => '0');
363 374
364 375 -------------------------------------------------------------------------------
365 376 -- LFR ------------------------------------------------------------------------
366 377 -------------------------------------------------------------------------------
367 378 LFR_rstn <= LFR_soft_rstn AND rstn;
368 379
369 380 lpp_lfr_1 : lpp_lfr
370 381 GENERIC MAP (
371 382 Mem_use => use_RAM,
372 383 nb_data_by_buffer_size => 32,
373 384 --nb_word_by_buffer_size => 30,
374 385 nb_snapshot_param_size => 32,
375 386 delta_vector_size => 32,
376 387 delta_vector_size_f0_2 => 7, -- log2(96)
377 388 pindex => 15,
378 389 paddr => 15,
379 390 pmask => 16#fff#,
380 391 pirq_ms => 6,
381 392 pirq_wfp => 14,
382 393 hindex => 2,
383 top_lfr_version => X"01013A") -- aa.bb.cc version
394 top_lfr_version => X"01013B") -- aa.bb.cc version
384 395 -- AA : BOARD NUMBER
385 396 -- 0 => MINI_LFR
386 397 -- 1 => EM
387 398 PORT MAP (
388 399 clk => clk_25,
389 400 rstn => LFR_rstn,
390 401 sample_B => sample_s(2 DOWNTO 0),
391 402 sample_E => sample_s(7 DOWNTO 3),
392 403 sample_val => sample_val,
393 404 apbi => apbi_ext,
394 405 apbo => apbo_ext(15),
395 406 ahbi => ahbi_m_ext,
396 407 ahbo => ahbo_m_ext(2),
397 408 coarse_time => coarse_time,
398 409 fine_time => fine_time,
399 410 data_shaping_BW => bias_fail_sw,
400 411 debug_vector => OPEN,
401 412 debug_vector_ms => OPEN); --,
402 413 --observation_vector_0 => OPEN,
403 414 --observation_vector_1 => OPEN,
404 415 --observation_reg => observation_reg);
405 416
406 417
407 418 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
408 419 sample_s(I) <= sample(I) & '0' & '0';
409 420 END GENERATE all_sample;
410 421 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
411 422
412 423 -----------------------------------------------------------------------------
413 424 --
414 425 -----------------------------------------------------------------------------
415 426 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
416 427 GENERIC MAP (
417 428 ChanelCount => 9,
418 429 ncycle_cnv_high => 13,
419 430 ncycle_cnv => 25,
420 431 FILTER_ENABLED => 16#FF#)
421 432 PORT MAP (
422 433 cnv_clk => clk_24,
423 434 cnv_rstn => rstn,
424 435 cnv => ADC_smpclk_s,
425 436 clk => clk_25,
426 437 rstn => rstn,
427 438 ADC_data => ADC_data,
428 439 ADC_nOE => ADC_OEB_bar_CH_s,
429 440 sample => sample,
430 441 sample_val => sample_val);
431 442
432 443 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
433 444
434 445 ADC_smpclk <= ADC_smpclk_s;
435 446 HK_smpclk <= ADC_smpclk_s;
436 447
437 448 TAG8 <= ADC_smpclk_s;
438 449
439 450 -----------------------------------------------------------------------------
440 451 -- HK
441 452 -----------------------------------------------------------------------------
442 453 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
443 454
444 455 END beh;
Show file before | Show file after | Hide comments
@@ -1,59 +1,58
1 1 #GRLIB=../..
2 2 VHDLIB=../..
3 3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 5 TOP=LFR_em
6 6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
8 8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 11 EFFORT=high
12 12 XSTOPT=
13 13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 15 #VHDLSYNFILES=config.vhd leon3mp.vhd
16 16 VHDLSYNFILES=LFR-em.vhd
17 17 VHDLSIMFILES=testbench.vhd
18 18 #SIMTOP=testbench
19 19 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
20 20 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
21 PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL_withHK.pdc
21 PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL_withHK-DAC.pdc
22 22
23 23 #SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
24 24 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc
25 25
26 26 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
27 27 CLEAN=soft-clean
28 28
29 29 TECHLIBS = proasic3e
30 30
31 31 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
32 32 tmtc openchip hynix ihp gleichmann micron usbhc
33 33
34 34 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
35 35 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
36 36 ./amba_lcd_16x2_ctrlr \
37 37 ./general_purpose/lpp_AMR \
38 38 ./general_purpose/lpp_balise \
39 39 ./general_purpose/lpp_delay \
40 40 ./lpp_bootloader \
41 ./lpp_cna \
42 41 ./dsp/lpp_fft_rtax \
43 42 ./lpp_uart \
44 43 ./lpp_usb \
45 44 ./lpp_sim/CY7C1061DV33 \
46 45
47 46 FILESKIP = i2cmst.vhd \
48 47 APB_MULTI_DIODE.vhd \
49 48 APB_MULTI_DIODE.vhd \
50 49 Top_MatrixSpec.vhd \
51 50 APB_FFT.vhd\
52 51 CoreFFT_simu.vhd \
53 52 lpp_lfr_apbreg_simu.vhd
54 53
55 54 include $(GRLIB)/bin/Makefile
56 55 include $(GRLIB)/software/leon3/Makefile
57 56
58 57 ################## project specific targets ##########################
59 58
Show file before | Show file after | Hide comments
@@ -1,31 +1,31
1 1 ./amba_lcd_16x2_ctrlr
2 2 ./general_purpose
3 3 ./general_purpose/lpp_AMR
4 4 ./general_purpose/lpp_balise
5 5 ./general_purpose/lpp_delay
6 6 ./lpp_amba
7 7 ./dsp/chirp
8 8 ./dsp/iir_filter
9 9 ./dsp/cic
10 10 ./dsp/lpp_downsampling
11 11 ./dsp/lpp_fft_rtax
12 12 ./lpp_memory
13 13 ./dsp/lpp_fft
14 ./lpp_cna
14 15 ./lfr_management
15 16 ./lpp_ad_Conv
16 17 ./lpp_bootloader
17 ./lpp_cna
18 18 ./lpp_spectral_matrix
19 19 ./lpp_demux
20 20 ./lpp_Header
21 21 ./lpp_matrix
22 22 ./lpp_uart
23 23 ./lpp_usb
24 24 ./lpp_dma
25 25 ./lpp_waveform
26 26 ./lpp_top_lfr
27 27 ./lpp_Header
28 28 ./lpp_leon3_soc
29 29 ./lpp_debug_lfr
30 30 ./lpp_sim/CY7C1061DV33
31 31 ./lpp_sim
Show file before | Show file after | Hide comments
@@ -1,397 +1,507
1 1 ----------------------------------------------------------------------------------
2 2 -- Company:
3 3 -- Engineer:
4 4 --
5 5 -- Create Date: 11:17:05 07/02/2012
6 6 -- Design Name:
7 7 -- Module Name: apb_lfr_time_management - Behavioral
8 8 -- Project Name:
9 9 -- Target Devices:
10 10 -- Tool versions:
11 11 -- Description:
12 12 --
13 13 -- Dependencies:
14 14 --
15 15 -- Revision:
16 16 -- Revision 0.01 - File Created
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 20 LIBRARY IEEE;
21 21 USE IEEE.STD_LOGIC_1164.ALL;
22 22 USE IEEE.NUMERIC_STD.ALL;
23 23 LIBRARY grlib;
24 24 USE grlib.amba.ALL;
25 25 USE grlib.stdlib.ALL;
26 26 USE grlib.devices.ALL;
27 27 LIBRARY lpp;
28 28 USE lpp.apb_devices_list.ALL;
29 29 USE lpp.general_purpose.ALL;
30 30 USE lpp.lpp_lfr_management.ALL;
31 31 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
32 USE lpp.lpp_cna.ALL;
33 LIBRARY techmap;
34 USE techmap.gencomp.ALL;
32 35
33 36
34 37 ENTITY apb_lfr_management IS
35 38
36 39 GENERIC(
40 tech : INTEGER := 0;
37 41 pindex : INTEGER := 0; --! APB slave index
38 42 paddr : INTEGER := 0; --! ADDR field of the APB BAR
39 43 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
40 44 FIRST_DIVISION : INTEGER := 374;
41 45 NB_SECOND_DESYNC : INTEGER := 60
42 46 );
43 47
44 48 PORT (
45 49 clk25MHz : IN STD_LOGIC; --! Clock
46 50 clk24_576MHz : IN STD_LOGIC; --! secondary clock
47 51 resetn : IN STD_LOGIC; --! Reset
48 52
49 53 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
50 54
51 55 apbi : IN apb_slv_in_type; --! APB slave input signals
52 56 apbo : OUT apb_slv_out_type; --! APB slave output signals
53 57 ---------------------------------------------------------------------------
54 58 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
55 59 HK_val : IN STD_LOGIC;
56 60 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
57 61 ---------------------------------------------------------------------------
62 DAC_SDO : OUT STD_LOGIC;
63 DAC_SCK : OUT STD_LOGIC;
64 DAC_SYNC : OUT STD_LOGIC;
65 DAC_CAL_EN : OUT STD_LOGIC;
66 ---------------------------------------------------------------------------
58 67 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
59 68 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
60 69 ---------------------------------------------------------------------------
61 70 LFR_soft_rstn : OUT STD_LOGIC
62 71 );
63 72
64 73 END apb_lfr_management;
65 74
66 75 ARCHITECTURE Behavioral OF apb_lfr_management IS
67 76
68 77 CONSTANT REVISION : INTEGER := 1;
69 78 CONSTANT pconfig : apb_config_type := (
70 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, 0),
79 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR_MANAGEMENT, 0, REVISION, 0),
71 80 1 => apb_iobar(paddr, pmask)
72 81 );
73 82
74 83 TYPE apb_lfr_time_management_Reg IS RECORD
75 84 ctrl : STD_LOGIC;
76 85 soft_reset : STD_LOGIC;
77 86 coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
78 87 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
79 88 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
80 89 LFR_soft_reset : STD_LOGIC;
81 90 HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
82 91 HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
83 92 HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
84 93 END RECORD;
85 94 SIGNAL r : apb_lfr_time_management_Reg;
86 95
87 96 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
88 97 SIGNAL force_tick : STD_LOGIC;
89 98 SIGNAL previous_force_tick : STD_LOGIC;
90 99 SIGNAL soft_tick : STD_LOGIC;
91 100
92 101 SIGNAL coarsetime_reg_updated : STD_LOGIC;
93 102 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0);
94 103
95 104 --SIGNAL coarse_time_new : STD_LOGIC;
96 105 SIGNAL coarse_time_new_49 : STD_LOGIC;
97 106 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 107 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 108
100 109 --SIGNAL fine_time_new : STD_LOGIC;
101 110 --SIGNAL fine_time_new_temp : STD_LOGIC;
102 111 SIGNAL fine_time_new_49 : STD_LOGIC;
103 112 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
104 113 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
105 114 SIGNAL tick : STD_LOGIC;
106 115 SIGNAL new_timecode : STD_LOGIC;
107 116 SIGNAL new_coarsetime : STD_LOGIC;
108 117
109 118 SIGNAL time_new_49 : STD_LOGIC;
110 119 SIGNAL time_new : STD_LOGIC;
111 120
112 121 -----------------------------------------------------------------------------
113 122 SIGNAL force_reset : STD_LOGIC;
114 123 SIGNAL previous_force_reset : STD_LOGIC;
115 124 SIGNAL soft_reset : STD_LOGIC;
116 125 SIGNAL soft_reset_sync : STD_LOGIC;
117 126 -----------------------------------------------------------------------------
118 127 SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
119 128
120 129 SIGNAL previous_fine_time_bit : STD_LOGIC;
121 130
122 131 SIGNAL rstn_LFR_TM : STD_LOGIC;
132
133 -----------------------------------------------------------------------------
134 -- DAC
135 -----------------------------------------------------------------------------
136 CONSTANT PRESZ : INTEGER := 8;
137 CONSTANT CPTSZ : INTEGER := 16;
138 CONSTANT datawidth : INTEGER := 18;
139 CONSTANT dacresolution : INTEGER := 12;
140 CONSTANT abits : INTEGER := 8;
141
142 SIGNAL pre : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
143 SIGNAL N : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
144 SIGNAL Reload : STD_LOGIC;
145 SIGNAL DATA_IN : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
146 SIGNAL WEN : STD_LOGIC;
147 SIGNAL LOAD_ADDRESSN : STD_LOGIC;
148 SIGNAL ADDRESS_IN : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
149 SIGNAL ADDRESS_OUT : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
150 SIGNAL INTERLEAVED : STD_LOGIC;
151 SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 SIGNAL DAC_CAL_EN_s : STD_LOGIC;
123 153
124 154 BEGIN
125 155
126 156 LFR_soft_rstn <= NOT r.LFR_soft_reset;
127 157
128 158 PROCESS(resetn, clk25MHz)
129 159 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
130 160 BEGIN
131 161
132 162 IF resetn = '0' THEN
133 163 Rdata <= (OTHERS => '0');
134 164 r.coarse_time_load <= (OTHERS => '0');
135 165 r.soft_reset <= '0';
136 166 r.ctrl <= '0';
137 167 r.LFR_soft_reset <= '1';
138 168
139 169 force_tick <= '0';
140 170 previous_force_tick <= '0';
141 171 soft_tick <= '0';
142 172
143 173 coarsetime_reg_updated <= '0';
144
174 --DAC
175 pre <= (OTHERS => '1');
176 N <= (OTHERS => '1');
177 Reload <= '1';
178 DATA_IN <= (OTHERS => '0');
179 WEN <= '1';
180 LOAD_ADDRESSN <= '1';
181 ADDRESS_IN <= (OTHERS => '1');
182 INTERLEAVED <= '0';
183 DAC_CFG <= (OTHERS => '0');
184 --
185 DAC_CAL_EN_s <= '0';
145 186 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
146 187 coarsetime_reg_updated <= '0';
147 188
148 189 force_tick <= r.ctrl;
149 190 previous_force_tick <= force_tick;
150 191 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
151 192 soft_tick <= '1';
152 193 ELSE
153 194 soft_tick <= '0';
154 195 END IF;
155 196
156 197 force_reset <= r.soft_reset;
157 198 previous_force_reset <= force_reset;
158 199 IF (previous_force_reset = '0') AND (force_reset = '1') THEN
159 200 soft_reset <= '1';
160 201 ELSE
161 202 soft_reset <= '0';
162 203 END IF;
163 204
164 205 paddr := "000000";
165 206 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
166 207 Rdata <= (OTHERS => '0');
167 208
168 209
169 210 IF apbi.psel(pindex) = '1' THEN
170 211 --APB READ OP
171 212 CASE paddr(7 DOWNTO 2) IS
172 213 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
173 214 Rdata(0) <= r.ctrl;
174 215 Rdata(1) <= r.soft_reset;
175 216 Rdata(2) <= r.LFR_soft_reset;
176 217 Rdata(31 DOWNTO 3) <= (OTHERS => '0');
177 218 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
178 219 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
179 220 WHEN ADDR_LFR_MANAGMENT_TIME_COARSE =>
180 221 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
181 222 WHEN ADDR_LFR_MANAGMENT_TIME_FINE =>
182 223 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
183 224 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
184 225 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 =>
185 226 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
186 227 Rdata(15 DOWNTO 0) <= r.HK_temp_0;
187 228 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 =>
188 229 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
189 230 Rdata(15 DOWNTO 0) <= r.HK_temp_1;
190 231 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
191 232 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
192 233 Rdata(15 DOWNTO 0) <= r.HK_temp_2;
234 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
235 Rdata(3 DOWNTO 0) <= DAC_CFG;
236 Rdata(4) <= Reload;
237 Rdata(5) <= INTERLEAVED;
238 Rdata(6) <= DAC_CAL_EN_s;
239 Rdata(31 DOWNTO 7) <= (OTHERS => '0');
240 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
241 Rdata(PRESZ-1 DOWNTO 0) <= pre;
242 Rdata(31 DOWNTO PRESZ) <= (OTHERS => '0');
243 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
244 Rdata(CPTSZ-1 DOWNTO 0) <= N;
245 Rdata(31 DOWNTO CPTSZ) <= (OTHERS => '0');
246 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
247 Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
248 Rdata(31 DOWNTO abits) <= (OTHERS => '0');
249 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
250 Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
251 Rdata(31 DOWNTO datawidth) <= (OTHERS => '0');
193 252 WHEN OTHERS =>
194 253 Rdata(31 DOWNTO 0) <= (OTHERS => '0');
195 254 END CASE;
196 255
197 256 --APB Write OP
198 257 IF (apbi.pwrite AND apbi.penable) = '1' THEN
199 258 CASE paddr(7 DOWNTO 2) IS
200 259 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
201 260 r.ctrl <= apbi.pwdata(0);
202 261 r.soft_reset <= apbi.pwdata(1);
203 262 r.LFR_soft_reset <= apbi.pwdata(2);
204 263 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
205 264 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
206 265 coarsetime_reg_updated <= '1';
266 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
267 DAC_CFG <= apbi.pwdata(3 DOWNTO 0);
268 Reload <= apbi.pwdata(4);
269 INTERLEAVED <= apbi.pwdata(5);
270 DAC_CAL_EN_s <= apbi.pwdata(6);
271 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
272 pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
273 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
274 N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
275 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
276 ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0);
277 LOAD_ADDRESSN <= '0';
278 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
279 DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
280 WEN <= '0';
281
207 282 WHEN OTHERS =>
208 283 NULL;
209 284 END CASE;
210 285 ELSE
286 LOAD_ADDRESSN <= '1';
287 WEN <= '1';
211 288 IF r.ctrl = '1' THEN
212 289 r.ctrl <= '0';
213 290 END IF;
214 291 IF r.soft_reset = '1' THEN
215 292 r.soft_reset <= '0';
216 293 END IF;
217 294 END IF;
218 295
219 296 END IF;
220 297
221 298 END IF;
222 299 END PROCESS;
223 300
224 301 apbo.pirq <= (OTHERS => '0');
225 302 apbo.prdata <= Rdata;
226 303 apbo.pconfig <= pconfig;
227 304 apbo.pindex <= pindex;
228 305
229 306 -----------------------------------------------------------------------------
230 307 -- IN
231 308 coarse_time <= r.coarse_time;
232 309 fine_time <= r.fine_time;
233 310 coarsetime_reg <= r.coarse_time_load;
234 311 -----------------------------------------------------------------------------
235 312
236 313 -----------------------------------------------------------------------------
237 314 -- OUT
238 315 r.coarse_time <= coarse_time_s;
239 316 r.fine_time <= fine_time_s;
240 317 -----------------------------------------------------------------------------
241 318
242 319 -----------------------------------------------------------------------------
243 320 tick <= grspw_tick OR soft_tick;
244 321
245 322 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
246 323 GENERIC MAP (
247 324 NB_FF_OF_SYNC => 2)
248 325 PORT MAP (
249 326 clk_in => clk25MHz,
250 327 clk_out => clk24_576MHz,
251 328 rstn => resetn,
252 329 sin => tick,
253 330 sout => new_timecode);
254 331
255 332 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
256 333 GENERIC MAP (
257 334 NB_FF_OF_SYNC => 2)
258 335 PORT MAP (
259 336 clk_in => clk25MHz,
260 337 clk_out => clk24_576MHz,
261 338 rstn => resetn,
262 339 sin => coarsetime_reg_updated,
263 340 sout => new_coarsetime);
264 341
265 342 SYNC_VALID_BIT_3 : SYNC_VALID_BIT
266 343 GENERIC MAP (
267 344 NB_FF_OF_SYNC => 2)
268 345 PORT MAP (
269 346 clk_in => clk25MHz,
270 347 clk_out => clk24_576MHz,
271 348 rstn => resetn,
272 349 sin => soft_reset,
273 350 sout => soft_reset_sync);
274 351
275 352 -----------------------------------------------------------------------------
276 353 --SYNC_FF_1 : SYNC_FF
277 354 -- GENERIC MAP (
278 355 -- NB_FF_OF_SYNC => 2)
279 356 -- PORT MAP (
280 357 -- clk => clk25MHz,
281 358 -- rstn => resetn,
282 359 -- A => fine_time_new_49,
283 360 -- A_sync => fine_time_new_temp);
284 361
285 362 --lpp_front_detection_1 : lpp_front_detection
286 363 -- PORT MAP (
287 364 -- clk => clk25MHz,
288 365 -- rstn => resetn,
289 366 -- sin => fine_time_new_temp,
290 367 -- sout => fine_time_new);
291 368
292 369 --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
293 370 -- GENERIC MAP (
294 371 -- NB_FF_OF_SYNC => 2)
295 372 -- PORT MAP (
296 373 -- clk_in => clk24_576MHz,
297 374 -- clk_out => clk25MHz,
298 375 -- rstn => resetn,
299 376 -- sin => coarse_time_new_49,
300 377 -- sout => coarse_time_new);
301 378
302 379 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
303 380
304 381 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
305 382 GENERIC MAP (
306 383 NB_FF_OF_SYNC => 2)
307 384 PORT MAP (
308 385 clk_in => clk24_576MHz,
309 386 clk_out => clk25MHz,
310 387 rstn => resetn,
311 388 sin => time_new_49,
312 389 sout => time_new);
313 390
314 391
315 392
316 393 PROCESS (clk25MHz, resetn)
317 394 BEGIN -- PROCESS
318 395 IF resetn = '0' THEN -- asynchronous reset (active low)
319 396 fine_time_s <= (OTHERS => '0');
320 397 coarse_time_s <= (OTHERS => '0');
321 398 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
322 399 IF time_new = '1' THEN
323 400 fine_time_s <= fine_time_49;
324 401 coarse_time_s <= coarse_time_49;
325 402 END IF;
326 403 END IF;
327 404 END PROCESS;
328 405
329 406
330 407 rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE
331 408 '0' WHEN soft_reset_sync = '1' ELSE
332 409 '1';
333 410
334 411
335 412 -----------------------------------------------------------------------------
336 413 -- LFR_TIME_MANAGMENT
337 414 -----------------------------------------------------------------------------
338 415 lfr_time_management_1 : lfr_time_management
339 416 GENERIC MAP (
340 417 FIRST_DIVISION => FIRST_DIVISION,
341 418 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
342 419 PORT MAP (
343 420 clk => clk24_576MHz,
344 421 rstn => rstn_LFR_TM,
345 422
346 423 tick => new_timecode,
347 424 new_coarsetime => new_coarsetime,
348 425 coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
349 426
350 427 fine_time => fine_time_49,
351 428 fine_time_new => fine_time_new_49,
352 429 coarse_time => coarse_time_49,
353 430 coarse_time_new => coarse_time_new_49);
354 431
355 432 -----------------------------------------------------------------------------
356 433 -- HK
357 434 -----------------------------------------------------------------------------
358 435
359 436 PROCESS (clk25MHz, resetn)
360 437 CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14; -- freq = 2^(16-BIT)
361 438 -- for each HK, the update frequency is freq/3
362 439 --
363 440 -- for 14, the update frequency is
364 441 -- 4Hz and update for each
365 442 -- HK is 1.33Hz
366 443
367 444 BEGIN -- PROCESS
368 445 IF resetn = '0' THEN -- asynchronous reset (active low)
369 446
370 447 r.HK_temp_0 <= (OTHERS => '0');
371 448 r.HK_temp_1 <= (OTHERS => '0');
372 449 r.HK_temp_2 <= (OTHERS => '0');
373 450
374 451 HK_sel_s <= "00";
375 452
376 453 previous_fine_time_bit <= '0';
377 454
378 455 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
379 456
380 457 IF HK_val = '1' THEN
381 458 IF previous_fine_time_bit = NOT(fine_time_s(BIT_FREQUENCY_UPDATE)) THEN
382 459 previous_fine_time_bit <= fine_time_s(BIT_FREQUENCY_UPDATE);
383 460 CASE HK_sel_s IS
384 461 WHEN "00" => r.HK_temp_0 <= HK_sample; HK_sel_s <= "01";
385 462 WHEN "01" => r.HK_temp_1 <= HK_sample; HK_sel_s <= "10";
386 463 WHEN "10" => r.HK_temp_2 <= HK_sample; HK_sel_s <= "00";
387 464 WHEN OTHERS => NULL;
388 465 END CASE;
389 466 END IF;
390 467 END IF;
391 468
392 469 END IF;
393 470 END PROCESS;
394 471
395 472 HK_sel <= HK_sel_s;
396
473
474 -----------------------------------------------------------------------------
475 -- DAC
476 -----------------------------------------------------------------------------
477 cal : lfr_cal_driver
478 GENERIC MAP(
479 tech => tech,
480 PRESZ => PRESZ,
481 CPTSZ => CPTSZ,
482 datawidth => datawidth,
483 abits => abits
484 )
485 PORT MAP(
486 clk => clk25MHz,
487 rstn => resetn,
488
489 pre => pre,
490 N => N,
491 Reload => Reload,
492 DATA_IN => DATA_IN,
493 WEN => WEN,
494 LOAD_ADDRESSN => LOAD_ADDRESSN,
495 ADDRESS_IN => ADDRESS_IN,
496 ADDRESS_OUT => ADDRESS_OUT,
497 INTERLEAVED => INTERLEAVED,
498 DAC_CFG => DAC_CFG,
499
500 SYNC => DAC_SYNC,
501 DOUT => DAC_SDO,
502 SCLK => DAC_SCK,
503 SMPCLK => OPEN --DAC_SMPCLK
504 );
505
506 DAC_CAL_EN <= DAC_CAL_EN_s;
397 507 END Behavioral; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,105 +1,110
1 1 ----------------------------------------------------------------------------------
2 2 -- Company:
3 3 -- Engineer:
4 4 --
5 5 -- Create Date: 13:04:01 07/02/2012
6 6 -- Design Name:
7 7 -- Module Name: lpp_lfr_time_management - Behavioral
8 8 -- Project Name:
9 9 -- Target Devices:
10 10 -- Tool versions:
11 11 -- Description:
12 12 --
13 13 -- Dependencies:
14 14 --
15 15 -- Revision:
16 16 -- Revision 0.01 - File Created
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 20 LIBRARY IEEE;
21 21 USE IEEE.STD_LOGIC_1164.ALL;
22 22 LIBRARY grlib;
23 23 USE grlib.amba.ALL;
24 24 USE grlib.stdlib.ALL;
25 25 USE grlib.devices.ALL;
26 26
27 27 PACKAGE lpp_lfr_management IS
28 28
29 29 --***************************
30 30 -- APB_LFR_MANAGEMENT
31 31
32 32 COMPONENT apb_lfr_management
33 33 GENERIC (
34 tech : INTEGER;
34 35 pindex : INTEGER;
35 36 paddr : INTEGER;
36 37 pmask : INTEGER;
37 38 FIRST_DIVISION : INTEGER;
38 39 NB_SECOND_DESYNC : INTEGER);
39 40 PORT (
40 41 clk25MHz : IN STD_LOGIC;
41 42 clk24_576MHz : IN STD_LOGIC;
42 43 resetn : IN STD_LOGIC;
43 44 grspw_tick : IN STD_LOGIC;
44 45 apbi : IN apb_slv_in_type;
45 46 apbo : OUT apb_slv_out_type;
46 47 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
47 48 HK_val : IN STD_LOGIC;
48 49 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
50 DAC_SDO : OUT STD_LOGIC;
51 DAC_SCK : OUT STD_LOGIC;
52 DAC_SYNC : OUT STD_LOGIC;
53 DAC_CAL_EN : OUT STD_LOGIC;
49 54 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
50 55 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
51 56 LFR_soft_rstn : OUT STD_LOGIC);
52 57 END COMPONENT;
53 58
54 59 COMPONENT lfr_time_management
55 60 GENERIC (
56 61 FIRST_DIVISION : INTEGER;
57 62 NB_SECOND_DESYNC : INTEGER);
58 63 PORT (
59 64 clk : IN STD_LOGIC;
60 65 rstn : IN STD_LOGIC;
61 66 tick : IN STD_LOGIC;
62 67 new_coarsetime : IN STD_LOGIC;
63 68 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
64 69 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
65 70 fine_time_new : OUT STD_LOGIC;
66 71 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
67 72 coarse_time_new : OUT STD_LOGIC);
68 73 END COMPONENT;
69 74
70 75 COMPONENT coarse_time_counter
71 76 GENERIC (
72 77 NB_SECOND_DESYNC : INTEGER );
73 78 PORT (
74 79 clk : IN STD_LOGIC;
75 80 rstn : IN STD_LOGIC;
76 81 tick : IN STD_LOGIC;
77 82 set_TCU : IN STD_LOGIC;
78 83 new_TCU : IN STD_LOGIC;
79 84 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
80 85 CT_add1 : IN STD_LOGIC;
81 86 fsm_desync : IN STD_LOGIC;
82 87 FT_max : IN STD_LOGIC;
83 88 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 89 coarse_time_new : OUT STD_LOGIC);
85 90 END COMPONENT;
86 91
87 92 COMPONENT fine_time_counter
88 93 GENERIC (
89 94 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0);
90 95 FIRST_DIVISION : INTEGER );
91 96 PORT (
92 97 clk : IN STD_LOGIC;
93 98 rstn : IN STD_LOGIC;
94 99 tick : IN STD_LOGIC;
95 100 fsm_transition : IN STD_LOGIC;
96 101 FT_max : OUT STD_LOGIC;
97 102 FT_half : OUT STD_LOGIC;
98 103 FT_wait : OUT STD_LOGIC;
99 104 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
100 105 fine_time_new : OUT STD_LOGIC);
101 106 END COMPONENT;
102 107
103 108
104 109 END lpp_lfr_management;
105 110
Show file before | Show file after | Hide comments
@@ -1,15 +1,20
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 PACKAGE lpp_lfr_management_apbreg_pkg IS
6 6
7 7 CONSTANT ADDR_LFR_MANAGMENT_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000000";
8 8 CONSTANT ADDR_LFR_MANAGMENT_TIME_LOAD : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000001";
9 9 CONSTANT ADDR_LFR_MANAGMENT_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000010";
10 10 CONSTANT ADDR_LFR_MANAGMENT_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000011";
11 11 CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_0 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000100";
12 12 CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_1 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000101";
13 13 CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_2 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000110";
14 CONSTANT ADDR_LFR_MANAGMENT_DAC_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000111";
15 CONSTANT ADDR_LFR_MANAGMENT_DAC_PRE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001000";
16 CONSTANT ADDR_LFR_MANAGMENT_DAC_N : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001001";
17 CONSTANT ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001010";
18 CONSTANT ADDR_LFR_MANAGMENT_DAC_DATA_IN : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001011";
14 19
15 20 END lpp_lfr_management_apbreg_pkg;
Show file before | Show file after | Hide comments
@@ -1,48 +1,48
1 1
2 2 --=================================================================================
3 3 --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT
4 4 --
5 5 --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID
6 6 --=================================================================================
7 7
8 8
9 9 LIBRARY ieee;
10 10 USE ieee.std_logic_1164.ALL;
11 11 LIBRARY grlib;
12 12 USE grlib.amba.ALL;
13 13 USE std.textio.ALL;
14 14
15 15
16 16 PACKAGE apb_devices_list IS
17 17
18 18
19 19 CONSTANT VENDOR_LPP : amba_vendor_type := 16#19#;
20 20
21 21 CONSTANT ROCKET_TM : amba_device_type := 16#1#;
22 22 CONSTANT otherCore : amba_device_type := 16#2#;
23 23 CONSTANT LPP_SIMPLE_DIODE : amba_device_type := 16#3#;
24 24 CONSTANT LPP_MULTI_DIODE : amba_device_type := 16#4#;
25 25 CONSTANT LPP_LCD_CTRLR : amba_device_type := 16#5#;
26 26 CONSTANT LPP_UART : amba_device_type := 16#6#;
27 27 CONSTANT LPP_CNA : amba_device_type := 16#7#;
28 28 CONSTANT LPP_APB_ADC : amba_device_type := 16#8#;
29 29 CONSTANT LPP_CHENILLARD : amba_device_type := 16#9#;
30 30 CONSTANT LPP_IIR_CEL_FILTER : amba_device_type := 16#10#;
31 31 CONSTANT LPP_FIFO_PID : amba_device_type := 16#11#;
32 32 CONSTANT LPP_FFT : amba_device_type := 16#12#;
33 33 CONSTANT LPP_MATRIX : amba_device_type := 16#13#;
34 34 CONSTANT LPP_DELAY : amba_device_type := 16#14#;
35 35 CONSTANT LPP_USB : amba_device_type := 16#15#;
36 36 CONSTANT LPP_BALISE : amba_device_type := 16#16#;
37 37 CONSTANT LPP_DMA_TYPE : amba_device_type := 16#17#;
38 38 CONSTANT LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#;
39 39 CONSTANT LPP_LFR : amba_device_type := 16#19#;
40 40 CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#;
41 41 CONSTANT LPP_LFR_HK_DEVICE : amba_device_type := 16#21#;
42
42 CONSTANT LPP_LFR_MANAGEMENT : amba_device_type := 16#22#;
43 43 CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#;
44 44 CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#;
45 45
46 46 CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A2#;
47 47
48 48 END;
Show file before | Show file after | Hide comments
@@ -1,181 +1,183
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@member.fsf.org
21 21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library grlib;
26 use grlib.amba.all;
27 use grlib.stdlib.all;
28 use grlib.devices.all;
29 library lpp;
30 use lpp.lpp_amba.all;
31 use lpp.lpp_cna.all;
32 use lpp.apb_devices_list.all;
22 LIBRARY ieee;
23 USE ieee.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 USE grlib.devices.ALL;
29 LIBRARY lpp;
30 USE lpp.lpp_amba.ALL;
31 USE lpp.lpp_cna.ALL;
32 USE lpp.apb_devices_list.ALL;
33 33
34 entity apb_lfr_cal is
35 generic (
36 pindex : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
39 tech : integer := 0;
40 PRESZ : integer := 8;
41 CPTSZ : integer := 16;
42 datawidth : integer := 18;
43 dacresolution : integer := 12;
44 abits : integer := 8
34 ENTITY apb_lfr_cal IS
35 GENERIC (
36 pindex : INTEGER := 0;
37 paddr : INTEGER := 0;
38 pmask : INTEGER := 16#fff#;
39 tech : INTEGER := 0;
40 PRESZ : INTEGER := 8;
41 CPTSZ : INTEGER := 16;
42 datawidth : INTEGER := 18;
43 dacresolution : INTEGER := 12;
44 abits : INTEGER := 8
45 45 );
46 port (
47 rstn : in std_logic;
48 clk : in std_logic;
49 apbi : in apb_slv_in_type;
50 apbo : out apb_slv_out_type;
51 SDO : out std_logic;
52 SCK : out std_logic;
53 SYNC : out std_logic;
54 SMPCLK : out std_logic
46 PORT (
47 rstn : IN STD_LOGIC;
48 clk : IN STD_LOGIC;
49 apbi : IN apb_slv_in_type;
50 apbo : OUT apb_slv_out_type;
51 SDO : OUT STD_LOGIC;
52 SCK : OUT STD_LOGIC;
53 SYNC : OUT STD_LOGIC;
54 SMPCLK : OUT STD_LOGIC
55 55 );
56 end entity;
56 END ENTITY;
57 57
58 58 --! @details Les deux registres (apbi,apbo) permettent de g�rer la communication sur le bus
59 59 --! et les sorties seront cabl�es vers le convertisseur.
60 60
61 architecture ar_apb_lfr_cal of apb_lfr_cal is
61 ARCHITECTURE ar_apb_lfr_cal OF apb_lfr_cal IS
62 62
63 constant REVISION : integer := 1;
63 CONSTANT REVISION : INTEGER := 1;
64 64
65 constant pconfig : apb_config_type := (
66 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
67 1 => apb_iobar(paddr, pmask));
65 CONSTANT pconfig : apb_config_type := (
66 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
67 1 => apb_iobar(paddr, pmask));
68 68
69 signal pre : STD_LOGIC_VECTOR(PRESZ-1 downto 0);
70 signal N : STD_LOGIC_VECTOR(CPTSZ-1 downto 0);
71 signal Reload : std_logic;
72 signal DATA_IN : STD_LOGIC_VECTOR(datawidth-1 downto 0);
73 signal WEN : STD_LOGIC;
74 signal LOAD_ADDRESSN : STD_LOGIC;
75 signal ADDRESS_IN : STD_LOGIC_VECTOR(abits-1 downto 0);
76 signal ADDRESS_OUT : STD_LOGIC_VECTOR(abits-1 downto 0);
77 signal INTERLEAVED : STD_LOGIC;
78 signal DAC_CFG : STD_LOGIC_VECTOR(3 downto 0);
79 signal Rdata : std_logic_vector(31 downto 0);
69 SIGNAL pre : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
70 SIGNAL N : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
71 SIGNAL Reload : STD_LOGIC;
72 SIGNAL DATA_IN : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
73 SIGNAL WEN : STD_LOGIC;
74 SIGNAL LOAD_ADDRESSN : STD_LOGIC;
75 SIGNAL ADDRESS_IN : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
76 SIGNAL ADDRESS_OUT : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
77 SIGNAL INTERLEAVED : STD_LOGIC;
78 SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0);
79 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
80 80
81 begin
81 BEGIN
82 82
83 cal: lfr_cal_driver
84 generic map(
85 tech => tech,
86 PRESZ => PRESZ,
87 CPTSZ => CPTSZ,
88 datawidth => datawidth,
89 abits => abits
90 )
91 Port map(
92 clk => clk,
93 rstn => rstn,
94 pre => pre,
95 N => N,
96 Reload => Reload,
97 DATA_IN => DATA_IN,
98 WEN => WEN,
99 LOAD_ADDRESSN => LOAD_ADDRESSN,
100 ADDRESS_IN => ADDRESS_IN,
101 ADDRESS_OUT => ADDRESS_OUT,
102 INTERLEAVED => INTERLEAVED,
103 DAC_CFG => DAC_CFG,
104 SYNC => SYNC,
105 DOUT => SDO,
106 SCLK => SCK,
107 SMPCLK => SMPCLK
108 );
83 cal : lfr_cal_driver
84 GENERIC MAP(
85 tech => tech,
86 PRESZ => PRESZ,
87 CPTSZ => CPTSZ,
88 datawidth => datawidth,
89 abits => abits
90 )
91 PORT MAP(
92 clk => clk,
93 rstn => rstn,
94
95 pre => pre,
96 N => N,
97 Reload => Reload,
98 DATA_IN => DATA_IN,
99 WEN => WEN,
100 LOAD_ADDRESSN => LOAD_ADDRESSN,
101 ADDRESS_IN => ADDRESS_IN,
102 ADDRESS_OUT => ADDRESS_OUT,
103 INTERLEAVED => INTERLEAVED,
104 DAC_CFG => DAC_CFG,
105
106 SYNC => SYNC,
107 DOUT => SDO,
108 SCLK => SCK,
109 SMPCLK => SMPCLK -- OPEN
110 );
109 111
110 process(rstn,clk)
111 begin
112 if(rstn='0')then
113 pre <= (others=>'1');
114 N <= (others=>'1');
115 Reload <= '1';
116 DATA_IN <= (others=>'0');
117 WEN <= '1';
118 LOAD_ADDRESSN <= '1';
119 ADDRESS_IN <= (others=>'1');
120 INTERLEAVED <= '0';
121 DAC_CFG <= (others=>'0');
122 Rdata <= (others=>'0');
123 elsif(clk'event and clk='1')then
124
112 PROCESS(rstn, clk)
113 BEGIN
114 IF(rstn = '0')then
115 pre <= (OTHERS => '1');
116 N <= (OTHERS => '1');
117 Reload <= '1';
118 DATA_IN <= (OTHERS => '0');
119 WEN <= '1';
120 LOAD_ADDRESSN <= '1';
121 ADDRESS_IN <= (OTHERS => '1');
122 INTERLEAVED <= '0';
123 DAC_CFG <= (OTHERS => '0');
124 Rdata <= (OTHERS => '0');
125 ELSIF(clk'EVENT AND clk = '1')then
126
125 127
126 --APB Write OP
127 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
128 case apbi.paddr(abits-1 downto 2) is
129 when "000000" =>
130 DAC_CFG <= apbi.pwdata(3 downto 0);
131 Reload <= apbi.pwdata(4);
132 INTERLEAVED <= apbi.pwdata(5);
133 when "000001" =>
134 pre <= apbi.pwdata(PRESZ-1 downto 0);
135 when "000010" =>
136 N <= apbi.pwdata(CPTSZ-1 downto 0);
137 when "000011" =>
138 ADDRESS_IN <= apbi.pwdata(abits-1 downto 0);
139 LOAD_ADDRESSN <= '0';
140 when "000100" =>
141 DATA_IN <= apbi.pwdata(datawidth-1 downto 0);
142 WEN <= '0';
143 when others =>
144 null;
145 end case;
146 else
147 LOAD_ADDRESSN <= '1';
148 WEN <= '1';
149 end if;
128 --APB Write OP
129 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
130 CASE apbi.paddr(abits-1 DOWNTO 2) IS
131 WHEN "000000" =>
132 DAC_CFG <= apbi.pwdata(3 DOWNTO 0);
133 Reload <= apbi.pwdata(4);
134 INTERLEAVED <= apbi.pwdata(5);
135 WHEN "000001" =>
136 pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
137 WHEN "000010" =>
138 N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
139 WHEN "000011" =>
140 ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0);
141 LOAD_ADDRESSN <= '0';
142 WHEN "000100" =>
143 DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
144 WEN <= '0';
145 WHEN OTHERS =>
146 NULL;
147 END CASE;
148 ELSE
149 LOAD_ADDRESSN <= '1';
150 WEN <= '1';
151 END IF;
150 152
151 --APB Read OP
152 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
153 case apbi.paddr(abits-1 downto 2) is
154 when "000000" =>
155 Rdata(3 downto 0) <= DAC_CFG;
156 Rdata(4) <= Reload;
157 Rdata(5) <= INTERLEAVED;
158 Rdata(31 downto 6) <= (others => '0');
159 when "000001" =>
160 Rdata(PRESZ-1 downto 0) <= pre;
161 Rdata(31 downto PRESZ) <= (others => '0');
162 when "000010" =>
163 Rdata(CPTSZ-1 downto 0) <= N;
164 Rdata(31 downto CPTSZ) <= (others => '0');
165 when "000011" =>
166 Rdata(abits-1 downto 0) <= ADDRESS_OUT;
167 Rdata(31 downto abits) <= (others => '0');
168 when "000100" =>
169 Rdata(datawidth-1 downto 0) <= DATA_IN;
170 Rdata(31 downto datawidth) <= (others => '0');
171 when others =>
172 Rdata <= (others => '0');
173 end case;
174 end if;
153 --APB Read OP
154 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
155 CASE apbi.paddr(abits-1 DOWNTO 2) IS
156 WHEN "000000" =>
157 Rdata(3 DOWNTO 0) <= DAC_CFG;
158 Rdata(4) <= Reload;
159 Rdata(5) <= INTERLEAVED;
160 Rdata(31 DOWNTO 6) <= (OTHERS => '0');
161 WHEN "000001" =>
162 Rdata(PRESZ-1 DOWNTO 0) <= pre;
163 Rdata(31 DOWNTO PRESZ) <= (OTHERS => '0');
164 WHEN "000010" =>
165 Rdata(CPTSZ-1 DOWNTO 0) <= N;
166 Rdata(31 DOWNTO CPTSZ) <= (OTHERS => '0');
167 WHEN "000011" =>
168 Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
169 Rdata(31 DOWNTO abits) <= (OTHERS => '0');
170 WHEN "000100" =>
171 Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
172 Rdata(31 DOWNTO datawidth) <= (OTHERS => '0');
173 WHEN OTHERS =>
174 Rdata <= (OTHERS => '0');
175 END CASE;
176 END IF;
175 177
176 end if;
177 apbo.pconfig <= pconfig;
178 end process;
178 END IF;
179 apbo.pconfig <= pconfig;
180 END PROCESS;
179 181
180 apbo.prdata <= Rdata when apbi.penable = '1';
181 end architecture ar_apb_lfr_cal; No newline at end of file
182 apbo.prdata <= Rdata WHEN apbi.penable = '1';
183 END ARCHITECTURE ar_apb_lfr_cal;
Show file before | Show file after | Hide comments
@@ -1,146 +1,146
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@member.fsf.org
21 21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.STD_LOGIC_1164.ALL;
22 LIBRARY IEEE;
23 USE IEEE.STD_LOGIC_1164.ALL;
24 24 LIBRARY techmap;
25 25 USE techmap.gencomp.ALL;
26 26
27 library lpp;
28 use lpp.lpp_cna.all;
27 LIBRARY lpp;
28 USE lpp.lpp_cna.ALL;
29 29
30 30
31 entity lfr_cal_driver is
32 generic(
33 tech : integer := 0;
34 PRESZ : integer range 1 to 32:=4;
35 PREMAX : integer := 16#FFFFFF#;
36 CPTSZ : integer range 1 to 32:=16;
37 datawidth : integer := 18;
38 abits : integer := 8
39 );
40 Port (
41 clk : in STD_LOGIC;
42 rstn : in STD_LOGIC;
43 pre : in STD_LOGIC_VECTOR(PRESZ-1 downto 0);
44 N : in STD_LOGIC_VECTOR(CPTSZ-1 downto 0);
45 Reload : in std_logic;
46 DATA_IN : in STD_LOGIC_VECTOR(datawidth-1 downto 0);
47 WEN : in STD_LOGIC;
48 LOAD_ADDRESSN : IN STD_LOGIC;
49 ADDRESS_IN : IN STD_LOGIC_VECTOR(abits-1 downto 0);
50 ADDRESS_OUT : OUT STD_LOGIC_VECTOR(abits-1 downto 0);
51 INTERLEAVED : IN STD_LOGIC;
52 DAC_CFG : IN STD_LOGIC_VECTOR(3 downto 0);
53 SYNC : out STD_LOGIC;
54 DOUT : out STD_LOGIC;
55 SCLK : out STD_LOGIC;
56 SMPCLK : out STD_lOGIC
57 );
58 end lfr_cal_driver;
59
60 architecture Behavioral of lfr_cal_driver is
61 constant dacresolution : integer := 12;
62 signal RAM_DATA_IN : STD_LOGIC_VECTOR(datawidth-1 downto 0);
63 signal RAM_WEN : STD_LOGIC;
64 signal RAM_WADDR : STD_LOGIC_VECTOR(abits-1 downto 0);
65 signal RAM_DATA_OUT : STD_LOGIC_VECTOR(datawidth-1 downto 0);
66 signal RAM_RADDR : STD_LOGIC_VECTOR(abits-1 downto 0);
67 signal RAM_REN : STD_LOGIC;
68 signal DAC_DATA : STD_LOGIC_VECTOR(dacresolution-1 downto 0);
69 signal SMP_CLK : STD_LOGIC;
70 signal DAC_INPUT : STD_LOGIC_VECTOR(15 downto 0);
71
72 begin
73
74 ADDRESS_OUT <= RAM_WADDR;
75 DAC_INPUT <= DAC_CFG & DAC_DATA;
76 SMPCLK <= SMP_CLK;
31 ENTITY lfr_cal_driver IS
32 GENERIC(
33 tech : INTEGER := 0;
34 PRESZ : INTEGER RANGE 1 TO 32 := 4;
35 PREMAX : INTEGER := 16#FFFFFF#;
36 CPTSZ : INTEGER RANGE 1 TO 32 := 16;
37 datawidth : INTEGER := 18;
38 abits : INTEGER := 8
39 );
40 PORT (
41 clk : IN STD_LOGIC;
42 rstn : IN STD_LOGIC;
43 pre : IN STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
44 N : IN STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
45 Reload : IN STD_LOGIC;
46 DATA_IN : IN STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
47 WEN : IN STD_LOGIC;
48 LOAD_ADDRESSN : IN STD_LOGIC;
49 ADDRESS_IN : IN STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
50 ADDRESS_OUT : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
51 INTERLEAVED : IN STD_LOGIC;
52 DAC_CFG : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
53 SYNC : OUT STD_LOGIC;
54 DOUT : OUT STD_LOGIC;
55 SCLK : OUT STD_LOGIC;
56 SMPCLK : OUT STD_LOGIC
57 );
58 END lfr_cal_driver;
77 59
78 dac_drv: SPI_DAC_DRIVER
79 Generic map(
80 datawidth => 16,
81 MSBFIRST => 1
82 )
83 Port map(
84 clk => clk,
85 rstn => rstn,
86 DATA => DAC_INPUT,
87 SMP_CLK => SMP_CLK,
88 SYNC => SYNC,
89 DOUT => DOUT,
90 SCLK => SCLK
91 );
60 ARCHITECTURE Behavioral OF lfr_cal_driver IS
61 CONSTANT dacresolution : INTEGER := 12;
62 SIGNAL RAM_DATA_IN : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
63 SIGNAL RAM_WEN : STD_LOGIC;
64 SIGNAL RAM_WADDR : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
65 SIGNAL RAM_DATA_OUT : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
66 SIGNAL RAM_RADDR : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
67 SIGNAL RAM_REN : STD_LOGIC;
68 SIGNAL DAC_DATA : STD_LOGIC_VECTOR(dacresolution-1 DOWNTO 0);
69 SIGNAL SMP_CLK : STD_LOGIC;
70 SIGNAL DAC_INPUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
71
72 BEGIN
73
74 ADDRESS_OUT <= RAM_WADDR;
75 DAC_INPUT <= DAC_CFG & DAC_DATA;
76 SMPCLK <= SMP_CLK;
92 77
93 freqGen: dynamic_freq_div
94 generic map(
95 PRESZ => PRESZ,
96 PREMAX => PREMAX,
97 CPTSZ => CPTSZ
98 )
99 Port map( clk => clk,
100 rstn => rstn,
101 pre => pre,
102 N => N,
103 Reload => Reload,
104 clk_out => SMP_CLK
105 );
106
107
108 ramWr: RAM_WRITER
109 Generic map(
110 datawidth => datawidth,
111 abits => abits
112 )
113 Port map(
114 clk => clk,
115 rstn => rstn,
116 DATA_IN => DATA_IN,
117 DATA_OUT => RAM_DATA_IN,
118 WEN_IN => WEN,
119 WEN_OUT => RAM_WEN,
120 LOAD_ADDRESSN => LOAD_ADDRESSN,
121 ADDRESS_IN => ADDRESS_IN,
122 ADDRESS_OUT => RAM_WADDR
123 );
124
125 ramRd: RAM_READER
126 Generic map(
127 datawidth => datawidth,
128 dacresolution => dacresolution,
129 abits => abits
130 )
131 Port map(
132 clk => clk,
133 rstn => rstn,
134 DATA_IN => RAM_DATA_OUT,
135 ADDRESS => RAM_RADDR,
136 REN => RAM_REN,
137 DATA_OUT => DAC_DATA,
138 SMP_CLK => SMP_CLK,
139 INTERLEAVED => INTERLEAVED
78 dac_drv : SPI_DAC_DRIVER
79 GENERIC MAP(
80 datawidth => 16,
81 MSBFIRST => 1
82 )
83 PORT MAP(
84 clk => clk,
85 rstn => rstn,
86 DATA => DAC_INPUT,
87 SMP_CLK => SMP_CLK,
88 SYNC => SYNC,
89 DOUT => DOUT,
90 SCLK => SCLK
91 );
92
93 freqGen : dynamic_freq_div
94 GENERIC MAP(
95 PRESZ => PRESZ,
96 PREMAX => PREMAX,
97 CPTSZ => CPTSZ
98 )
99 PORT MAP(clk => clk,
100 rstn => rstn,
101 pre => pre,
102 N => N,
103 Reload => Reload,
104 clk_out => SMP_CLK
140 105 );
141 106
142 SRAM : syncram_2p
143 GENERIC MAP(tech, abits, datawidth)
144 PORT MAP(clk, RAM_REN, RAM_RADDR, RAM_DATA_OUT, clk, RAM_WEN, RAM_WADDR, RAM_DATA_IN);
107
108 ramWr : RAM_WRITER
109 GENERIC MAP(
110 datawidth => datawidth,
111 abits => abits
112 )
113 PORT MAP(
114 clk => clk,
115 rstn => rstn,
116 DATA_IN => DATA_IN,
117 DATA_OUT => RAM_DATA_IN,
118 WEN_IN => WEN,
119 WEN_OUT => RAM_WEN,
120 LOAD_ADDRESSN => LOAD_ADDRESSN,
121 ADDRESS_IN => ADDRESS_IN,
122 ADDRESS_OUT => RAM_WADDR
123 );
145 124
146 end Behavioral;
125 ramRd : RAM_READER
126 GENERIC MAP(
127 datawidth => datawidth,
128 dacresolution => dacresolution,
129 abits => abits
130 )
131 PORT MAP(
132 clk => clk,
133 rstn => rstn,
134 DATA_IN => RAM_DATA_OUT,
135 ADDRESS => RAM_RADDR,
136 REN => RAM_REN,
137 DATA_OUT => DAC_DATA,
138 SMP_CLK => SMP_CLK,
139 INTERLEAVED => INTERLEAVED
140 );
141
142 SRAM : syncram_2p
143 GENERIC MAP(tech, abits, datawidth)
144 PORT MAP(clk, RAM_REN, RAM_RADDR, RAM_DATA_OUT, clk, RAM_WEN, RAM_WADDR, RAM_DATA_IN);
145
146 END Behavioral; No newline at end of file
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
General Comments 0
You need to be logged in to leave comments. Login now