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Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

LFR-em 1.1.35
pellion -
r467:10ba15a05d8c (LFR-EM) WFP_MS-1-1-35 JC
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@@ -364,7 +364,7 BEGIN -- beh
364 364 pirq_ms => 6,
365 365 pirq_wfp => 14,
366 366 hindex => 2,
367 top_lfr_version => X"010122") -- aa.bb.cc version
367 top_lfr_version => X"010123") -- aa.bb.cc version
368 368 -- AA : BOARD NUMBER
369 369 -- 0 => MINI_LFR
370 370 -- 1 => EM
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@@ -16,6 +16,7 USE techmap.gencomp.ALL;
16 16
17 17 LIBRARY lpp;
18 18 USE lpp.lpp_sim_pkg.ALL;
19 USE lpp.lpp_lfr_sim_pkg.ALL;
19 20 USE lpp.lpp_lfr_apbreg_pkg.ALL;
20 21 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
21 22
@@ -134,6 +135,9 ARCHITECTURE behav OF testbench IS
134 135
135 136
136 137 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
138
139 SIGNAL data_message : STRING(1 TO 15) := "---------------";
140 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
137 141
138 142 BEGIN
139 143
@@ -142,6 +146,7 BEGIN
142 146 -----------------------------------------------------------------------------
143 147 PROCESS
144 148 CONSTANT txp : TIME := 320 ns;
149 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 150 BEGIN -- PROCESS
146 151 TXD1 <= '1';
147 152 reset <= '0';
@@ -155,11 +160,15 BEGIN
155 160 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
156 161 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
157 162 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
158
163 UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v);
164 data_read <= data_read_v;
165 data_message <= "GPIO_data_write";
166
159 167 -- UNSET the LFR reset
160 168 message_simu <= "2 - LFR UNRESET";
161 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
162 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
169 UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT);
170 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
171 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
163 172 --
164 173 message_simu <= "3 - LFR CONFIG ";
165 174 UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
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@@ -7,10 +7,10 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 --USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
12 --USE lpp.lpp_top_lfr_pkg.ALL;
13 --USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.general_purpose.ALL;
15 15
16 16 LIBRARY techmap;
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@@ -7,10 +7,10 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 --USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
12 --USE lpp.lpp_top_lfr_pkg.ALL;
13 --USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.general_purpose.ALL;
15 15
16 16 LIBRARY techmap;
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@@ -7,10 +7,10 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 --USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
12 --USE lpp.lpp_top_lfr_pkg.ALL;
13 --USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.general_purpose.ALL;
15 15
16 16 LIBRARY techmap;
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@@ -37,7 +37,7 USE lpp.lpp_amba.ALL;
37 37 USE lpp.apb_devices_list.ALL;
38 38 USE lpp.lpp_memory.ALL;
39 39 USE lpp.lpp_dma_pkg.ALL;
40 USE lpp.lpp_waveform_pkg.ALL;
40 --USE lpp.lpp_waveform_pkg.ALL;
41 41 LIBRARY techmap;
42 42 USE techmap.gencomp.ALL;
43 43
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@@ -50,7 +50,15 PACKAGE lpp_sim_pkg IS
50 50 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
51 51 CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
52 52 );
53
53 PROCEDURE UART_READ (
54 SIGNAL TX : OUT STD_LOGIC;
55 SIGNAL RX : IN STD_LOGIC;
56 CONSTANT tx_period : IN TIME;
57 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
58 DATA : OUT STD_LOGIC_VECTOR
59 );
60
61
54 62 END lpp_sim_pkg;
55 63
56 64 PACKAGE BODY lpp_sim_pkg IS
@@ -101,4 +109,31 PACKAGE BODY lpp_sim_pkg IS
101 109 tx_period);
102 110 END;
103 111
112 PROCEDURE UART_READ (
113 SIGNAL TX : OUT STD_LOGIC;
114 SIGNAL RX : IN STD_LOGIC;
115 CONSTANT tx_period : IN TIME;
116 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
117 DATA : OUT STD_LOGIC_VECTOR )
118 IS
119 VARIABLE V_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
120 CONSTANT ADDR_last : STD_LOGIC_VECTOR(7 DOWNTO 0) := ADDR(7 DOWNTO 2) & "00";
121 BEGIN
122 txc(TX, 16#80#, tx_period);
123 txa(TX,
124 to_integer(UNSIGNED(ADDR(31 DOWNTO 24))),
125 to_integer(UNSIGNED(ADDR(23 DOWNTO 16))),
126 to_integer(UNSIGNED(ADDR(15 DOWNTO 8))),
127 to_integer(UNSIGNED(ADDR_last)),
128 tx_period);
129 rxc(RX,V_DATA,tx_period);
130 DATA(31 DOWNTO 24) := V_DATA;
131 rxc(RX,V_DATA,tx_period);
132 DATA(23 DOWNTO 16) := V_DATA;
133 rxc(RX,V_DATA,tx_period);
134 DATA(15 DOWNTO 8) := V_DATA;
135 rxc(RX,V_DATA,tx_period);
136 DATA(7 DOWNTO 0) := V_DATA;
137 END;
138
104 139 END lpp_sim_pkg;
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@@ -1,2 +1,3
1 1 lpp_sim_pkg.vhd
2 lpp_lfr_sim_pkg.vhd
2 3
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