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Modif DMA_SubSystem en cours
pellion -
r435:0d4ef716262e JC
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
15
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
18
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
25 ENTITY DMA_SubSystem IS
26
27 GENERIC (
28 hindex : INTEGER := 2);
29
30 PORT (
31 clk : IN STD_LOGIC;
32 rstn : IN STD_LOGIC;
33 run : IN STD_LOGIC;
34 -- AHB
35 ahbi : IN AHB_Mst_In_Type;
36 ahbo : OUT AHB_Mst_Out_Type;
37 ---------------------------------------------------------------------------
38 fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
40 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
41 ---------------------------------------------------------------------------
42 buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
43 buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
44 buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
45 buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
47 ---------------------------------------------------------------------------
48 grant_error : OUT STD_LOGIC --
49
50 );
51
52 END DMA_SubSystem;
53
54
55 ARCHITECTURE beh OF DMA_SubSystem IS
56
57 COMPONENT DMA_SubSystem_GestionBuffer
58 GENERIC (
59 BUFFER_ADDR_SIZE : INTEGER;
60 BUFFER_LENGTH_SIZE : INTEGER);
61 PORT (
62 clk : IN STD_LOGIC;
63 rstn : IN STD_LOGIC;
64 run : IN STD_LOGIC;
65 buffer_new : IN STD_LOGIC;
66 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
67 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
68 buffer_full : OUT STD_LOGIC;
69 buffer_full_err : OUT STD_LOGIC;
70 burst_send : IN STD_LOGIC;
71 burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
72 END COMPONENT;
73
74 COMPONENT DMA_SubSystem_Arbiter
75 PORT (
76 clk : IN STD_LOGIC;
77 rstn : IN STD_LOGIC;
78 run : IN STD_LOGIC;
79 data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
80 data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
81 END COMPONENT;
82
83 COMPONENT DMA_SubSystem_MUX
84 PORT (
85 clk : IN STD_LOGIC;
86 rstn : IN STD_LOGIC;
87 run : IN STD_LOGIC;
88 fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
89 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
90 fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
91 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
92 fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
93 dma_send : OUT STD_LOGIC;
94 dma_valid_burst : OUT STD_LOGIC;
95 dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 dma_ren : IN STD_LOGIC;
98 dma_done : IN STD_LOGIC;
99 grant_error : OUT STD_LOGIC);
100 END COMPONENT;
101
102 -----------------------------------------------------------------------------
103 SIGNAL dma_send : STD_LOGIC;
104 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
105 SIGNAL dma_done : STD_LOGIC;
106 SIGNAL dma_ren : STD_LOGIC;
107 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL burst_send : STD_LOGIC_VECTOR(4 DOWNTO 0);
110 SIGNAL fifo_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
111 SIGNAL fifo_address : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --
112
113
114 BEGIN -- beh
115
116 -----------------------------------------------------------------------------
117 -- DMA
118 -----------------------------------------------------------------------------
119 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
120 GENERIC MAP (
121 tech => inferred,
122 hindex => hindex)
123 PORT MAP (
124 HCLK => clk,
125 HRESETn => rstn,
126 run => run,
127 AHB_Master_In => ahbi,
128 AHB_Master_Out => ahbo,
129
130 send => dma_send,
131 valid_burst => dma_valid_burst,
132 done => dma_done,
133 ren => dma_ren,
134 address => dma_address,
135 data => dma_data);
136
137
138 -----------------------------------------------------------------------------
139 -- RoundRobin Selection Channel For DMA
140 -----------------------------------------------------------------------------
141 DMA_SubSystem_Arbiter_1: DMA_SubSystem_Arbiter
142 PORT MAP (
143 clk => clk,
144 rstn => rstn,
145 run => run,
146 data_burst_valid => fifo_burst_valid,
147 data_burst_valid_grant => fifo_grant);
148
149
150 -----------------------------------------------------------------------------
151 -- Mux between the channel from Waveform Picker and Spectral Matrix
152 -----------------------------------------------------------------------------
153 DMA_SubSystem_MUX_1: DMA_SubSystem_MUX
154 PORT MAP (
155 clk => clk,
156 rstn => rstn,
157 run => run,
158
159 fifo_grant => fifo_grant,
160 fifo_data => fifo_data,
161 fifo_address => fifo_address,
162 fifo_ren => fifo_ren,
163 fifo_burst_done => burst_send,
164
165 dma_send => dma_send,
166 dma_valid_burst => dma_valid_burst,
167 dma_address => dma_address,
168 dma_data => dma_data,
169 dma_ren => dma_ren,
170 dma_done => dma_done,
171
172 grant_error => grant_error);
173
174
175 -----------------------------------------------------------------------------
176 -- GEN ADDR
177 -----------------------------------------------------------------------------
178 all_buffer : FOR I IN 4 DOWNTO 0 GENERATE
179 DMA_SubSystem_GestionBuffer_I : DMA_SubSystem_GestionBuffer
180 GENERIC MAP (
181 BUFFER_ADDR_SIZE => 32,
182 BUFFER_LENGTH_SIZE => 26)
183 PORT MAP (
184 clk => clk,
185 rstn => rstn,
186 run => run,
187
188 buffer_new => buffer_new(I),
189 buffer_addr => buffer_addr(32*(I+1)-1 DOWNTO I*32),
190 buffer_length => buffer_length(26*(I+1)-1 DOWNTO I*26),
191 buffer_full => buffer_full(I),
192 buffer_full_err => buffer_full_err(I),
193
194 burst_send => burst_send(I),
195 burst_addr => fifo_address(32*(I+1)-1 DOWNTO 32*I)
196 );
197 END GENERATE all_buffer;
198
199
200
201 END beh;
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
15
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
18
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
25 ENTITY DMA_SubSystem_Arbiter IS
26
27 PORT (
28 clk : IN STD_LOGIC;
29 rstn : IN STD_LOGIC;
30 run : IN STD_LOGIC;
31 --
32 data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
34 );
35
36 END DMA_SubSystem_Arbiter;
37
38
39 ARCHITECTURE beh OF DMA_SubSystem_Arbiter IS
40
41 SIGNAL data_burst_valid_r : STD_LOGIC_VECTOR(4 DOWNTO 0);
42 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
43 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
44 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
45
46 BEGIN -- beh
47 -----------------------------------------------------------------------------
48 -- REG the burst valid signal
49 -----------------------------------------------------------------------------
50 PROCESS (clk, rstn)
51 BEGIN -- PROCESS
52 IF rstn = '0' THEN -- asynchronous reset (active low)
53 data_burst_valid_r <= (OTHERS => '0');
54 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
55 IF run = '1' THEN
56 data_burst_valid_r <= data_burst_valid;
57 ELSE
58 data_burst_valid_r <= (OTHERS => '0');
59 END IF;
60
61 END IF;
62 END PROCESS;
63
64 -----------------------------------------------------------------------------
65 -- ARBITER Between all the "WAVEFORM_PICKER" channel
66 -----------------------------------------------------------------------------
67 RR_Arbiter_4_1 : RR_Arbiter_4
68 PORT MAP (
69 clk => clk,
70 rstn => rstn,
71 in_valid => data_burst_valid_r(3 DOWNTO 0),
72 out_grant => dma_rr_grant_s);
73
74 dma_rr_valid_ms(0) <= data_burst_valid_r(4);--data_ms_valid OR data_ms_valid_burst;
75 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
76 dma_rr_valid_ms(2) <= '0';
77 dma_rr_valid_ms(3) <= '0';
78
79 -----------------------------------------------------------------------------
80 -- ARBITER Between all the "WAVEFORM_PICKER" and "SPECTRAL MATRIX"
81 -----------------------------------------------------------------------------
82
83 RR_Arbiter_4_2 : RR_Arbiter_4
84 PORT MAP (
85 clk => clk,
86 rstn => rstn,
87 in_valid => dma_rr_valid_ms,
88 out_grant => dma_rr_grant_ms);
89
90 data_burst_valid_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
91
92
93
94 END beh;
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1
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
4 USE ieee.numeric_std.ALL;
5
6 ENTITY DMA_SubSystem_GestionBuffer IS
7 GENERIC (
8 BUFFER_ADDR_SIZE : INTEGER := 32;
9 BUFFER_LENGTH_SIZE : INTEGER := 26);
10 PORT (
11 clk : IN STD_LOGIC;
12 rstn : IN STD_LOGIC;
13 run : IN STD_LOGIC;
14 --
15 buffer_new : IN STD_LOGIC;
16 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
17 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0); --in 64B
18 buffer_full : OUT STD_LOGIC;
19 buffer_full_err : OUT STD_LOGIC;
20 --
21 burst_send : IN STD_LOGIC;
22 burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0)
23 );
24 END DMA_SubSystem_GestionBuffer;
25
26
27 ARCHITECTURE beh OF DMA_SubSystem_GestionBuffer IS
28
29 TYPE state_DMA_GestionBuffer IS (IDLE, ON_GOING);
30 SIGNAL state : state_DMA_GestionBuffer;
31
32 SIGNAL burst_send_counter : STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
33 SIGNAL burst_send_counter_add1 : STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
34 SIGNAL addr_shift : STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
35
36 BEGIN
37 addr_shift <= burst_send_counter & "000000";
38 burst_addr <= STD_LOGIC_VECTOR(unsigned(buffer_addr) + unsigned(addr_shift));
39
40 burst_send_counter_add1 <= STD_LOGIC_VECTOR(unsigned(burst_send_counter) + 1);
41
42 PROCESS (clk, rstn)
43 BEGIN -- PROCESS
44 IF rstn = '0' THEN -- asynchronous reset (active low)
45 burst_send_counter <= (OTHERS => '0');
46 state <= IDLE;
47 buffer_full <= '0';
48 buffer_full_err <= '0';
49 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
50 CASE state IS
51 WHEN IDLE =>
52 burst_send_counter <= (OTHERS => '0');
53 buffer_full_err <= burst_send;
54 buffer_full <= '0';
55 IF buffer_new = '1' THEN
56 state <= ON_GOING;
57 END IF;
58
59 WHEN ON_GOING =>
60 buffer_full_err <= '0';
61 buffer_full <= '0';
62 IF burst_send = '1' THEN
63 IF burst_send_counter_add1 < buffer_length THEN
64 burst_send_counter <= burst_send_counter_add1;
65 ELSE
66 buffer_full <= '1';
67 state <= IDLE;
68 END IF;
69 END IF;
70
71 WHEN OTHERS => NULL;
72 END CASE;
73 END IF;
74 END PROCESS;
75
76 END beh;
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
15
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
18
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
25 ENTITY DMA_SubSystem_MUX IS
26
27 PORT (
28 clk : IN STD_LOGIC;
29 rstn : IN STD_LOGIC;
30 run : IN STD_LOGIC;
31 --
32 fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --
34 fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --
35 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --
36 fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
37 --
38 dma_send : OUT STD_LOGIC;
39 dma_valid_burst : OUT STD_LOGIC; --
40 dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
41 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
42 dma_ren : IN STD_LOGIC; --
43 dma_done : IN STD_LOGIC; --
44 --
45 grant_error : OUT STD_LOGIC --
46 );
47
48 END DMA_SubSystem_MUX;
49
50 ARCHITECTURE beh OF DMA_SubSystem_MUX IS
51 SIGNAL channel_ongoing : STD_LOGIC_VECTOR(4 DOWNTO 0);
52 SIGNAL one_grant : STD_LOGIC;
53 SIGNAL more_than_one_grant : STD_LOGIC;
54
55 BEGIN
56
57 one_grant <= '0' WHEN fifo_grant = "00000" ELSE '1';
58 more_than_one_grant <= '0' WHEN fifo_grant = "00000" OR
59 fifo_grant = "00001" OR
60 fifo_grant = "00010" OR
61 fifo_grant = "00100" OR
62 fifo_grant = "01000" OR
63 fifo_grant = "10000" ELSE '1';
64
65 PROCESS (clk, rstn)
66 BEGIN -- PROCESS
67 IF rstn = '0' THEN -- asynchronous reset (active low)
68 channel_ongoing <= (OTHERS => '0');
69 fifo_burst_done <= (OTHERS => '0');
70 dma_send <= '0';
71 dma_valid_burst <= '0';
72 grant_error <= '0';
73 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
74 grant_error <= '0';
75 IF run = '1' THEN
76 IF dma_done = '1' THEN
77 fifo_burst_done <= channel_ongoing;
78 ELSE
79 fifo_burst_done <= (OTHERS => '0');
80 END IF;
81
82 IF channel_ongoing = "00000" OR dma_done = '1' THEN
83 channel_ongoing <= fifo_grant;
84 grant_error <= more_than_one_grant;
85 dma_valid_burst <= one_grant;
86 dma_send <= one_grant;
87 ELSE
88 dma_send <= '0';
89 END IF;
90
91 ELSE
92 channel_ongoing <= (OTHERS => '0');
93 fifo_burst_done <= (OTHERS => '0');
94 dma_send <= '0';
95 dma_valid_burst <= '0';
96 END IF;
97 END IF;
98 END PROCESS;
99
100 -------------------------------------------------------------------------
101
102 all_channel : FOR I IN 4 DOWNTO 0 GENERATE
103 fifo_ren(I) <= dma_ren WHEN channel_ongoing(I) = '1' ELSE '1';
104 END GENERATE all_channel;
105
106 dma_data <= fifo_data(32*1-1 DOWNTO 32*0) WHEN channel_ongoing(0) = '1' ELSE
107 fifo_data(32*2-1 DOWNTO 32*1) WHEN channel_ongoing(1) = '1' ELSE
108 fifo_data(32*3-1 DOWNTO 32*2) WHEN channel_ongoing(2) = '1' ELSE
109 fifo_data(32*4-1 DOWNTO 32*3) WHEN channel_ongoing(3) = '1' ELSE
110 fifo_data(32*5-1 DOWNTO 32*4); --WHEN channel_ongoing(4) = '1' ELSE
111
112 dma_address <= fifo_address(32*1-1 DOWNTO 32*0) WHEN channel_ongoing(0) = '1' ELSE
113 fifo_address(32*2-1 DOWNTO 32*1) WHEN channel_ongoing(1) = '1' ELSE
114 fifo_address(32*3-1 DOWNTO 32*2) WHEN channel_ongoing(2) = '1' ELSE
115 fifo_address(32*4-1 DOWNTO 32*3) WHEN channel_ongoing(3) = '1' ELSE
116 fifo_address(32*5-1 DOWNTO 32*4); --WHEN channel_ongoing(4) = '1' ELSE
117
118 END beh;
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@@ -428,7 +428,7 BEGIN -- beh
428 428 pirq_ms => 6,
429 429 pirq_wfp => 14,
430 430 hindex => 2,
431 top_lfr_version => X"00011B") -- aa.bb.cc version
431 top_lfr_version => X"00011C") -- aa.bb.cc version
432 432 PORT MAP (
433 433 clk => clk_25,
434 434 rstn => reset,
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@@ -216,5 +216,74 PACKAGE lpp_dma_pkg IS
216 216 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
217 217 debug_dmaout_okay : OUT STD_LOGIC);
218 218 END COMPONENT;
219
220
221 -----------------------------------------------------------------------------
222 -- DMA_SubSystem
223 -----------------------------------------------------------------------------
224 COMPONENT DMA_SubSystem
225 GENERIC (
226 hindex : INTEGER);
227 PORT (
228 clk : IN STD_LOGIC;
229 rstn : IN STD_LOGIC;
230 run : IN STD_LOGIC;
231 ahbi : IN AHB_Mst_In_Type;
232 ahbo : OUT AHB_Mst_Out_Type;
233 fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
234 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
235 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
236 buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
237 buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
238 buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
239 buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
240 buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
241 grant_error : OUT STD_LOGIC);
242 END COMPONENT;
243
244 COMPONENT DMA_SubSystem_GestionBuffer
245 GENERIC (
246 BUFFER_ADDR_SIZE : INTEGER;
247 BUFFER_LENGTH_SIZE : INTEGER);
248 PORT (
249 clk : IN STD_LOGIC;
250 rstn : IN STD_LOGIC;
251 run : IN STD_LOGIC;
252 buffer_new : IN STD_LOGIC;
253 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
254 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
255 buffer_full : OUT STD_LOGIC;
256 buffer_full_err : OUT STD_LOGIC;
257 burst_send : IN STD_LOGIC;
258 burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
259 END COMPONENT;
260
261 COMPONENT DMA_SubSystem_Arbiter
262 PORT (
263 clk : IN STD_LOGIC;
264 rstn : IN STD_LOGIC;
265 run : IN STD_LOGIC;
266 data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
267 data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
268 END COMPONENT;
269
270 COMPONENT DMA_SubSystem_MUX
271 PORT (
272 clk : IN STD_LOGIC;
273 rstn : IN STD_LOGIC;
274 run : IN STD_LOGIC;
275 fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
276 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
277 fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
278 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
279 fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
280 dma_send : OUT STD_LOGIC;
281 dma_valid_burst : OUT STD_LOGIC;
282 dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
283 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
284 dma_ren : IN STD_LOGIC;
285 dma_done : IN STD_LOGIC;
286 grant_error : OUT STD_LOGIC);
287 END COMPONENT;
219 288
220 289 END;
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@@ -5,3 +5,7 lpp_dma_ip.vhd
5 5 lpp_dma_send_16word.vhd
6 6 lpp_dma_send_1word.vhd
7 7 lpp_dma_singleOrBurst.vhd
8 DMA_SubSystem.vhd
9 DMA_SubSystem_GestionBuffer.vhd
10 DMA_SubSystem_Arbiter.vhd
11 DMA_SubSystem_MUX.vhd
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@@ -59,13 +59,13 ENTITY lpp_lfr IS
59 59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 61 --
62 data_shaping_BW : OUT STD_LOGIC;
62 data_shaping_BW : OUT STD_LOGIC
63 63 --
64 64 --
65 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
66 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
67
68 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
65 -- observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
66 -- observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
67
68 -- observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
69 69
70 70 --debug
71 71 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
@@ -138,25 +138,27 ARCHITECTURE beh OF lpp_lfr IS
138 138 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
139 139
140 140 -- SM
141 SIGNAL ready_matrix_f0 : STD_LOGIC;
142 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
143 SIGNAL ready_matrix_f1 : STD_LOGIC;
144 SIGNAL ready_matrix_f2 : STD_LOGIC;
141 SIGNAL ready_matrix_f0 : STD_LOGIC;
142 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
143 SIGNAL ready_matrix_f1 : STD_LOGIC;
144 SIGNAL ready_matrix_f2 : STD_LOGIC;
145 145 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
146 SIGNAL error_bad_component_error : STD_LOGIC;
146 -- SIGNAL error_bad_component_error : STD_LOGIC;
147 147 -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
149 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
150 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
151 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
148 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
149 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
150 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
151 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
152 152 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
153 153 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
154 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
155 SIGNAL config_active_interruption_onError : STD_LOGIC;
156 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 --SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
155 -- SIGNAL config_active_interruption_onError : STD_LOGIC;
156 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
160 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
161 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
160 162
161 163 -- WFP
162 164 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
@@ -278,19 +280,30 ARCHITECTURE beh OF lpp_lfr IS
278 280
279 281 SIGNAL run_ms : STD_LOGIC;
280 282 SIGNAL ms_softandhard_rstn : STD_LOGIC;
281
282 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
283
284 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
283 285 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
284 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
285 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
286
286 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
287 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
288
289
290 SIGNAL error_buffer_full : STD_LOGIC;
291 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
292
293 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
294 SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
295
296 -----------------------------------------------------------------------------
297 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
298 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
299 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
300 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
301 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
302 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
303 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
304 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
305 SIGNAL dma_grant_error : STD_LOGIC;
287 306
288 SIGNAL error_buffer_full : STD_LOGIC;
289 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
290
291 SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
292 SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
293
294 307 BEGIN
295 308
296 309 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
@@ -345,33 +358,26 BEGIN
345 358
346 359 run_ms => run_ms,
347 360
348 ready_matrix_f0 => ready_matrix_f0,
349 -- ready_matrix_f0_1 => ready_matrix_f0_1,
350 ready_matrix_f1 => ready_matrix_f1,
351 ready_matrix_f2 => ready_matrix_f2,
352 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
353 error_bad_component_error => error_bad_component_error,
354 error_buffer_full => error_buffer_full, -- TODO
355 error_input_fifo_write => error_input_fifo_write, -- TODO
356 -- debug_reg => debug_reg,
357 status_ready_matrix_f0 => status_ready_matrix_f0,
358 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
359 status_ready_matrix_f1 => status_ready_matrix_f1,
360 status_ready_matrix_f2 => status_ready_matrix_f2,
361 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
362 -- status_error_bad_component_error => status_error_bad_component_error,
363 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
364 config_active_interruption_onError => config_active_interruption_onError,
361 ready_matrix_f0 => ready_matrix_f0,
362 ready_matrix_f1 => ready_matrix_f1,
363 ready_matrix_f2 => ready_matrix_f2,
364 error_buffer_full => error_buffer_full, -- TODO
365 error_input_fifo_write => error_input_fifo_write, -- TODO
366 status_ready_matrix_f0 => status_ready_matrix_f0,
367 status_ready_matrix_f1 => status_ready_matrix_f1,
368 status_ready_matrix_f2 => status_ready_matrix_f2,
365 369
366 370 matrix_time_f0 => matrix_time_f0,
367 -- matrix_time_f0_1 => matrix_time_f0_1,
368 matrix_time_f1 => matrix_time_f1,
369 matrix_time_f2 => matrix_time_f2,
371 matrix_time_f1 => matrix_time_f1,
372 matrix_time_f2 => matrix_time_f2,
370 373
371 addr_matrix_f0 => addr_matrix_f0,
372 -- addr_matrix_f0_1 => addr_matrix_f0_1,
373 addr_matrix_f1 => addr_matrix_f1,
374 addr_matrix_f2 => addr_matrix_f2,
374 addr_matrix_f0 => addr_matrix_f0,
375 addr_matrix_f1 => addr_matrix_f1,
376 addr_matrix_f2 => addr_matrix_f2,
377
378 length_matrix_f0 => length_matrix_f0,
379 length_matrix_f1 => length_matrix_f1,
380 length_matrix_f2 => length_matrix_f2,
375 381 -------------------------------------------------------------------------
376 382 status_full => status_full,
377 383 status_full_ack => status_full_ack,
@@ -452,19 +458,19 BEGIN
452 458 --f0
453 459 addr_data_f0 => addr_data_f0,
454 460 data_f0_in_valid => sample_f0_val,
455 data_f0_in => sample_f0_data,
461 data_f0_in => sample_f0_data,
456 462 --f1
457 463 addr_data_f1 => addr_data_f1,
458 464 data_f1_in_valid => sample_f1_val,
459 data_f1_in => sample_f1_data,
465 data_f1_in => sample_f1_data,
460 466 --f2
461 467 addr_data_f2 => addr_data_f2,
462 468 data_f2_in_valid => sample_f2_val,
463 data_f2_in => sample_f2_data,
469 data_f2_in => sample_f2_data,
464 470 --f3
465 471 addr_data_f3 => addr_data_f3,
466 472 data_f3_in_valid => sample_f3_val,
467 data_f3_in => sample_f3_data,
473 data_f3_in => sample_f3_data,
468 474 -- OUTPUT -- DMA interface
469 475 --f0
470 476 data_f0_addr_out => data_f0_addr_out_s,
@@ -492,7 +498,7 BEGIN
492 498 data_f3_data_out_ren => data_f3_data_out_ren ,
493 499
494 500 -------------------------------------------------------------------------
495 observation_reg => OPEN
501 observation_reg => OPEN
496 502
497 503 );
498 504
@@ -605,8 +611,8 BEGIN
605 611 dma_send <= '1';
606 612 dma_valid_burst <= data_ms_valid_burst;
607 613 dma_sel_valid <= data_ms_valid;
608 --ELSE
609 --dma_ms_ongoing <= '0';
614 --ELSE
615 --dma_ms_ongoing <= '0';
610 616 END IF;
611 617
612 618 IF dma_ms_ongoing = '1' AND dma_done = '1' THEN
@@ -658,8 +664,8 BEGIN
658 664 HCLK => clk,
659 665 HRESETn => rstn,
660 666 run => run,
661 AHB_Master_In => ahbi,
662 AHB_Master_Out => ahbo,
667 AHB_Master_In => OPEN,
668 AHB_Master_Out => OPEN,
663 669
664 670 send => dma_send,
665 671 valid_burst => dma_valid_burst,
@@ -693,6 +699,7 BEGIN
693 699 PORT MAP (
694 700 clk => clk,
695 701 rstn => ms_softandhard_rstn, --rstn,
702 run => run_ms,
696 703
697 704 coarse_time => coarse_time,
698 705 fine_time => fine_time,
@@ -701,51 +708,64 BEGIN
701 708 sample_f0_wdata => sample_f0_wdata,
702 709 sample_f1_wen => sample_f1_wen,
703 710 sample_f1_wdata => sample_f1_wdata,
704 sample_f2_wen => sample_f2_wen, -- TODO
705 sample_f2_wdata => sample_f2_wdata,-- TODO
711 sample_f2_wen => sample_f2_wen,
712 sample_f2_wdata => sample_f2_wdata,
706 713
707 dma_addr => data_ms_addr, --
708 dma_data => data_ms_data, --
709 dma_valid => data_ms_valid, --
710 dma_valid_burst => data_ms_valid_burst, --
711 dma_ren => data_ms_ren, --
712 dma_done => data_ms_done, --
714 --DMA
715 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
716 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
717 dma_fifo_ren => dma_fifo_ren(4), -- IN
718 dma_buffer_new => dma_buffer_new(4), -- OUT
719 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
720 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
721 dma_buffer_full => dma_buffer_full(4), -- IN
722 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
723
724
713 725
714 ready_matrix_f0 => ready_matrix_f0,
715 ready_matrix_f1 => ready_matrix_f1,
716 ready_matrix_f2 => ready_matrix_f2,
717 error_bad_component_error => error_bad_component_error,
718 error_buffer_full => error_buffer_full,
719 error_input_fifo_write => error_input_fifo_write,
720
721 debug_reg => debug_ms,--observation_reg,
722 observation_vector_0 => observation_vector_0,
723 observation_vector_1 => observation_vector_1,
724
725 status_ready_matrix_f0 => status_ready_matrix_f0,
726 status_ready_matrix_f1 => status_ready_matrix_f1,
727 status_ready_matrix_f2 => status_ready_matrix_f2,
728 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
729 config_active_interruption_onError => config_active_interruption_onError,
730 addr_matrix_f0 => addr_matrix_f0,
731 addr_matrix_f1 => addr_matrix_f1,
732 addr_matrix_f2 => addr_matrix_f2,
726 --REG
727 ready_matrix_f0 => ready_matrix_f0,
728 ready_matrix_f1 => ready_matrix_f1,
729 ready_matrix_f2 => ready_matrix_f2,
730 error_buffer_full => error_buffer_full,
731 error_input_fifo_write => error_input_fifo_write,
733 732
734 matrix_time_f0 => matrix_time_f0,
735 matrix_time_f1 => matrix_time_f1,
736 matrix_time_f2 => matrix_time_f2);
733 status_ready_matrix_f0 => status_ready_matrix_f0,
734 status_ready_matrix_f1 => status_ready_matrix_f1,
735 status_ready_matrix_f2 => status_ready_matrix_f2,
736 addr_matrix_f0 => addr_matrix_f0,
737 addr_matrix_f1 => addr_matrix_f1,
738 addr_matrix_f2 => addr_matrix_f2,
739
740 length_matrix_f0 => length_matrix_f0,
741 length_matrix_f1 => length_matrix_f1,
742 length_matrix_f2 => length_matrix_f2,
743
744 matrix_time_f0 => matrix_time_f0,
745 matrix_time_f1 => matrix_time_f1,
746 matrix_time_f2 => matrix_time_f2);
737 747
738 748 -----------------------------------------------------------------------------
739 749
740
741 observation_reg(31 DOWNTO 0) <=
742 dma_sel(4) & -- 31
743 dma_ms_ongoing & -- 30
744 data_ms_done & -- 29
745 dma_done & -- 28
746 ms_softandhard_rstn & --27
747 debug_ms(14 DOWNTO 12) & -- 26 .. 24
748 debug_ms(11 DOWNTO 0) & -- 23 .. 12
749 debug_signal(11 DOWNTO 0); -- 11 .. 0
750
750 DMA_SubSystem_1 : DMA_SubSystem
751 GENERIC MAP (
752 hindex => hindex)
753 PORT MAP (
754 clk => clk,
755 rstn => rstn,
756 run => run_ms,
757 ahbi => ahbi,
758 ahbo => ahbo,
759
760 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
761 fifo_data => dma_fifo_data, --fifo_data,
762 fifo_ren => dma_fifo_ren, --fifo_ren,
763
764 buffer_new => dma_buffer_new, --buffer_new,
765 buffer_addr => dma_buffer_addr, --buffer_addr,
766 buffer_length => dma_buffer_length, --buffer_length,
767 buffer_full => dma_buffer_full, --buffer_full,
768 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
769 grant_error => dma_grant_error); --grant_error);
770
751 771 END beh;
Show file before | Show file after | Hide comments
@@ -66,7 +66,7 ENTITY lpp_lfr_apbreg IS
66 66 ready_matrix_f1 : IN STD_LOGIC;
67 67 ready_matrix_f2 : IN STD_LOGIC;
68 68
69 error_bad_component_error : IN STD_LOGIC;
69 -- error_bad_component_error : IN STD_LOGIC;
70 70 error_buffer_full : IN STD_LOGIC; -- TODO
71 71 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
72 72
@@ -77,13 +77,17 ENTITY lpp_lfr_apbreg IS
77 77 status_ready_matrix_f1 : OUT STD_LOGIC;
78 78 status_ready_matrix_f2 : OUT STD_LOGIC;
79 79
80 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
81 config_active_interruption_onError : OUT STD_LOGIC;
80 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
81 --config_active_interruption_onError : OUT STD_LOGIC;
82 82
83 83 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 84 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 85 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 86
87 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
88 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
89 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
90
87 91 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
88 92 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
89 93 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
@@ -154,7 +158,7 ARCHITECTURE beh OF lpp_lfr_apbreg IS
154 158 status_ready_matrix_f0_1 : STD_LOGIC;
155 159 status_ready_matrix_f1_1 : STD_LOGIC;
156 160 status_ready_matrix_f2_1 : STD_LOGIC;
157 status_error_bad_component_error : STD_LOGIC;
161 -- status_error_bad_component_error : STD_LOGIC;
158 162 status_error_buffer_full : STD_LOGIC;
159 163 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
160 164
@@ -165,6 +169,8 ARCHITECTURE beh OF lpp_lfr_apbreg IS
165 169 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
166 170 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 171
172 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
173
168 174 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
169 175 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
170 176 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
@@ -255,8 +261,8 BEGIN -- beh
255 261 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
256 262 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
257 263
258 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
259 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
264 -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
265 -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
260 266
261 267
262 268 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
@@ -298,6 +304,11 BEGIN -- beh
298 304
299 305 start_date <= reg_wp.start_date;
300 306
307 length_matrix_f0 <= reg_sp.length_matrix;
308 length_matrix_f1 <= reg_sp.length_matrix;
309 length_matrix_f2 <= reg_sp.length_matrix;
310
311
301 312 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
302 313 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
303 314 BEGIN -- PROCESS lpp_dma_top
@@ -311,7 +322,7 BEGIN -- beh
311 322 reg_sp.status_ready_matrix_f0_1 <= '0';
312 323 reg_sp.status_ready_matrix_f1_1 <= '0';
313 324 reg_sp.status_ready_matrix_f2_1 <= '0';
314 reg_sp.status_error_bad_component_error <= '0';
325 -- reg_sp.status_error_bad_component_error <= '0';
315 326 reg_sp.status_error_buffer_full <= '0';
316 327 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
317 328
@@ -323,6 +334,8 BEGIN -- beh
323 334 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
324 335 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
325 336
337 reg_sp.length_matrix <= (OTHERS => '0');
338
326 339 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
327 340 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
328 341 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
@@ -382,7 +395,7 BEGIN -- beh
382 395 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
383 396 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
384 397
385 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
398 -- reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
386 399
387 400 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
388 401 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
@@ -414,7 +427,7 BEGIN -- beh
414 427 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
415 428 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
416 429 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
417 prdata(6) <= reg_sp.status_error_bad_component_error;
430 -- prdata(6) <= reg_sp.status_error_bad_component_error;
418 431 prdata(7) <= reg_sp.status_error_buffer_full;
419 432 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
420 433 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
@@ -455,16 +468,18 BEGIN -- beh
455 468 WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
456 469 --19
457 470 WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
471 --20
472 WHEN "010100" => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
458 473 ---------------------------------------------------------------------
459 474 --20
460 WHEN "010100" => prdata(0) <= reg_wp.data_shaping_BW;
475 WHEN "010101" => prdata(0) <= reg_wp.data_shaping_BW;
461 476 prdata(1) <= reg_wp.data_shaping_SP0;
462 477 prdata(2) <= reg_wp.data_shaping_SP1;
463 478 prdata(3) <= reg_wp.data_shaping_R0;
464 479 prdata(4) <= reg_wp.data_shaping_R1;
465 480 prdata(5) <= reg_wp.data_shaping_R2;
466 481 --21
467 WHEN "010101" => prdata(0) <= reg_wp.enable_f0;
482 WHEN "010110" => prdata(0) <= reg_wp.enable_f0;
468 483 prdata(1) <= reg_wp.enable_f1;
469 484 prdata(2) <= reg_wp.enable_f2;
470 485 prdata(3) <= reg_wp.enable_f3;
@@ -473,35 +488,35 BEGIN -- beh
473 488 prdata(6) <= reg_wp.burst_f2;
474 489 prdata(7) <= reg_wp.run;
475 490 --22
476 WHEN "010110" => prdata <= reg_wp.addr_data_f0;
491 WHEN "010111" => prdata <= reg_wp.addr_data_f0;
477 492 --23
478 WHEN "010111" => prdata <= reg_wp.addr_data_f1;
493 WHEN "011000" => prdata <= reg_wp.addr_data_f1;
479 494 --24
480 WHEN "011000" => prdata <= reg_wp.addr_data_f2;
495 WHEN "011001" => prdata <= reg_wp.addr_data_f2;
481 496 --25
482 WHEN "011001" => prdata <= reg_wp.addr_data_f3;
497 WHEN "011010" => prdata <= reg_wp.addr_data_f3;
483 498 --26
484 WHEN "011010" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
499 WHEN "011011" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
485 500 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
486 501 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
487 502 --27
488 WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
503 WHEN "011100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
489 504 --28
490 WHEN "011100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
505 WHEN "011101" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
491 506 --29
492 WHEN "011101" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
507 WHEN "011110" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
493 508 --30
494 WHEN "011110" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
509 WHEN "011111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
495 510 --31
496 WHEN "011111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
511 WHEN "100000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
497 512 --32
498 WHEN "100000" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
513 WHEN "100001" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
499 514 --33
500 WHEN "100001" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
515 WHEN "100010" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
501 516 --34
502 WHEN "100010" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
517 WHEN "100011" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
503 518 --35
504 WHEN "100011" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
519 WHEN "100100" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
505 520 ----------------------------------------------------
506 521 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
507 522 WHEN OTHERS => NULL;
@@ -522,7 +537,6 BEGIN -- beh
522 537 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
523 538 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
524 539 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
525 reg_sp.status_error_bad_component_error <= ((NOT apbi.pwdata(6) ) AND reg_sp.status_error_bad_component_error) OR error_bad_component_error;
526 540 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
527 541 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
528 542 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
@@ -536,13 +550,15 BEGIN -- beh
536 550 WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
537 551 --8 to 19
538 552 --20
539 WHEN "010100" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
553 WHEN "010100" => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
554 --20
555 WHEN "010101" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
540 556 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
541 557 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
542 558 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
543 559 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
544 560 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
545 WHEN "010101" => reg_wp.enable_f0 <= apbi.pwdata(0);
561 WHEN "010110" => reg_wp.enable_f0 <= apbi.pwdata(0);
546 562 reg_wp.enable_f1 <= apbi.pwdata(1);
547 563 reg_wp.enable_f2 <= apbi.pwdata(2);
548 564 reg_wp.enable_f3 <= apbi.pwdata(3);
@@ -551,27 +567,27 BEGIN -- beh
551 567 reg_wp.burst_f2 <= apbi.pwdata(6);
552 568 reg_wp.run <= apbi.pwdata(7);
553 569 --22
554 WHEN "010110" => reg_wp.addr_data_f0 <= apbi.pwdata;
555 WHEN "010111" => reg_wp.addr_data_f1 <= apbi.pwdata;
556 WHEN "011000" => reg_wp.addr_data_f2 <= apbi.pwdata;
557 WHEN "011001" => reg_wp.addr_data_f3 <= apbi.pwdata;
570 WHEN "010111" => reg_wp.addr_data_f0 <= apbi.pwdata;
571 WHEN "011000" => reg_wp.addr_data_f1 <= apbi.pwdata;
572 WHEN "011001" => reg_wp.addr_data_f2 <= apbi.pwdata;
573 WHEN "011010" => reg_wp.addr_data_f3 <= apbi.pwdata;
558 574 --26
559 WHEN "011010" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
575 WHEN "011011" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
560 576 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
561 577 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
562 578 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
563 579 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
564 580 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
565 581 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
566 WHEN "011011" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
567 WHEN "011100" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
568 WHEN "011101" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
569 WHEN "011110" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
570 WHEN "011111" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
571 WHEN "100000" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
572 WHEN "100001" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
573 WHEN "100010" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
574 WHEN "100011" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
582 WHEN "011100" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
583 WHEN "011101" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
584 WHEN "011110" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
585 WHEN "011111" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
586 WHEN "100000" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
587 WHEN "100001" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
588 WHEN "100010" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
589 WHEN "100011" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
590 WHEN "100100" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
575 591 --
576 592 WHEN OTHERS => NULL;
577 593 END CASE;
@@ -584,8 +600,8 BEGIN -- beh
584 600 )
585 601 OR
586 602 (reg_sp.config_active_interruption_onError AND (
587 error_bad_component_error
588 OR error_buffer_full
603 -- error_bad_component_error OR
604 error_buffer_full
589 605 OR error_input_fifo_write(0)
590 606 OR error_input_fifo_write(1)
591 607 OR error_input_fifo_write(2))
@@ -695,7 +711,9 BEGIN -- beh
695 711 reg_sp.status_error_input_fifo_write(2) &--10
696 712 reg_sp.status_error_input_fifo_write(1) &--9
697 713 reg_sp.status_error_input_fifo_write(0) &--8
698 reg_sp.status_error_buffer_full & reg_sp.status_error_bad_component_error & --7 6
714 reg_sp.status_error_buffer_full &
715 '0' &
716 -- reg_sp.status_error_bad_component_error & --7 6
699 717 reg_sp.status_ready_matrix_f2_1 & reg_sp.status_ready_matrix_f2_0 &--5 4
700 718 reg_sp.status_ready_matrix_f1_1 & reg_sp.status_ready_matrix_f1_0 &--3 2
701 719 reg_sp.status_ready_matrix_f0_1 & reg_sp.status_ready_matrix_f0_0; --1 0
Show file before | Show file after | Hide comments
@@ -21,6 +21,7 ENTITY lpp_lfr_ms IS
21 21 PORT (
22 22 clk : IN STD_LOGIC;
23 23 rstn : IN STD_LOGIC;
24 run : IN STD_LOGIC;
24 25
25 26 ---------------------------------------------------------------------------
26 27 -- DATA INPUT
@@ -41,40 +42,39 ENTITY lpp_lfr_ms IS
41 42 ---------------------------------------------------------------------------
42 43 -- DMA
43 44 ---------------------------------------------------------------------------
44 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
45 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
46 dma_valid : OUT STD_LOGIC;
47 dma_valid_burst : OUT STD_LOGIC;
48 dma_ren : IN STD_LOGIC;
49 dma_done : IN STD_LOGIC;
45 dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
46 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
47 dma_fifo_ren : IN STD_LOGIC; --TODO
48 dma_buffer_new : OUT STD_LOGIC; --TODO
49 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
50 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
51 dma_buffer_full : IN STD_LOGIC; --TODO
52 dma_buffer_full_err : IN STD_LOGIC; --TODO
50 53
51 54 -- Reg out
52 ready_matrix_f0 : OUT STD_LOGIC;
53 ready_matrix_f1 : OUT STD_LOGIC;
54 ready_matrix_f2 : OUT STD_LOGIC;
55 error_bad_component_error : OUT STD_LOGIC;
56 error_buffer_full : OUT STD_LOGIC;
55 ready_matrix_f0 : OUT STD_LOGIC; -- TODO
56 ready_matrix_f1 : OUT STD_LOGIC; -- TODO
57 ready_matrix_f2 : OUT STD_LOGIC; -- TODO
58 -- error_bad_component_error : OUT STD_LOGIC; -- TODO
59 error_buffer_full : OUT STD_LOGIC; -- TODO
57 60 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
58 61
59 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 --
61 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
62 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
63
64 62 -- Reg In
65 status_ready_matrix_f0 : IN STD_LOGIC;
66 status_ready_matrix_f1 : IN STD_LOGIC;
67 status_ready_matrix_f2 : IN STD_LOGIC;
63 status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
64 status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
65 status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
68 66
69 config_active_interruption_onNewMatrix : IN STD_LOGIC;
70 config_active_interruption_onError : IN STD_LOGIC;
71 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
67 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
68 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
69 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
70
71 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
72 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
73 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
74 74
75 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
77 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
75 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
76 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
77 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
78 78
79 79 );
80 80 END;
@@ -195,6 +195,7 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
195 195
196 196 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
197 197 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
198 SIGNAL FSM_DMA_fifo_empty_threshold : STD_LOGIC;
198 199 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 200 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
200 201 -----------------------------------------------------------------------------
@@ -204,6 +205,7 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
204 205 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
205 206 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
206 207 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
208 SIGNAL MEM_OUT_SM_Empty_Threshold : STD_LOGIC_VECTOR(1 DOWNTO 0);
207 209
208 210 -----------------------------------------------------------------------------
209 211 -- TIME REG & INFOs
@@ -623,17 +625,6 BEGIN
623 625 fft_data_valid => fft_data_valid,
624 626 fft_ready => fft_ready);
625 627
626 observation_vector_0(11 DOWNTO 0) <= "000" & --11 10
627 fft_ongoing_counter & --9 8
628 sample_load_rising_down & --7
629 fft_ready_rising_down & --6
630 fft_ready & --5
631 fft_data_valid & --4
632 fft_pong & --3
633 sample_load & --2
634 fft_read & --1
635 sample_valid; --0
636
637 628 -----------------------------------------------------------------------------
638 629 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
639 630 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
@@ -764,15 +755,6 BEGIN
764 755 empty => MEM_IN_SM_Empty,
765 756 almost_full => OPEN);
766 757
767 -----------------------------------------------------------------------------
768
769 observation_vector_1(11 DOWNTO 0) <= '0' &
770 SM_correlation_done & --4
771 SM_correlation_auto & --3
772 SM_correlation_start &
773 SM_correlation_start & --7
774 status_MS_input(1 DOWNTO 0)& --6..5
775 MEM_IN_SM_locked(4 DOWNTO 0); --4..0
776 758
777 759 -----------------------------------------------------------------------------
778 760 MS_control_1 : MS_control
@@ -881,29 +863,60 BEGIN
881 863 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
882 864 -----------------------------------------------------------------------------
883 865
884 Mem_Out_SpectralMatrix : lppFIFOxN
885 GENERIC MAP (
886 tech => 0,
887 Mem_use => Mem_use,
888 Data_sz => 32,
889 Addr_sz => 8,
890 FifoCnt => 2)
891 PORT MAP (
892 clk => clk,
893 rstn => rstn,
866 --Mem_Out_SpectralMatrix : lppFIFOxN
867 -- GENERIC MAP (
868 -- tech => 0,
869 -- Mem_use => Mem_use,
870 -- Data_sz => 32,
871 -- Addr_sz => 8,
872 -- FifoCnt => 2)
873 -- PORT MAP (
874 -- clk => clk,
875 -- rstn => rstn,
876
877 -- ReUse => (OTHERS => '0'),
878 -- run => (OTHERS => '1'),
879
880 -- wen => MEM_OUT_SM_Write,
881 -- wdata => MEM_OUT_SM_Data_in,
882
883 -- ren => MEM_OUT_SM_Read,
884 -- rdata => MEM_OUT_SM_Data_out,
885
886 -- full => MEM_OUT_SM_Full,
887 -- empty => MEM_OUT_SM_Empty,
888 -- almost_full => OPEN);
894 889
895 ReUse => (OTHERS => '0'),
896 run => (OTHERS => '1'),
897
898 wen => MEM_OUT_SM_Write,
899 wdata => MEM_OUT_SM_Data_in,
890
891 all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE
892 Mem_Out_SpectralMatrix_I: lpp_fifo
893 GENERIC MAP (
894 tech => 0,
895 Mem_use => Mem_use,
896 EMPTY_THRESHOLD_LIMIT => 15,
897 FULL_THRESHOLD_LIMIT => 1,
898 DataSz => 32,
899 AddrSz => 8)
900 PORT MAP (
901 clk => clk,
902 rstn => rstn,
903 reUse => '0',
904 run => run,
900 905
901 ren => MEM_OUT_SM_Read,
902 rdata => MEM_OUT_SM_Data_out,
903
904 full => MEM_OUT_SM_Full,
905 empty => MEM_OUT_SM_Empty,
906 almost_full => OPEN);
906 ren => MEM_OUT_SM_Read(I),
907 rdata => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i),
908
909 wen => MEM_OUT_SM_Write(I),
910 wdata => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i),
911
912 empty => MEM_OUT_SM_Empty(I),
913 full => MEM_OUT_SM_Full(I),
914 full_almost => OPEN,
915 empty_threshold => MEM_OUT_SM_Empty_Threshold(I),
916
917 full_threshold => OPEN);
918
919 END GENERATE all_Mem_Out_SpectralMatrix;
907 920
908 921 -----------------------------------------------------------------------------
909 922 -- MEM_OUT_SM_Read <= "00";
@@ -949,51 +962,140 BEGIN
949 962 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
950 963 MEM_OUT_SM_Data_out(63 DOWNTO 32);
951 964
965
966 FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
967 MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
968 '0';
969
952 970 -----------------------------------------------------------------------------
953 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
954 PORT MAP (
955 HCLK => clk,
956 HRESETn => rstn,
957
958 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
959 fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
960 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
961 fifo_data => FSM_DMA_fifo_data,
962 fifo_empty => FSM_DMA_fifo_empty,
963 fifo_ren => FSM_DMA_fifo_ren,
971 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --IN
972 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --IN
973 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --IN
974 -- fifo_data => FSM_DMA_fifo_data, --IN
975 -- fifo_empty => FSM_DMA_fifo_empty, --IN
976 -- fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, --IN
977 -- fifo_ren => FSM_DMA_fifo_ren, --OUT
978
964 979
965 dma_addr => dma_addr,
966 dma_data => dma_data,
967 dma_valid => dma_valid,
968 dma_valid_burst => dma_valid_burst,
969 dma_ren => dma_ren,
970 dma_done => dma_done,
971
972 ready_matrix_f0 => ready_matrix_f0,
973 ready_matrix_f1 => ready_matrix_f1,
974 ready_matrix_f2 => ready_matrix_f2,
975
976 error_bad_component_error => error_bad_component_error,
977 error_buffer_full => error_buffer_full,
978
979 debug_reg => debug_reg,
980 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
981 PORT MAP (
982 clk => clk,
983 rstn => rstn,
984 run => run,
985
986 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
987 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
988 fifo_data => FSM_DMA_fifo_data,
989 fifo_empty => FSM_DMA_fifo_empty,
990 fifo_empty_threshold => FSM_DMA_fifo_empty_threshold,
991 fifo_ren => FSM_DMA_fifo_ren,
992
993 dma_fifo_valid_burst => dma_fifo_burst_valid,
994 dma_fifo_data => dma_fifo_data,
995 dma_fifo_ren => dma_fifo_ren,
996 dma_buffer_new => dma_buffer_new,
997 dma_buffer_addr => dma_buffer_addr,
998 dma_buffer_length => dma_buffer_length,
999 dma_buffer_full => dma_buffer_full,
1000 dma_buffer_full_err => dma_buffer_full_err,
1001
980 1002 status_ready_matrix_f0 => status_ready_matrix_f0,
981 1003 status_ready_matrix_f1 => status_ready_matrix_f1,
982 1004 status_ready_matrix_f2 => status_ready_matrix_f2,
1005 addr_matrix_f0 => addr_matrix_f0,
1006 addr_matrix_f1 => addr_matrix_f1,
1007 addr_matrix_f2 => addr_matrix_f2,
1008 length_matrix_f0 => length_matrix_f0,
1009 length_matrix_f1 => length_matrix_f1,
1010 length_matrix_f2 => length_matrix_f2,
1011 ready_matrix_f0 => ready_matrix_f0,
1012 ready_matrix_f1 => ready_matrix_f1,
1013 ready_matrix_f2 => ready_matrix_f2,
1014 matrix_time_f0 => matrix_time_f0,
1015 matrix_time_f1 => matrix_time_f1,
1016 matrix_time_f2 => matrix_time_f2,
1017 error_buffer_full => error_buffer_full);
1018
983 1019
984 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
985 config_active_interruption_onError => config_active_interruption_onError,
1020
1021
1022
1023 --dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
1024 --dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1025 --dma_fifo_ren : IN STD_LOGIC; --TODO
1026 --dma_buffer_new : OUT STD_LOGIC; --TODO
1027 --dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1028 --dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
1029 --dma_buffer_full : IN STD_LOGIC; --TODO
1030 --dma_buffer_full_err : IN STD_LOGIC; --TODO
1031
1032 ---- Reg out
1033 --ready_matrix_f0 : OUT STD_LOGIC; -- TODO
1034 --ready_matrix_f1 : OUT STD_LOGIC; -- TODO
1035 --ready_matrix_f2 : OUT STD_LOGIC; -- TODO
1036 --error_bad_component_error : OUT STD_LOGIC; -- TODO
1037 --error_buffer_full : OUT STD_LOGIC; -- TODO
1038
1039 ---- Reg In
1040 --status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
1041 --status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
1042 --status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
1043
1044 --addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1045 --addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1046 --addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
986 1047
987 addr_matrix_f0 => addr_matrix_f0,
988 addr_matrix_f1 => addr_matrix_f1,
989 addr_matrix_f2 => addr_matrix_f2,
1048 --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1049 --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1050 --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
1051 -----------------------------------------------------------------------------
1052
1053 -----------------------------------------------------------------------------
1054 --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
1055 -- PORT MAP (
1056 -- HCLK => clk,
1057 -- HRESETn => rstn,
1058
1059 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1060 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
1061 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1062 -- fifo_data => FSM_DMA_fifo_data,
1063 -- fifo_empty => FSM_DMA_fifo_empty,
1064 -- fifo_ren => FSM_DMA_fifo_ren,
990 1065
991 matrix_time_f0 => matrix_time_f0,
992 matrix_time_f1 => matrix_time_f1,
993 matrix_time_f2 => matrix_time_f2
994 );
1066 -- dma_addr => dma_addr,
1067 -- dma_data => dma_data,
1068 -- dma_valid => dma_valid,
1069 -- dma_valid_burst => dma_valid_burst,
1070 -- dma_ren => dma_ren,
1071 -- dma_done => dma_done,
1072
1073 -- ready_matrix_f0 => ready_matrix_f0,
1074 -- ready_matrix_f1 => ready_matrix_f1,
1075 -- ready_matrix_f2 => ready_matrix_f2,
1076
1077 -- error_bad_component_error => error_bad_component_error,
1078 -- error_buffer_full => error_buffer_full,
1079
1080 -- debug_reg => debug_reg,
1081 -- status_ready_matrix_f0 => status_ready_matrix_f0,
1082 -- status_ready_matrix_f1 => status_ready_matrix_f1,
1083 -- status_ready_matrix_f2 => status_ready_matrix_f2,
1084
1085 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
1086 -- config_active_interruption_onError => config_active_interruption_onError,
1087
1088 -- addr_matrix_f0 => addr_matrix_f0,
1089 -- addr_matrix_f1 => addr_matrix_f1,
1090 -- addr_matrix_f2 => addr_matrix_f2,
1091
1092 -- matrix_time_f0 => matrix_time_f0,
1093 -- matrix_time_f1 => matrix_time_f1,
1094 -- matrix_time_f2 => matrix_time_f2
1095 -- );
995 1096 -----------------------------------------------------------------------------
996 1097
1098
997 1099
998 1100
999 1101
@@ -1039,4 +1141,4 BEGIN
1039 1141
1040 1142 -----------------------------------------------------------------------------
1041 1143
1042 END Behavioral;
1144 END Behavioral; No newline at end of file
Show file before | Show file after | Hide comments
@@ -41,259 +41,147 USE techmap.gencomp.ALL;
41 41 ENTITY lpp_lfr_ms_fsmdma IS
42 42 PORT (
43 43 -- AMBA AHB system signals
44 HCLK : IN STD_ULOGIC;
45 HRESETn : IN STD_ULOGIC;
44 clk : IN STD_ULOGIC;
45 rstn : IN STD_ULOGIC;
46 run : IN STD_LOGIC;
46 47
47 48 ---------------------------------------------------------------------------
48 49 -- FIFO - IN
49 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
50 fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
51 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
52 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 fifo_empty : IN STD_LOGIC;
54 fifo_ren : OUT STD_LOGIC;
50 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
51 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
52 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 fifo_empty : IN STD_LOGIC;
54 fifo_empty_threshold : IN STD_LOGIC;
55 fifo_ren : OUT STD_LOGIC;
55 56
56 57 ---------------------------------------------------------------------------
57 58 -- DMA - OUT
58 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
59 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 dma_valid : OUT STD_LOGIC;
61 dma_valid_burst : OUT STD_LOGIC;
62 dma_ren : IN STD_LOGIC;
63 dma_done : IN STD_LOGIC;
59 dma_fifo_valid_burst : OUT STD_LOGIC;
60 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
61 dma_fifo_ren : IN STD_LOGIC;
62
63 dma_buffer_new : OUT STD_LOGIC;
64 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
65 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
66 dma_buffer_full : IN STD_LOGIC;
67 dma_buffer_full_err : IN STD_LOGIC;
64 68
65 69 ---------------------------------------------------------------------------
66 -- Reg out
67 ready_matrix_f0 : OUT STD_LOGIC;
68 ready_matrix_f1 : OUT STD_LOGIC;
69 ready_matrix_f2 : OUT STD_LOGIC;
70
71 error_bad_component_error : OUT STD_LOGIC;
72 error_buffer_full : OUT STD_LOGIC;
73 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
70 -- Reg In
71 status_ready_matrix_f0 : IN STD_LOGIC;
72 status_ready_matrix_f1 : IN STD_LOGIC;
73 status_ready_matrix_f2 : IN STD_LOGIC;
74
75 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
76 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
77 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74 78
75 -- Reg In
76 status_ready_matrix_f0 : IN STD_LOGIC;
77 status_ready_matrix_f1 : IN STD_LOGIC;
78 status_ready_matrix_f2 : IN STD_LOGIC;
79 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
80 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
81 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
79 82
80 config_active_interruption_onNewMatrix : IN STD_LOGIC;
81 config_active_interruption_onError : IN STD_LOGIC;
82 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
83 -- Reg Out
84 ready_matrix_f0 : OUT STD_LOGIC;
85 ready_matrix_f1 : OUT STD_LOGIC;
86 ready_matrix_f2 : OUT STD_LOGIC;
85 87
86 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
87 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
88 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
89
88 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
89 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
90 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
91 error_buffer_full : OUT STD_LOGIC
90 92 );
91 93 END;
92 94
93 95 ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
94 -----------------------------------------------------------------------------
95 TYPE state_DMAWriteBurst IS (IDLE,
96 CHECK_COMPONENT_TYPE,
97 WRITE_COARSE_TIME,
98 WRITE_FINE_TIME,
99 TRASH_FIFO,
100 SEND_DATA,
101 WAIT_DATA_ACK
102 );
103 SIGNAL state : state_DMAWriteBurst;
104
105 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
106 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SIGNAL header_check_ok : STD_LOGIC;
109 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 -----------------------------------------------------------------------------
112 -----------------------------------------------------------------------------
113 96
114 SIGNAL component_send : STD_LOGIC;
115 SIGNAL component_send_ok : STD_LOGIC;
116 -----------------------------------------------------------------------------
117 SIGNAL fifo_ren_trash : STD_LOGIC;
118
119 -----------------------------------------------------------------------------
120 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 -----------------------------------------------------------------------------
122 SIGNAL log_empty_fifo : STD_LOGIC;
123 -----------------------------------------------------------------------------
97 TYPE FSM_DMA_STATE IS (IDLE, ONGOING);
98 SIGNAL state : FSM_DMA_STATE;
99 SIGNAL burst_valid_s : STD_LOGIC;
124 100
125 SIGNAL matrix_buffer_ready : STD_LOGIC;
126 BEGIN
127
128 debug_reg <= debug_reg_s;
129
130
131 matrix_buffer_ready <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0 = '0' ELSE
132 '1' WHEN matrix_type = "01" AND status_ready_matrix_f1 = '0' ELSE
133 '1' WHEN matrix_type = "10" AND status_ready_matrix_f2 = '0' ELSE
134 '0';
101 SIGNAL current_matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
135 102
136 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
137 '1' WHEN component_type = "0000" ELSE --AND component_type_pre = "0000" ELSE
138 '1' WHEN component_type = component_type_pre + "0001" ELSE
139 '0';
140
141 address_matrix <= addr_matrix_f0 WHEN matrix_type = "00" ELSE
142 addr_matrix_f1 WHEN matrix_type = "01" ELSE
143 addr_matrix_f2 WHEN matrix_type = "10" ELSE
144 (OTHERS => '0');
103 BEGIN
104 burst_valid_s <= NOT fifo_empty_threshold;
145 105
146 debug_reg_s(31 DOWNTO 15) <= (OTHERS => '0');
147 -----------------------------------------------------------------------------
148 -- DMA control
149 -----------------------------------------------------------------------------
150 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
151 BEGIN
152 IF HRESETn = '0' THEN
153 matrix_type <= (OTHERS => '0');
154 component_type <= (OTHERS => '0');
155 state <= IDLE;
156 ready_matrix_f0 <= '0';
157 ready_matrix_f1 <= '0';
158 ready_matrix_f2 <= '0';
159 error_bad_component_error <= '0';
160 error_buffer_full <= '0'; -- TODO
161 component_type_pre <= "0000";
162 fifo_ren_trash <= '1';
163 component_send <= '0';
164 address <= (OTHERS => '0');
106 error_buffer_full <= dma_buffer_full_err;
165 107
166 debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0');
167 debug_reg_s(5 DOWNTO 3) <= (OTHERS => '0');
168 debug_reg_s(8 DOWNTO 6) <= (OTHERS => '0');
169 debug_reg_s(10 DOWNTO 9) <= (OTHERS => '0');
170 debug_reg_s(14 DOWNTO 11) <= (OTHERS => '0');
171
172 log_empty_fifo <= '0';
173
174 matrix_time_f0 <= (OTHERS => '0');
175 matrix_time_f1 <= (OTHERS => '0');
176 matrix_time_f2 <= (OTHERS => '0');
108 fifo_ren <= dma_fifo_ren WHEN state = ONGOING ELSE '1';
109 dma_fifo_data <= fifo_data;
110 dma_fifo_valid_burst <= burst_valid_s WHEN state = ONGOING ELSE '1';
177 111
178 ELSIF HCLK'EVENT AND HCLK = '1' THEN
179 --
180 debug_reg_s(3) <= status_ready_matrix_f0;
181 debug_reg_s(4) <= status_ready_matrix_f1;
182 debug_reg_s(5) <= status_ready_matrix_f2;
183 debug_reg_s(6) <= '0';
184 debug_reg_s(7) <= '0';
185 debug_reg_s(8) <= '0';
186 debug_reg_s(10 DOWNTO 9) <= matrix_type;
187 debug_reg_s(14 DOWNTO 11) <= component_type;
188
189 --
190
191
192
193 ready_matrix_f0 <= '0';
194 ready_matrix_f1 <= '0';
195 ready_matrix_f2 <= '0';
196 error_bad_component_error <= '0';
197 error_buffer_full <= '0';
198
199 CASE state IS
200 WHEN IDLE =>
201 debug_reg_s(2 DOWNTO 0) <= "000";
202 IF fifo_empty = '0' THEN
203 state <= CHECK_COMPONENT_TYPE;
204 matrix_type <= fifo_matrix_type;
205 component_type <= fifo_matrix_component;
206 component_type_pre <= component_type;
207 END IF;
208
209 log_empty_fifo <= '0';
210
211 WHEN CHECK_COMPONENT_TYPE =>
212 debug_reg_s(2 DOWNTO 0) <= "001";
213
214 IF header_check_ok = '1' AND matrix_buffer_ready = '1'THEN
215 IF component_type = "0000" THEN
216 address <= address_matrix;
217 CASE matrix_type IS
218 WHEN "00" => matrix_time_f0 <= fifo_matrix_time;
219 WHEN "01" => matrix_time_f1 <= fifo_matrix_time;
220 WHEN "10" => matrix_time_f2 <= fifo_matrix_time;
221 WHEN OTHERS => NULL;
222 END CASE;
223 component_send <= '1';
224 END IF;
225 state <= SEND_DATA;
226 --
227 ELSE
228 error_bad_component_error <= NOT header_check_ok;
229 error_buffer_full <= NOT matrix_buffer_ready; -- TODO
230 component_type_pre <= "0000";
231 state <= TRASH_FIFO;
232 END IF;
233
234 WHEN TRASH_FIFO =>
235 debug_reg_s(2 DOWNTO 0) <= "100";
236
237 error_buffer_full <= '0';
238 error_bad_component_error <= '0';
239 IF fifo_empty = '1' THEN
240 state <= IDLE;
241 fifo_ren_trash <= '1';
242 ELSE
243 fifo_ren_trash <= '0';
244 END IF;
245
246 WHEN SEND_DATA =>
247 debug_reg_s(2 DOWNTO 0) <= "010";
248
249 IF fifo_empty = '1' OR log_empty_fifo = '1' THEN
250 state <= IDLE;
251 IF component_type = "1110" THEN
252 CASE matrix_type IS
253 WHEN "00" =>
254 ready_matrix_f0 <= '1';
255 debug_reg_s(6) <= '1';
256 WHEN "01" =>
257 ready_matrix_f1 <= '1';
258 debug_reg_s(7) <= '1';
259 WHEN "10" =>
260 ready_matrix_f2 <= '1';
261 debug_reg_s(8) <= '1';
112 PROCESS (clk, rstn)
113 BEGIN -- PROCESS
114 IF rstn = '0' THEN -- asynchronous reset (active low)
115 state <= IDLE;
116 current_matrix_type <= "00";
117 matrix_time_f0 <= (OTHERS => '0');
118 matrix_time_f1 <= (OTHERS => '0');
119 matrix_time_f2 <= (OTHERS => '0');
120 dma_buffer_addr <= (OTHERS => '0');
121 dma_buffer_length <= (OTHERS => '0');
122 dma_buffer_new <= '0';
123 ready_matrix_f0 <= '0';
124 ready_matrix_f1 <= '0';
125 ready_matrix_f2 <= '0';
126 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
127 ready_matrix_f0 <= '0';
128 ready_matrix_f1 <= '0';
129 ready_matrix_f2 <= '0';
130 IF run = '1' THEN
131 CASE state IS
132 WHEN IDLE =>
133 IF fifo_empty = '0' THEN
134 current_matrix_type <= fifo_matrix_type;
135 CASE fifo_matrix_type IS
136 WHEN "00" =>
137 IF status_ready_matrix_f0 = '0' THEN
138 state <= ONGOING;
139 matrix_time_f0 <= fifo_matrix_time;
140 dma_buffer_addr <= addr_matrix_f0;
141 dma_buffer_length <= length_matrix_f0;
142 dma_buffer_new <= '1';
143 END IF;
144 WHEN "01" =>
145 IF status_ready_matrix_f1 = '0' THEN
146 state <= ONGOING;
147 matrix_time_f1 <= fifo_matrix_time;
148 dma_buffer_addr <= addr_matrix_f1;
149 dma_buffer_length <= length_matrix_f1;
150 dma_buffer_new <= '1';
151 END IF;
152 WHEN "10" =>
153 IF status_ready_matrix_f2 = '0' THEN
154 state <= ONGOING;
155 matrix_time_f2 <= fifo_matrix_time;
156 dma_buffer_addr <= addr_matrix_f2;
157 dma_buffer_length <= length_matrix_f2;
158 dma_buffer_new <= '1';
159 END IF;
262 160 WHEN OTHERS => NULL;
263 161 END CASE;
264 162 END IF;
265 ELSE
266 component_send <= '1';
267 address <= address;
268 state <= WAIT_DATA_ACK;
269 END IF;
270
271 WHEN WAIT_DATA_ACK =>
272 log_empty_fifo <= fifo_empty OR log_empty_fifo;
273
274 debug_reg_s(2 DOWNTO 0) <= "011";
275
276 IF dma_ren = '0' THEN
277 component_send <= '0';
278 END IF;
279
280 IF component_send_ok = '1' THEN
281 address <= address + 64;
282 state <= SEND_DATA;
283 END IF;
284
285 WHEN OTHERS => NULL;
286 END CASE;
287
163 WHEN ONGOING =>
164 IF dma_buffer_full = '1' THEN
165 CASE current_matrix_type IS
166 WHEN "00" => ready_matrix_f0 <= '1'; state <= IDLE;
167 WHEN "01" => ready_matrix_f1 <= '1'; state <= IDLE;
168 WHEN "10" => ready_matrix_f2 <= '1'; state <= IDLE;
169 WHEN OTHERS => NULL;
170 END CASE;
171 END IF;
172 WHEN OTHERS => NULL;
173 END CASE;
174 ELSE
175 state <= IDLE;
176 current_matrix_type <= "00";
177 matrix_time_f0 <= (OTHERS => '0');
178 matrix_time_f1 <= (OTHERS => '0');
179 matrix_time_f2 <= (OTHERS => '0');
180 dma_buffer_addr <= (OTHERS => '0');
181 dma_buffer_length <= (OTHERS => '0');
182 dma_buffer_new <= '0';
183 END IF;
288 184 END IF;
289 END PROCESS DMAWriteFSM_p;
290
291 dma_valid_burst <= component_send;
292 dma_valid <= '0';
293 dma_data <= fifo_data;
294 dma_addr <= address;
295 fifo_ren <= dma_ren AND fifo_ren_trash;
296
297 component_send_ok <= dma_done;
185 END PROCESS;
298 186
299 187 END Behavioral;
Show file before | Show file after | Hide comments
@@ -69,114 +69,83 PACKAGE lpp_lfr_pkg IS
69 69 -----------------------------------------------------------------------------
70 70 COMPONENT lpp_lfr_ms
71 71 GENERIC (
72 Mem_use : INTEGER
73 );
72 Mem_use : INTEGER);
74 73 PORT (
75 clk : IN STD_LOGIC;
76 rstn : IN STD_LOGIC;
77
78 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
79 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
80
81 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
82 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
83
84 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
85 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
86
87 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
88 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
89
90 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 dma_valid : OUT STD_LOGIC;
93 dma_valid_burst : OUT STD_LOGIC;
94 dma_ren : IN STD_LOGIC;
95 dma_done : IN STD_LOGIC;
96
97 ready_matrix_f0 : OUT STD_LOGIC;
98 -- ready_matrix_f0_1 : OUT STD_LOGIC;
99 ready_matrix_f1 : OUT STD_LOGIC;
100 ready_matrix_f2 : OUT STD_LOGIC;
101 -- error_anticipating_empty_fifo : OUT STD_LOGIC;
102 error_bad_component_error : OUT STD_LOGIC;
103 error_buffer_full : OUT STD_LOGIC;
104 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
105 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
106 --
107 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
108 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
109 -------------------------------------------------------------------------
110 status_ready_matrix_f0 : IN STD_LOGIC;
111 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
112 status_ready_matrix_f1 : IN STD_LOGIC;
113 status_ready_matrix_f2 : IN STD_LOGIC;
114 -- status_error_anticipating_empty_fifo : IN STD_LOGIC;
115 -- status_error_bad_component_error : IN STD_LOGIC;
116 config_active_interruption_onNewMatrix : IN STD_LOGIC;
117 config_active_interruption_onError : IN STD_LOGIC;
118 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
119 -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
120 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
121 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
122
123 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
124 -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
125 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
126 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
74 clk : IN STD_LOGIC;
75 rstn : IN STD_LOGIC;
76 run : IN STD_LOGIC;
77 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
79 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
80 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
81 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
82 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
83 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
84 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
85 dma_fifo_burst_valid : OUT STD_LOGIC;
86 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 dma_fifo_ren : IN STD_LOGIC;
88 dma_buffer_new : OUT STD_LOGIC;
89 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
91 dma_buffer_full : IN STD_LOGIC;
92 dma_buffer_full_err : IN STD_LOGIC;
93 ready_matrix_f0 : OUT STD_LOGIC;
94 ready_matrix_f1 : OUT STD_LOGIC;
95 ready_matrix_f2 : OUT STD_LOGIC;
96 error_buffer_full : OUT STD_LOGIC;
97 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
98 status_ready_matrix_f0 : IN STD_LOGIC;
99 status_ready_matrix_f1 : IN STD_LOGIC;
100 status_ready_matrix_f2 : IN STD_LOGIC;
101 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
105 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
106 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
107 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
108 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
109 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
127 110 END COMPONENT;
128 111
129 112 COMPONENT lpp_lfr_ms_fsmdma
130 113 PORT (
131 HCLK : IN STD_ULOGIC;
132 HRESETn : IN STD_ULOGIC;
133 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
134 fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
135 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
136 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 fifo_empty : IN STD_LOGIC;
138 fifo_ren : OUT STD_LOGIC;
139 --data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
140 --fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
141 --fifo_empty : IN STD_LOGIC;
142 --fifo_ren : OUT STD_LOGIC;
143 --header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
144 --header_val : IN STD_LOGIC;
145 --header_ack : OUT STD_LOGIC;
146 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
147 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
148 dma_valid : OUT STD_LOGIC;
149 dma_valid_burst : OUT STD_LOGIC;
150 dma_ren : IN STD_LOGIC;
151 dma_done : IN STD_LOGIC;
152 ready_matrix_f0 : OUT STD_LOGIC;
153 -- ready_matrix_f0_1 : OUT STD_LOGIC;
154 ready_matrix_f1 : OUT STD_LOGIC;
155 ready_matrix_f2 : OUT STD_LOGIC;
156 -- error_anticipating_empty_fifo : OUT STD_LOGIC;
157 error_bad_component_error : OUT STD_LOGIC;
158 error_buffer_full : OUT STD_LOGIC;
159 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
160 status_ready_matrix_f0 : IN STD_LOGIC;
161 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
162 status_ready_matrix_f1 : IN STD_LOGIC;
163 status_ready_matrix_f2 : IN STD_LOGIC;
164 -- status_error_anticipating_empty_fifo : IN STD_LOGIC;
165 -- status_error_bad_component_error : IN STD_LOGIC;
166 config_active_interruption_onNewMatrix : IN STD_LOGIC;
167 config_active_interruption_onError : IN STD_LOGIC;
168 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
169 -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
170 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
171 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
172
173 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
174 -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
175 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
176 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
177 );
114 clk : IN STD_ULOGIC;
115 rstn : IN STD_ULOGIC;
116 run : IN STD_LOGIC;
117 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
118 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
119 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
120 fifo_empty : IN STD_LOGIC;
121 fifo_empty_threshold : IN STD_LOGIC;
122 fifo_ren : OUT STD_LOGIC;
123 dma_fifo_valid_burst : OUT STD_LOGIC;
124 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
125 dma_fifo_ren : IN STD_LOGIC;
126 dma_buffer_new : OUT STD_LOGIC;
127 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
129 dma_buffer_full : IN STD_LOGIC;
130 dma_buffer_full_err : IN STD_LOGIC;
131 status_ready_matrix_f0 : IN STD_LOGIC;
132 status_ready_matrix_f1 : IN STD_LOGIC;
133 status_ready_matrix_f2 : IN STD_LOGIC;
134 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
135 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
136 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
138 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
139 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
140 ready_matrix_f0 : OUT STD_LOGIC;
141 ready_matrix_f1 : OUT STD_LOGIC;
142 ready_matrix_f2 : OUT STD_LOGIC;
143 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
144 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
145 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
146 error_buffer_full : OUT STD_LOGIC);
178 147 END COMPONENT;
179
148
180 149 COMPONENT lpp_lfr_ms_FFT
181 150 PORT (
182 151 clk : IN STD_LOGIC;
@@ -285,6 +254,7 PACKAGE lpp_lfr_pkg IS
285 254 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
286 255 END COMPONENT;
287 256 -----------------------------------------------------------------------------
257
288 258 COMPONENT lpp_lfr_apbreg
289 259 GENERIC (
290 260 nb_data_by_buffer_size : INTEGER;
@@ -299,70 +269,62 PACKAGE lpp_lfr_pkg IS
299 269 pirq_wfp : INTEGER;
300 270 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
301 271 PORT (
302 HCLK : IN STD_ULOGIC;
303 HRESETn : IN STD_ULOGIC;
304 apbi : IN apb_slv_in_type;
305 apbo : OUT apb_slv_out_type;
306 run_ms : OUT STD_LOGIC;
307 ready_matrix_f0 : IN STD_LOGIC;
308 ready_matrix_f1 : IN STD_LOGIC;
309 ready_matrix_f2 : IN STD_LOGIC;
310 error_bad_component_error : IN STD_LOGIC;
311 error_buffer_full : in STD_LOGIC;
312 error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0);
313 --x debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
314 status_ready_matrix_f0 : OUT STD_LOGIC;
315 status_ready_matrix_f1 : OUT STD_LOGIC;
316 status_ready_matrix_f2 : OUT STD_LOGIC;
317 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
318 config_active_interruption_onError : OUT STD_LOGIC;
319 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
320 -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
321 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
322 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
323 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
324 -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
325 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
326 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
327 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
328 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
329 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
330 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
331 data_shaping_BW : OUT STD_LOGIC;
332 data_shaping_SP0 : OUT STD_LOGIC;
333 data_shaping_SP1 : OUT STD_LOGIC;
334 data_shaping_R0 : OUT STD_LOGIC;
335 data_shaping_R1 : OUT STD_LOGIC;
336 data_shaping_R2 : OUT STD_LOGIC;
337 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
338 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
339 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
340 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
341 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
342 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
343 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
344 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
345 enable_f0 : OUT STD_LOGIC;
346 enable_f1 : OUT STD_LOGIC;
347 enable_f2 : OUT STD_LOGIC;
348 enable_f3 : OUT STD_LOGIC;
349 burst_f0 : OUT STD_LOGIC;
350 burst_f1 : OUT STD_LOGIC;
351 burst_f2 : OUT STD_LOGIC;
352 run : OUT STD_LOGIC;
353 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
354 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
355 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
356 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
357 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
358
359 debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
360
361 );
272 HCLK : IN STD_ULOGIC;
273 HRESETn : IN STD_ULOGIC;
274 apbi : IN apb_slv_in_type;
275 apbo : OUT apb_slv_out_type;
276 run_ms : OUT STD_LOGIC;
277 ready_matrix_f0 : IN STD_LOGIC;
278 ready_matrix_f1 : IN STD_LOGIC;
279 ready_matrix_f2 : IN STD_LOGIC;
280 error_buffer_full : IN STD_LOGIC;
281 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
282 status_ready_matrix_f0 : OUT STD_LOGIC;
283 status_ready_matrix_f1 : OUT STD_LOGIC;
284 status_ready_matrix_f2 : OUT STD_LOGIC;
285 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
286 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
287 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
288 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
289 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
290 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
291 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
292 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
293 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
294 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
295 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
296 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
297 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
298 data_shaping_BW : OUT STD_LOGIC;
299 data_shaping_SP0 : OUT STD_LOGIC;
300 data_shaping_SP1 : OUT STD_LOGIC;
301 data_shaping_R0 : OUT STD_LOGIC;
302 data_shaping_R1 : OUT STD_LOGIC;
303 data_shaping_R2 : OUT STD_LOGIC;
304 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
305 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
306 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
307 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
308 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
309 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
310 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
311 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
312 enable_f0 : OUT STD_LOGIC;
313 enable_f1 : OUT STD_LOGIC;
314 enable_f2 : OUT STD_LOGIC;
315 enable_f3 : OUT STD_LOGIC;
316 burst_f0 : OUT STD_LOGIC;
317 burst_f1 : OUT STD_LOGIC;
318 burst_f2 : OUT STD_LOGIC;
319 run : OUT STD_LOGIC;
320 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
321 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
322 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
323 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
324 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
325 debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
362 326 END COMPONENT;
363 327
364
365
366 328 COMPONENT lpp_top_ms
367 329 GENERIC (
368 330 Mem_use : INTEGER;
Show file before | Show file after | Hide comments
@@ -103,58 +103,18 ENTITY lpp_waveform IS
103 103 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 104 data_f3_in_valid : IN STD_LOGIC;
105 105 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
106
106
107 107 ---------------------------------------------------------------------------
108 -- OUTPUT
109 --f0
110 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
111 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
112 data_f0_data_out_valid : OUT STD_LOGIC;
113 data_f0_data_out_valid_burst : OUT STD_LOGIC;
114 data_f0_data_out_ren : IN STD_LOGIC;
115 --f1
116 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
117 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118 data_f1_data_out_valid : OUT STD_LOGIC;
119 data_f1_data_out_valid_burst : OUT STD_LOGIC;
120 data_f1_data_out_ren : IN STD_LOGIC;
121 --f2
122 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
123 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
124 data_f2_data_out_valid : OUT STD_LOGIC;
125 data_f2_data_out_valid_burst : OUT STD_LOGIC;
126 data_f2_data_out_ren : IN STD_LOGIC;
127 --f3
128 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 data_f3_data_out_valid : OUT STD_LOGIC;
131 data_f3_data_out_valid_burst : OUT STD_LOGIC;
132 data_f3_data_out_ren : IN STD_LOGIC;
133
134 ---------------------------------------------------------------------------
135 --
136 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
108 -- DMA --------------------------------------------------------------------
137 109
138
139 ----debug SNAPSHOT OUT
140 --debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 --debug_f0_data_valid : OUT STD_LOGIC;
142 --debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
143 --debug_f1_data_valid : OUT STD_LOGIC;
144 --debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
145 --debug_f2_data_valid : OUT STD_LOGIC;
146 --debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
147 --debug_f3_data_valid : OUT STD_LOGIC;
148
149 ----debug FIFO IN
150 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
151 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
152 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
153 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
154 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
155 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
156 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
157 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC
110 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
111 dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
112 dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
113 dma_buffer_new : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
114 dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
115 dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
116 dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
117 dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
158 118
159 119 );
160 120
@@ -219,30 +179,11 ARCHITECTURE beh OF lpp_waveform IS
219 179
220 180 --
221 181
222 SIGNAL observation_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
223 182 SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
224 183
225 184
226 185 BEGIN -- beh
227 186
228
229 -----------------------------------------------------------------------------
230 -- DEBUG
231 -----------------------------------------------------------------------------
232 PROCESS (clk, rstn)
233 BEGIN -- PROCESS
234 IF rstn = '0' THEN -- asynchronous reset (active low)
235 observation_reg <= (OTHERS => '0');
236 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
237 observation_reg <= observation_reg_s;
238 END IF;
239 END PROCESS;
240 observation_reg_s( 2 DOWNTO 0) <= start_snapshot_f2 & start_snapshot_f1 & start_snapshot_f0;
241 observation_reg_s( 5 DOWNTO 3) <= data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
242 observation_reg_s( 8 DOWNTO 6) <= status_full_s(2 DOWNTO 0) ;
243 observation_reg_s(11 DOWNTO 9) <= status_full_ack(2 DOWNTO 0);
244 observation_reg_s(14 DOWNTO 12) <= data_wen(2 DOWNTO 0);
245 observation_reg_s(31 DOWNTO 15) <= (OTHERS => '0');
246 187 -----------------------------------------------------------------------------
247 188
248 189 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
@@ -506,8 +447,8 BEGIN -- beh
506 447 GENERIC MAP (
507 448 tech => tech,
508 449 Mem_use => use_RAM,
509 EMPTY_THRESHOLD_LIMIT => 16,
510 FULL_THRESHOLD_LIMIT => 5,
450 EMPTY_THRESHOLD_LIMIT => 15,
451 FULL_THRESHOLD_LIMIT => 3,
511 452 DataSz => 32,
512 453 AddrSz => 7)
513 454 PORT MAP (
@@ -528,70 +469,108 BEGIN -- beh
528 469 END GENERATE generate_all_fifo;
529 470
530 471
531 --empty <= s_empty;
532 --empty_almost <= s_empty_almost;
533 --s_data_ren <= data_ren;
472 ----empty <= s_empty;
473 ----empty_almost <= s_empty_almost;
474 ----s_data_ren <= data_ren;
534 475
535 data_f0_data_out <= s_rdata_v(31 downto 0);
536 data_f1_data_out <= s_rdata_v(31+32 downto 0+32);
537 data_f2_data_out <= s_rdata_v(31+32*2 downto 32*2);
538 data_f3_data_out <= s_rdata_v(31+32*3 downto 32*3);
476 --data_f0_data_out <= s_rdata_v(31 downto 0);
477 --data_f1_data_out <= s_rdata_v(31+32 downto 0+32);
478 --data_f2_data_out <= s_rdata_v(31+32*2 downto 32*2);
479 --data_f3_data_out <= s_rdata_v(31+32*3 downto 32*3);
480
481 --data_ren <= data_f3_data_out_ren &
482 -- data_f2_data_out_ren &
483 -- data_f1_data_out_ren &
484 -- data_f0_data_out_ren;
485
486 --lpp_waveform_gen_address_1 : lpp_waveform_genaddress
487 -- GENERIC MAP (
488 -- nb_data_by_buffer_size => nb_word_by_buffer_size)
489 -- PORT MAP (
490 -- clk => clk,
491 -- rstn => rstn,
492 -- run => run,
539 493
540 data_ren <= data_f3_data_out_ren &
541 data_f2_data_out_ren &
542 data_f1_data_out_ren &
543 data_f0_data_out_ren;
544
545 lpp_waveform_gen_address_1 : lpp_waveform_genaddress
546 GENERIC MAP (
547 nb_data_by_buffer_size => nb_word_by_buffer_size)
548 PORT MAP (
549 clk => clk,
550 rstn => rstn,
551 run => run,
494 -- -------------------------------------------------------------------------
495 -- -- CONFIG
496 -- -------------------------------------------------------------------------
497 -- nb_data_by_buffer => nb_word_by_buffer,
552 498
553 -------------------------------------------------------------------------
554 -- CONFIG
555 -------------------------------------------------------------------------
556 nb_data_by_buffer => nb_word_by_buffer,
499 -- addr_data_f0 => addr_data_f0,
500 -- addr_data_f1 => addr_data_f1,
501 -- addr_data_f2 => addr_data_f2,
502 -- addr_data_f3 => addr_data_f3,
503 -- -------------------------------------------------------------------------
504 -- -- CTRL
505 -- -------------------------------------------------------------------------
506 -- -- IN
507 -- empty => empty,
508 -- empty_almost => empty_almost,
509 -- data_ren => data_ren,
510
511 -- -------------------------------------------------------------------------
512 -- -- STATUS
513 -- -------------------------------------------------------------------------
514 -- status_full => status_full_s,
515 -- status_full_ack => status_full_ack,
516 -- status_full_err => status_full_err,
557 517
558 addr_data_f0 => addr_data_f0,
559 addr_data_f1 => addr_data_f1,
560 addr_data_f2 => addr_data_f2,
561 addr_data_f3 => addr_data_f3,
562 -------------------------------------------------------------------------
563 -- CTRL
564 -------------------------------------------------------------------------
565 -- IN
566 empty => empty,
567 empty_almost => empty_almost,
568 data_ren => data_ren,
518 -- -------------------------------------------------------------------------
519 -- -- ADDR DATA OUT
520 -- -------------------------------------------------------------------------
521 -- data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
522 -- data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
523 -- data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
524 -- data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
569 525
570 -------------------------------------------------------------------------
571 -- STATUS
572 -------------------------------------------------------------------------
573 status_full => status_full_s,
574 status_full_ack => status_full_ack,
575 status_full_err => status_full_err,
526 -- data_f0_data_out_valid => data_f0_data_out_valid,
527 -- data_f1_data_out_valid => data_f1_data_out_valid,
528 -- data_f2_data_out_valid => data_f2_data_out_valid,
529 -- data_f3_data_out_valid => data_f3_data_out_valid,
530
531 -- data_f0_addr_out => data_f0_addr_out,
532 -- data_f1_addr_out => data_f1_addr_out,
533 -- data_f2_addr_out => data_f2_addr_out,
534 -- data_f3_addr_out => data_f3_addr_out
535 -- );
536 --status_full <= status_full_s;
537
576 538
577 -------------------------------------------------------------------------
578 -- ADDR DATA OUT
579 -------------------------------------------------------------------------
580 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
581 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
582 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
583 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
539 -----------------------------------------------------------------------------
540 --
541 -----------------------------------------------------------------------------
542
543 all_channel: FOR I IN 3 DOWNTO 0 GENERATE
544 lpp_waveform_fsmdma_I: lpp_waveform_fsmdma
545 PORT MAP (
546 clk => clk,
547 rstn => rstn,
548 run => run,
549
550 fifo_buffer_time => fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO
551
552 fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I),
553 fifo_empty => empty(I),
554 fifo_empty_threshold => empty_almost(I),
555 fifo_ren => data_ren(I),
556
557 dma_fifo_valid_burst => dma_fifo_valid_burst(I),
558 dma_fifo_data => dma_fifo_data(32*(I+1)-1 DOWNTO 32*I),
559 dma_fifo_ren => dma_fifo_ren(I),
560 dma_buffer_new => dma_buffer_new(I),
561 dma_buffer_addr => dma_buffer_addr(32*(I+1)-1 DOWNTO 32*I),
562 dma_buffer_length => dma_buffer_length(26*(I+1)-1 DOWNTO 26*I),
563 dma_buffer_full => dma_buffer_full(I),
564 dma_buffer_full_err => dma_buffer_full_err(I),
565
566 status_buffer_ready => status_buffer_ready(I), -- TODO
567 addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO
568 length_buffer => length_buffer(26*(I+1)-1 DOWNTO 26*I), -- TODO
569 ready_buffer => ready_buffer(I), -- TODO
570 buffer_time => buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO
571 error_buffer_full => error_buffer_full(I)); -- TODO
572
573 END GENERATE all_channel;
584 574
585 data_f0_data_out_valid => data_f0_data_out_valid,
586 data_f1_data_out_valid => data_f1_data_out_valid,
587 data_f2_data_out_valid => data_f2_data_out_valid,
588 data_f3_data_out_valid => data_f3_data_out_valid,
589
590 data_f0_addr_out => data_f0_addr_out,
591 data_f1_addr_out => data_f1_addr_out,
592 data_f2_addr_out => data_f2_addr_out,
593 data_f3_addr_out => data_f3_addr_out
594 );
595 status_full <= status_full_s;
596 575
597 576 END beh;
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@@ -372,5 +372,31 PACKAGE lpp_waveform_pkg IS
372 372 data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
373 373 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0));
374 374 END COMPONENT;
375
376 COMPONENT lpp_waveform_fsmdma
377 PORT (
378 clk : IN STD_ULOGIC;
379 rstn : IN STD_ULOGIC;
380 run : IN STD_LOGIC;
381 fifo_buffer_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
382 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
383 fifo_empty : IN STD_LOGIC;
384 fifo_empty_threshold : IN STD_LOGIC;
385 fifo_ren : OUT STD_LOGIC;
386 dma_fifo_valid_burst : OUT STD_LOGIC;
387 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
388 dma_fifo_ren : IN STD_LOGIC;
389 dma_buffer_new : OUT STD_LOGIC;
390 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
391 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
392 dma_buffer_full : IN STD_LOGIC;
393 dma_buffer_full_err : IN STD_LOGIC;
394 status_buffer_ready : IN STD_LOGIC;
395 addr_buffer : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
396 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
397 ready_buffer : OUT STD_LOGIC;
398 buffer_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
399 error_buffer_full : OUT STD_LOGIC);
400 END COMPONENT;
375 401
376 402 END lpp_waveform_pkg;
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