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Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

TOP with Leon3 SoC only (no LPP module)
pellion -
r260:083bc4300827 JC
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@@ -1,18 +1,19
1 TECHNOLOGY=PROASIC3
2 PACKAGE=\"\"
1 PACKAGE=\"\"
3 SPEED=Std
2 SPEED=Std
4 SYNFREQ=50
3 SYNFREQ=50
5
4
6 PART=A3PE3000L
5 TECHNOLOGY=ProASIC3E
6 LIBERO_DIE=IT14X14M4
7 PART=A3PE3000
8
9 DESIGNER_VOLTAGE=COM
10 DESIGNER_TEMP=COM
7 DESIGNER_PACKAGE=FBGA
11 DESIGNER_PACKAGE=FBGA
8 DESIGNER_PINS=324
12 DESIGNER_PINS=324
9 DESIGNER_VOLTAGE=COM
10 DESIGNER_TEMP=COM
11
13
12 MANUFACTURER=Actel
14 MANUFACTURER=Actel
15 MGCTECHNOLOGY=Proasic3
13 MGCPART=$(PART)
16 MGCPART=$(PART)
14 MGCTECHNOLOGY=PROASIC3
15 MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
17 MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
16 LIBERO_DIE=IT14X14M4LDP
17 LIBERO_PACKAGE=fg$(DESIGNER_PINS)
18 LIBERO_PACKAGE=fg$(DESIGNER_PINS)
18
19
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@@ -124,7 +124,6 ARCHITECTURE beh OF MINI_LFR_top IS
124 pclow : INTEGER);
124 pclow : INTEGER);
125 PORT (
125 PORT (
126 clk100MHz : IN STD_ULOGIC;
126 clk100MHz : IN STD_ULOGIC;
127 clk49_152MHz : IN STD_ULOGIC;
128 reset : IN STD_ULOGIC;
127 reset : IN STD_ULOGIC;
129 errorn : OUT STD_ULOGIC;
128 errorn : OUT STD_ULOGIC;
130 ahbrxd : IN STD_ULOGIC;
129 ahbrxd : IN STD_ULOGIC;
@@ -148,14 +147,34 ARCHITECTURE beh OF MINI_LFR_top IS
148 spw2_sin : IN STD_LOGIC;
147 spw2_sin : IN STD_LOGIC;
149 spw2_dout : OUT STD_LOGIC;
148 spw2_dout : OUT STD_LOGIC;
150 spw2_sout : OUT STD_LOGIC;
149 spw2_sout : OUT STD_LOGIC;
151 apbi_wfp : OUT apb_slv_in_type;
150 apbi_ext : OUT apb_slv_in_type;
152 apbo_wfp : IN apb_slv_out_type;
151 apbo_wfp : IN apb_slv_out_type;
153 ahbi_wfp : OUT AHB_Mst_In_Type;
152 apbo_ltm : IN apb_slv_out_type;
154 ahbo_wfp : IN AHB_Mst_Out_Type;
153 ahbi_ext : OUT AHB_Mst_In_Type;
155 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
154 ahbo_wfp : IN AHB_Mst_Out_Type);
156 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
157 END COMPONENT;
155 END COMPONENT;
158
156
157 -----------------------------------------------------------------------------
158 SIGNAL apbi : apb_slv_in_type;
159 SIGNAL apbo_wfp : apb_slv_out_type;
160 SIGNAL apbo_ltm : apb_slv_out_type;
161 SIGNAL ahbi : AHB_Mst_In_Type;
162 SIGNAL ahbo_wfp : AHB_Mst_Out_Type;
163 --
164 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
165 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
166 --
167 SIGNAL errorn : STD_LOGIC;
168 -- UART AHB ---------------------------------------------------------------
169 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
170 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
171
172 -- UART APB ---------------------------------------------------------------
173 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
174 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
175 --
176 SIGNAL I00_s : STD_LOGIC;
177
159 BEGIN -- beh
178 BEGIN -- beh
160
179
161 PROCESS (clk_50, reset)
180 PROCESS (clk_50, reset)
@@ -164,29 +183,23 BEGIN -- beh
164 LED0 <= '0';
183 LED0 <= '0';
165 LED1 <= '0';
184 LED1 <= '0';
166 LED2 <= '0';
185 LED2 <= '0';
186 IO1 <= '0';
187 IO2 <= '1';
188 IO3 <= '0';
189 IO4 <= '0';
190 IO5 <= '0';
191 IO6 <= '0';
192 IO7 <= '0';
193 IO8 <= '0';
194 IO9 <= '0';
195 IO10 <= '0';
196 IO11 <= '0';
167 ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge
197 ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge
168 LED0 <= '0';
198 LED0 <= '0';
169 LED1 <= '1';
199 LED1 <= '1';
170 LED2 <= BP0;
200 LED2 <= BP0;
171 END IF;
201 IO1 <= '1';
172 END PROCESS;
202 IO2 <= '0';
173
174 --UARTs
175 RXD1 <= '0';
176 nCTS1 <= '0';
177 RXD2 <= '0';
178 nCTS2 <= '0';
179 nDCD2 <= '0';
180
181 --EXT CONNECTOR
182 IO0 <= clk_49;
183 IO1 <= clk_50;
184
185 IO2 <= SPW_NOM_DIN OR
186 SPW_NOM_SIN OR
187 SPW_RED_DIN OR
188 SPW_RED_SIN;
189
190 IO3 <= ADC_SDO(0);
203 IO3 <= ADC_SDO(0);
191 IO4 <= ADC_SDO(1);
204 IO4 <= ADC_SDO(1);
192 IO5 <= ADC_SDO(2);
205 IO5 <= ADC_SDO(2);
@@ -195,67 +208,79 BEGIN -- beh
195 IO8 <= ADC_SDO(5);
208 IO8 <= ADC_SDO(5);
196 IO9 <= ADC_SDO(6);
209 IO9 <= ADC_SDO(6);
197 IO10 <= ADC_SDO(7);
210 IO10 <= ADC_SDO(7);
198 IO11 <= BP1 OR TXD1 OR TXD2 OR nDTR2 OR nRTS2 OR nRTS1;
211 IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
212 END IF;
213 END PROCESS;
214
215 PROCESS (clk_49, reset)
216 BEGIN -- PROCESS
217 IF reset = '0' THEN -- asynchronous reset (active low)
218 I00_s <= '0';
219 ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
220 I00_s <= NOT I00_s;
221 END IF;
222 END PROCESS;
223 IO0 <= I00_s;
224
225 --UARTs
226 nCTS1 <= '0';
227 nCTS2 <= '0';
228 nDCD2 <= '0';
229
230 --EXT CONNECTOR
199
231
200 --SPACE WIRE
232 --SPACE WIRE
201 SPW_EN <= '0'; -- 0 => off
233 SPW_EN <= '0'; -- 0 => off
202 SPW_NOM_DOUT <= '0';
234
203 SPW_NOM_SOUT <= '0';
204 SPW_RED_DOUT <= '0';
205 SPW_RED_SOUT <= '0';
206 ADC_nCS <= '0';
235 ADC_nCS <= '0';
207 ADC_CLK <= '0';
236 ADC_CLK <= '0';
208
237
209 -- SRAM
210 SRAM_nWE <= '1';
211 SRAM_CE <= '0';
212 SRAM_nOE <= '1';
213 SRAM_nBE <= (OTHERS => '1');
214 SRAM_A <= (OTHERS => '0');
215 SRAM_DQ <= (OTHERS => '0');
216
217
218 leon3mp_1: leon3_soc
238 leon3mp_1: leon3_soc
219 GENERIC MAP (
239 GENERIC MAP (
220 fabtech => fabtech,
240 fabtech => CFG_FABTECH,
221 memtech => memtech,
241 memtech => CFG_MEMTECH,
222 padtech => padtech,
242 padtech => CFG_PADTECH,
223 clktech => clktech,
243 clktech => CFG_CLKTECH,
224 disas => disas,
244 disas => CFG_DISAS,
225 dbguart => dbguart,
245 dbguart => CFG_DUART,
226 pclow => pclow)
246 pclow => CFG_PCLOW)
227 PORT MAP (
247 PORT MAP (
228 clk100MHz => clk100MHz,
248 clk100MHz => clk_50, --
229 clk49_152MHz => clk49_152MHz,
249 reset => reset, --
230 reset => reset,
250 errorn => errorn, --
231 errorn => errorn,
232 ahbrxd => ahbrxd,
233 ahbtxd => ahbtxd,
234 urxd1 => urxd1,
235 utxd1 => utxd1,
236 address => address,
237 data => data,
238 nSRAM_BE0 => nSRAM_BE0,
239 nSRAM_BE1 => nSRAM_BE1,
240 nSRAM_BE2 => nSRAM_BE2,
241 nSRAM_BE3 => nSRAM_BE3,
242 nSRAM_WE => nSRAM_WE,
243 nSRAM_CE => nSRAM_CE,
244 nSRAM_OE => nSRAM_OE,
245 spw1_din => spw1_din,
246 spw1_sin => spw1_sin,
247 spw1_dout => spw1_dout,
248 spw1_sout => spw1_sout,
249 spw2_din => spw2_din,
250 spw2_sin => spw2_sin,
251 spw2_dout => spw2_dout,
252 spw2_sout => spw2_sout,
253 apbi_wfp => apbi_wfp,
254 apbo_wfp => apbo_wfp,
255 ahbi_wfp => ahbi_wfp,
256 ahbo_wfp => ahbo_wfp,
257 coarse_time => coarse_time,
258 fine_time => fine_time);
259
251
252 ahbrxd => TXD1, --
253 ahbtxd => RXD1, --
254 urxd1 => TXD2, --
255 utxd1 => RXD2, --
256 --RAM
257 address => SRAM_A, --
258 data => SRAM_DQ, --
259 nSRAM_BE0 => SRAM_nBE(0), --
260 nSRAM_BE1 => SRAM_nBE(1), --
261 nSRAM_BE2 => SRAM_nBE(2), --
262 nSRAM_BE3 => SRAM_nBE(3), --
263 nSRAM_WE => SRAM_nWE, --
264 nSRAM_CE => SRAM_CE, --
265 nSRAM_OE => SRAM_nOE, --
266 --SPW
267 spw1_din => SPW_NOM_DIN, --
268 spw1_sin => SPW_NOM_SIN, --
269 spw1_dout => SPW_NOM_DOUT, --
270 spw1_sout => SPW_NOM_SOUT, --
271 spw2_din => SPW_RED_DIN, --
272 spw2_sin => SPW_RED_SIN, --
273 spw2_dout => SPW_RED_DOUT, --
274 spw2_sout => SPW_RED_SOUT, --
260
275
261 END beh;
276 apbi_ext => apbi, --
277 apbo_wfp => apbo_wfp, --
278 apbo_ltm => apbo_ltm, -- lfr time management
279 ahbi_ext => ahbi, --
280 ahbo_wfp => ahbo_wfp); --
281
282 apbo_wfp <= apb_none;
283 apbo_ltm <= apb_none;
284 ahbo_wfp <= ahbm_none;
285
286 END beh; No newline at end of file
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@@ -10,8 +10,8 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 EFFORT=high
10 EFFORT=high
11 XSTOPT=
11 XSTOPT=
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= MINI_LFR_top.vhd \
13 VHDLSYNFILES= config.vhd \
14 config.vhd \
14 MINI_LFR_top.vhd \
15 leon3_soc.vhd
15 leon3_soc.vhd
16
16
17 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
17 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
@@ -38,9 +38,12 DIRSKIP = b1553 pcif leon2 leon2ft crypt
38 ./lpp_usb \
38 ./lpp_usb \
39 ./lpp_Header \
39 ./lpp_Header \
40
40
41 FILESKIP = i2cmst.vhd \
41 FILESKIP =lpp_lfr_ms.vhd \
42 i2cmst.vhd \
42 APB_MULTI_DIODE.vhd \
43 APB_MULTI_DIODE.vhd \
43 APB_SIMPLE_DIODE.vhd
44 APB_SIMPLE_DIODE.vhd \
45 Top_MatrixSpec.vhd \
46 APB_FFT.vhd
44
47
45 include $(GRLIB)/bin/Makefile
48 include $(GRLIB)/bin/Makefile
46 include $(GRLIB)/software/leon3/Makefile
49 include $(GRLIB)/software/leon3/Makefile
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@@ -54,7 +54,6 ENTITY leon3_soc IS
54 );
54 );
55 PORT (
55 PORT (
56 clk100MHz : IN STD_ULOGIC;
56 clk100MHz : IN STD_ULOGIC;
57 clk49_152MHz : IN STD_ULOGIC;
58 reset : IN STD_ULOGIC;
57 reset : IN STD_ULOGIC;
59
58
60 errorn : OUT STD_ULOGIC;
59 errorn : OUT STD_ULOGIC;
@@ -90,13 +89,11 ENTITY leon3_soc IS
90 spw2_sout : OUT STD_LOGIC;
89 spw2_sout : OUT STD_LOGIC;
91
90
92 -- WAVEFORM PICKER --------------------------------------------------------
91 -- WAVEFORM PICKER --------------------------------------------------------
93 apbi_wfp : OUT apb_slv_in_type;
92 apbi_ext : OUT apb_slv_in_type;
94 apbo_wfp : IN apb_slv_out_type;
93 apbo_wfp : IN apb_slv_out_type;
95 ahbi_wfp : OUT AHB_Mst_In_Type;
94 apbo_ltm : IN apb_slv_out_type;
96 ahbo_wfp : IN AHB_Mst_Out_Type;
95 ahbi_ext : OUT AHB_Mst_In_Type;
97 -- TIME -------------------------------------------------------------------
96 ahbo_wfp : IN AHB_Mst_Out_Type
98 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
99 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
100
97
101 );
98 );
102 END;
99 END;
@@ -359,25 +356,6 BEGIN
359 END GENERATE;
356 END GENERATE;
360 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
357 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
361
358
362 -------------------------------------------------------------------------------
363 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
364 -------------------------------------------------------------------------------
365 apb_lfr_time_management_1: apb_lfr_time_management
366 GENERIC MAP (
367 pindex => 6,
368 paddr => 6,
369 pmask => 16#fff#,
370 pirq => 12)
371 PORT MAP (
372 clk25MHz => clkm,
373 clk49_152MHz => clk49_152MHz,
374 resetn => rstn,
375 grspw_tick => swno.tickout,
376 apbi => apbi,
377 apbo => apbo(6),
378 coarse_time => coarse_time,
379 fine_time => fine_time);
380
381 -----------------------------------------------------------------------
359 -----------------------------------------------------------------------
382 --- SpaceWire --------------------------------------------------------
360 --- SpaceWire --------------------------------------------------------
383 -----------------------------------------------------------------------
361 -----------------------------------------------------------------------
@@ -465,9 +443,10 BEGIN
465 -------------------------------------------------------------------------------
443 -------------------------------------------------------------------------------
466 -- LFR
444 -- LFR
467 -------------------------------------------------------------------------------
445 -------------------------------------------------------------------------------
468 apbi_wfp <= apbi;
446 apbi_ext <= apbi;
469 apbo(15) <= apbo_wfp;
447 apbo(15) <= apbo_wfp;
470 ahbi_wfp <= ahbmi;
448 apbo(6) <= apbo_ltm;
449 ahbi_ext <= ahbmi;
471 ahbmo(2) <= ahbo_wfp;
450 ahbmo(2) <= ahbo_wfp;
472
451
473 END Behavioral;
452 END Behavioral;
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