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TOP with Leon3 SoC only (no LPP module)
pellion -
r260:083bc4300827 JC
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1 TECHNOLOGY=PROASIC3
2 PACKAGE=\"\"
1 PACKAGE=\"\"
3 SPEED=Std
2 SPEED=Std
4 SYNFREQ=50
3 SYNFREQ=50
5
4
6 PART=A3PE3000L
5 TECHNOLOGY=ProASIC3E
6 LIBERO_DIE=IT14X14M4
7 PART=A3PE3000
8
9 DESIGNER_VOLTAGE=COM
10 DESIGNER_TEMP=COM
7 DESIGNER_PACKAGE=FBGA
11 DESIGNER_PACKAGE=FBGA
8 DESIGNER_PINS=324
12 DESIGNER_PINS=324
9 DESIGNER_VOLTAGE=COM
10 DESIGNER_TEMP=COM
11
13
12 MANUFACTURER=Actel
14 MANUFACTURER=Actel
15 MGCTECHNOLOGY=Proasic3
13 MGCPART=$(PART)
16 MGCPART=$(PART)
14 MGCTECHNOLOGY=PROASIC3
15 MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
17 MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
16 LIBERO_DIE=IT14X14M4LDP
17 LIBERO_PACKAGE=fg$(DESIGNER_PINS)
18 LIBERO_PACKAGE=fg$(DESIGNER_PINS)
18
19
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@@ -1,261 +1,286
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL; -- PLE
35 USE gaisler.spacewire.ALL; -- PLE
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 USE work.config.ALL;
38 USE work.config.ALL;
39 LIBRARY lpp;
39 LIBRARY lpp;
40 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_memory.ALL;
41 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_ad_conv.ALL;
42 USE lpp.lpp_lfr_pkg.ALL;
42 USE lpp.lpp_lfr_pkg.ALL;
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46
46
47 ENTITY MINI_LFR_top IS
47 ENTITY MINI_LFR_top IS
48
48
49 PORT (
49 PORT (
50 clk_50 : IN STD_LOGIC;
50 clk_50 : IN STD_LOGIC;
51 clk_49 : IN STD_LOGIC;
51 clk_49 : IN STD_LOGIC;
52 reset : IN STD_LOGIC;
52 reset : IN STD_LOGIC;
53 --BPs
53 --BPs
54 BP0 : IN STD_LOGIC;
54 BP0 : IN STD_LOGIC;
55 BP1 : IN STD_LOGIC;
55 BP1 : IN STD_LOGIC;
56 --LEDs
56 --LEDs
57 LED0 : OUT STD_LOGIC;
57 LED0 : OUT STD_LOGIC;
58 LED1 : OUT STD_LOGIC;
58 LED1 : OUT STD_LOGIC;
59 LED2 : OUT STD_LOGIC;
59 LED2 : OUT STD_LOGIC;
60 --UARTs
60 --UARTs
61 TXD1 : IN STD_LOGIC;
61 TXD1 : IN STD_LOGIC;
62 RXD1 : OUT STD_LOGIC;
62 RXD1 : OUT STD_LOGIC;
63 nCTS1 : OUT STD_LOGIC;
63 nCTS1 : OUT STD_LOGIC;
64 nRTS1 : IN STD_LOGIC;
64 nRTS1 : IN STD_LOGIC;
65
65
66 TXD2 : IN STD_LOGIC;
66 TXD2 : IN STD_LOGIC;
67 RXD2 : OUT STD_LOGIC;
67 RXD2 : OUT STD_LOGIC;
68 nCTS2 : OUT STD_LOGIC;
68 nCTS2 : OUT STD_LOGIC;
69 nDTR2 : IN STD_LOGIC;
69 nDTR2 : IN STD_LOGIC;
70 nRTS2 : IN STD_LOGIC;
70 nRTS2 : IN STD_LOGIC;
71 nDCD2 : OUT STD_LOGIC;
71 nDCD2 : OUT STD_LOGIC;
72
72
73 --EXT CONNECTOR
73 --EXT CONNECTOR
74 IO0 : INOUT STD_LOGIC;
74 IO0 : INOUT STD_LOGIC;
75 IO1 : INOUT STD_LOGIC;
75 IO1 : INOUT STD_LOGIC;
76 IO2 : INOUT STD_LOGIC;
76 IO2 : INOUT STD_LOGIC;
77 IO3 : INOUT STD_LOGIC;
77 IO3 : INOUT STD_LOGIC;
78 IO4 : INOUT STD_LOGIC;
78 IO4 : INOUT STD_LOGIC;
79 IO5 : INOUT STD_LOGIC;
79 IO5 : INOUT STD_LOGIC;
80 IO6 : INOUT STD_LOGIC;
80 IO6 : INOUT STD_LOGIC;
81 IO7 : INOUT STD_LOGIC;
81 IO7 : INOUT STD_LOGIC;
82 IO8 : INOUT STD_LOGIC;
82 IO8 : INOUT STD_LOGIC;
83 IO9 : INOUT STD_LOGIC;
83 IO9 : INOUT STD_LOGIC;
84 IO10 : INOUT STD_LOGIC;
84 IO10 : INOUT STD_LOGIC;
85 IO11 : INOUT STD_LOGIC;
85 IO11 : INOUT STD_LOGIC;
86
86
87 --SPACE WIRE
87 --SPACE WIRE
88 SPW_EN : OUT STD_LOGIC; -- 0 => off
88 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
89 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_SIN : IN STD_LOGIC;
90 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_DOUT : OUT STD_LOGIC;
91 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_SOUT : OUT STD_LOGIC;
92 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
93 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_SIN : IN STD_LOGIC;
94 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_DOUT : OUT STD_LOGIC;
95 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_SOUT : OUT STD_LOGIC;
96 SPW_RED_SOUT : OUT STD_LOGIC;
97 -- MINI LFR ADC INPUTS
97 -- MINI LFR ADC INPUTS
98 ADC_nCS : OUT STD_LOGIC;
98 ADC_nCS : OUT STD_LOGIC;
99 ADC_CLK : OUT STD_LOGIC;
99 ADC_CLK : OUT STD_LOGIC;
100 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
100 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101
101
102 -- SRAM
102 -- SRAM
103 SRAM_nWE : OUT STD_LOGIC;
103 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_CE : OUT STD_LOGIC;
104 SRAM_CE : OUT STD_LOGIC;
105 SRAM_nOE : OUT STD_LOGIC;
105 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
106 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
107 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
108 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 );
109 );
110
110
111 END MINI_LFR_top;
111 END MINI_LFR_top;
112
112
113
113
114 ARCHITECTURE beh OF MINI_LFR_top IS
114 ARCHITECTURE beh OF MINI_LFR_top IS
115
115
116 COMPONENT leon3_soc
116 COMPONENT leon3_soc
117 GENERIC (
117 GENERIC (
118 fabtech : INTEGER;
118 fabtech : INTEGER;
119 memtech : INTEGER;
119 memtech : INTEGER;
120 padtech : INTEGER;
120 padtech : INTEGER;
121 clktech : INTEGER;
121 clktech : INTEGER;
122 disas : INTEGER;
122 disas : INTEGER;
123 dbguart : INTEGER;
123 dbguart : INTEGER;
124 pclow : INTEGER);
124 pclow : INTEGER);
125 PORT (
125 PORT (
126 clk100MHz : IN STD_ULOGIC;
126 clk100MHz : IN STD_ULOGIC;
127 clk49_152MHz : IN STD_ULOGIC;
128 reset : IN STD_ULOGIC;
127 reset : IN STD_ULOGIC;
129 errorn : OUT STD_ULOGIC;
128 errorn : OUT STD_ULOGIC;
130 ahbrxd : IN STD_ULOGIC;
129 ahbrxd : IN STD_ULOGIC;
131 ahbtxd : OUT STD_ULOGIC;
130 ahbtxd : OUT STD_ULOGIC;
132 urxd1 : IN STD_ULOGIC;
131 urxd1 : IN STD_ULOGIC;
133 utxd1 : OUT STD_ULOGIC;
132 utxd1 : OUT STD_ULOGIC;
134 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
133 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
135 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
134 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
136 nSRAM_BE0 : OUT STD_LOGIC;
135 nSRAM_BE0 : OUT STD_LOGIC;
137 nSRAM_BE1 : OUT STD_LOGIC;
136 nSRAM_BE1 : OUT STD_LOGIC;
138 nSRAM_BE2 : OUT STD_LOGIC;
137 nSRAM_BE2 : OUT STD_LOGIC;
139 nSRAM_BE3 : OUT STD_LOGIC;
138 nSRAM_BE3 : OUT STD_LOGIC;
140 nSRAM_WE : OUT STD_LOGIC;
139 nSRAM_WE : OUT STD_LOGIC;
141 nSRAM_CE : OUT STD_LOGIC;
140 nSRAM_CE : OUT STD_LOGIC;
142 nSRAM_OE : OUT STD_LOGIC;
141 nSRAM_OE : OUT STD_LOGIC;
143 spw1_din : IN STD_LOGIC;
142 spw1_din : IN STD_LOGIC;
144 spw1_sin : IN STD_LOGIC;
143 spw1_sin : IN STD_LOGIC;
145 spw1_dout : OUT STD_LOGIC;
144 spw1_dout : OUT STD_LOGIC;
146 spw1_sout : OUT STD_LOGIC;
145 spw1_sout : OUT STD_LOGIC;
147 spw2_din : IN STD_LOGIC;
146 spw2_din : IN STD_LOGIC;
148 spw2_sin : IN STD_LOGIC;
147 spw2_sin : IN STD_LOGIC;
149 spw2_dout : OUT STD_LOGIC;
148 spw2_dout : OUT STD_LOGIC;
150 spw2_sout : OUT STD_LOGIC;
149 spw2_sout : OUT STD_LOGIC;
151 apbi_wfp : OUT apb_slv_in_type;
150 apbi_ext : OUT apb_slv_in_type;
152 apbo_wfp : IN apb_slv_out_type;
151 apbo_wfp : IN apb_slv_out_type;
153 ahbi_wfp : OUT AHB_Mst_In_Type;
152 apbo_ltm : IN apb_slv_out_type;
154 ahbo_wfp : IN AHB_Mst_Out_Type;
153 ahbi_ext : OUT AHB_Mst_In_Type;
155 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
154 ahbo_wfp : IN AHB_Mst_Out_Type);
156 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
157 END COMPONENT;
155 END COMPONENT;
156
157 -----------------------------------------------------------------------------
158 SIGNAL apbi : apb_slv_in_type;
159 SIGNAL apbo_wfp : apb_slv_out_type;
160 SIGNAL apbo_ltm : apb_slv_out_type;
161 SIGNAL ahbi : AHB_Mst_In_Type;
162 SIGNAL ahbo_wfp : AHB_Mst_Out_Type;
163 --
164 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
165 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
166 --
167 SIGNAL errorn : STD_LOGIC;
168 -- UART AHB ---------------------------------------------------------------
169 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
170 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
171
172 -- UART APB ---------------------------------------------------------------
173 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
174 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
175 --
176 SIGNAL I00_s : STD_LOGIC;
158
177
159 BEGIN -- beh
178 BEGIN -- beh
160
179
161 PROCESS (clk_50, reset)
180 PROCESS (clk_50, reset)
162 BEGIN -- PROCESS
181 BEGIN -- PROCESS
163 IF reset = '0' THEN -- asynchronous reset (active low)
182 IF reset = '0' THEN -- asynchronous reset (active low)
164 LED0 <= '0';
183 LED0 <= '0';
165 LED1 <= '0';
184 LED1 <= '0';
166 LED2 <= '0';
185 LED2 <= '0';
186 IO1 <= '0';
187 IO2 <= '1';
188 IO3 <= '0';
189 IO4 <= '0';
190 IO5 <= '0';
191 IO6 <= '0';
192 IO7 <= '0';
193 IO8 <= '0';
194 IO9 <= '0';
195 IO10 <= '0';
196 IO11 <= '0';
167 ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge
197 ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge
168 LED0 <= '0';
198 LED0 <= '0';
169 LED1 <= '1';
199 LED1 <= '1';
170 LED2 <= BP0;
200 LED2 <= BP0;
201 IO1 <= '1';
202 IO2 <= '0';
203 IO3 <= ADC_SDO(0);
204 IO4 <= ADC_SDO(1);
205 IO5 <= ADC_SDO(2);
206 IO6 <= ADC_SDO(3);
207 IO7 <= ADC_SDO(4);
208 IO8 <= ADC_SDO(5);
209 IO9 <= ADC_SDO(6);
210 IO10 <= ADC_SDO(7);
211 IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
171 END IF;
212 END IF;
172 END PROCESS;
213 END PROCESS;
173
214
215 PROCESS (clk_49, reset)
216 BEGIN -- PROCESS
217 IF reset = '0' THEN -- asynchronous reset (active low)
218 I00_s <= '0';
219 ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
220 I00_s <= NOT I00_s;
221 END IF;
222 END PROCESS;
223 IO0 <= I00_s;
224
174 --UARTs
225 --UARTs
175 RXD1 <= '0';
226 nCTS1 <= '0';
176 nCTS1 <= '0';
177 RXD2 <= '0';
178 nCTS2 <= '0';
227 nCTS2 <= '0';
179 nDCD2 <= '0';
228 nDCD2 <= '0';
180
229
181 --EXT CONNECTOR
230 --EXT CONNECTOR
182 IO0 <= clk_49;
183 IO1 <= clk_50;
184
185 IO2 <= SPW_NOM_DIN OR
186 SPW_NOM_SIN OR
187 SPW_RED_DIN OR
188 SPW_RED_SIN;
189
190 IO3 <= ADC_SDO(0);
191 IO4 <= ADC_SDO(1);
192 IO5 <= ADC_SDO(2);
193 IO6 <= ADC_SDO(3);
194 IO7 <= ADC_SDO(4);
195 IO8 <= ADC_SDO(5);
196 IO9 <= ADC_SDO(6);
197 IO10 <= ADC_SDO(7);
198 IO11 <= BP1 OR TXD1 OR TXD2 OR nDTR2 OR nRTS2 OR nRTS1;
199
231
200 --SPACE WIRE
232 --SPACE WIRE
201 SPW_EN <= '0'; -- 0 => off
233 SPW_EN <= '0'; -- 0 => off
202 SPW_NOM_DOUT <= '0';
234
203 SPW_NOM_SOUT <= '0';
204 SPW_RED_DOUT <= '0';
205 SPW_RED_SOUT <= '0';
206 ADC_nCS <= '0';
235 ADC_nCS <= '0';
207 ADC_CLK <= '0';
236 ADC_CLK <= '0';
208
237
209 -- SRAM
210 SRAM_nWE <= '1';
211 SRAM_CE <= '0';
212 SRAM_nOE <= '1';
213 SRAM_nBE <= (OTHERS => '1');
214 SRAM_A <= (OTHERS => '0');
215 SRAM_DQ <= (OTHERS => '0');
216
217
218 leon3mp_1: leon3_soc
238 leon3mp_1: leon3_soc
219 GENERIC MAP (
239 GENERIC MAP (
220 fabtech => fabtech,
240 fabtech => CFG_FABTECH,
221 memtech => memtech,
241 memtech => CFG_MEMTECH,
222 padtech => padtech,
242 padtech => CFG_PADTECH,
223 clktech => clktech,
243 clktech => CFG_CLKTECH,
224 disas => disas,
244 disas => CFG_DISAS,
225 dbguart => dbguart,
245 dbguart => CFG_DUART,
226 pclow => pclow)
246 pclow => CFG_PCLOW)
227 PORT MAP (
247 PORT MAP (
228 clk100MHz => clk100MHz,
248 clk100MHz => clk_50, --
229 clk49_152MHz => clk49_152MHz,
249 reset => reset, --
230 reset => reset,
250 errorn => errorn, --
231 errorn => errorn,
251
232 ahbrxd => ahbrxd,
252 ahbrxd => TXD1, --
233 ahbtxd => ahbtxd,
253 ahbtxd => RXD1, --
234 urxd1 => urxd1,
254 urxd1 => TXD2, --
235 utxd1 => utxd1,
255 utxd1 => RXD2, --
236 address => address,
256 --RAM
237 data => data,
257 address => SRAM_A, --
238 nSRAM_BE0 => nSRAM_BE0,
258 data => SRAM_DQ, --
239 nSRAM_BE1 => nSRAM_BE1,
259 nSRAM_BE0 => SRAM_nBE(0), --
240 nSRAM_BE2 => nSRAM_BE2,
260 nSRAM_BE1 => SRAM_nBE(1), --
241 nSRAM_BE3 => nSRAM_BE3,
261 nSRAM_BE2 => SRAM_nBE(2), --
242 nSRAM_WE => nSRAM_WE,
262 nSRAM_BE3 => SRAM_nBE(3), --
243 nSRAM_CE => nSRAM_CE,
263 nSRAM_WE => SRAM_nWE, --
244 nSRAM_OE => nSRAM_OE,
264 nSRAM_CE => SRAM_CE, --
245 spw1_din => spw1_din,
265 nSRAM_OE => SRAM_nOE, --
246 spw1_sin => spw1_sin,
266 --SPW
247 spw1_dout => spw1_dout,
267 spw1_din => SPW_NOM_DIN, --
248 spw1_sout => spw1_sout,
268 spw1_sin => SPW_NOM_SIN, --
249 spw2_din => spw2_din,
269 spw1_dout => SPW_NOM_DOUT, --
250 spw2_sin => spw2_sin,
270 spw1_sout => SPW_NOM_SOUT, --
251 spw2_dout => spw2_dout,
271 spw2_din => SPW_RED_DIN, --
252 spw2_sout => spw2_sout,
272 spw2_sin => SPW_RED_SIN, --
253 apbi_wfp => apbi_wfp,
273 spw2_dout => SPW_RED_DOUT, --
254 apbo_wfp => apbo_wfp,
274 spw2_sout => SPW_RED_SOUT, --
255 ahbi_wfp => ahbi_wfp,
275
256 ahbo_wfp => ahbo_wfp,
276 apbi_ext => apbi, --
257 coarse_time => coarse_time,
277 apbo_wfp => apbo_wfp, --
258 fine_time => fine_time);
278 apbo_ltm => apbo_ltm, -- lfr time management
279 ahbi_ext => ahbi, --
280 ahbo_wfp => ahbo_wfp); --
259
281
282 apbo_wfp <= apb_none;
283 apbo_ltm <= apb_none;
284 ahbo_wfp <= ahbm_none;
260
285
261 END beh;
286 END beh; No newline at end of file
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@@ -1,49 +1,52
1 VHDLIB=../..
1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=MINI_LFR_top
4 TOP=MINI_LFR_top
5 BOARD=MINI-LFR
5 BOARD=MINI-LFR
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 EFFORT=high
10 EFFORT=high
11 XSTOPT=
11 XSTOPT=
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= MINI_LFR_top.vhd \
13 VHDLSYNFILES= config.vhd \
14 config.vhd \
14 MINI_LFR_top.vhd \
15 leon3_soc.vhd
15 leon3_soc.vhd
16
16
17 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
17 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
18 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
18 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
19 CLEAN=soft-clean
19 CLEAN=soft-clean
20
20
21 TECHLIBS = proasic3e
21 TECHLIBS = proasic3e
22
22
23 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
23 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
24 tmtc openchip hynix ihp gleichmann micron usbhc
24 tmtc openchip hynix ihp gleichmann micron usbhc
25
25
26 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
26 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
27 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
27 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
28 ./amba_lcd_16x2_ctrlr \
28 ./amba_lcd_16x2_ctrlr \
29 ./general_purpose/lpp_AMR \
29 ./general_purpose/lpp_AMR \
30 ./general_purpose/lpp_balise \
30 ./general_purpose/lpp_balise \
31 ./general_purpose/lpp_delay \
31 ./general_purpose/lpp_delay \
32 ./dsp/lpp_fft \
32 ./dsp/lpp_fft \
33 ./lpp_bootloader \
33 ./lpp_bootloader \
34 ./lpp_cna \
34 ./lpp_cna \
35 ./lpp_demux \
35 ./lpp_demux \
36 ./lpp_matrix \
36 ./lpp_matrix \
37 ./lpp_uart \
37 ./lpp_uart \
38 ./lpp_usb \
38 ./lpp_usb \
39 ./lpp_Header \
39 ./lpp_Header \
40
40
41 FILESKIP = i2cmst.vhd \
41 FILESKIP =lpp_lfr_ms.vhd \
42 i2cmst.vhd \
42 APB_MULTI_DIODE.vhd \
43 APB_MULTI_DIODE.vhd \
43 APB_SIMPLE_DIODE.vhd
44 APB_SIMPLE_DIODE.vhd \
45 Top_MatrixSpec.vhd \
46 APB_FFT.vhd
44
47
45 include $(GRLIB)/bin/Makefile
48 include $(GRLIB)/bin/Makefile
46 include $(GRLIB)/software/leon3/Makefile
49 include $(GRLIB)/software/leon3/Makefile
47
50
48 ################## project specific targets ##########################
51 ################## project specific targets ##########################
49
52
Show file before | Show file after | Hide comments
@@ -1,473 +1,452
1 -----------------------------------------------------------------------------
1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19
19
20
20
21 LIBRARY ieee;
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
35 USE esa.memoryctrl.ALL;
36 USE work.config.ALL;
36 USE work.config.ALL;
37 LIBRARY lpp;
37 LIBRARY lpp;
38 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_ad_conv.ALL;
39 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_lfr_pkg.ALL;
40 USE lpp.lpp_lfr_pkg.ALL;
41 USE lpp.iir_filter.ALL;
41 USE lpp.iir_filter.ALL;
42 USE lpp.general_purpose.ALL;
42 USE lpp.general_purpose.ALL;
43 USE lpp.lpp_lfr_time_management.ALL;
43 USE lpp.lpp_lfr_time_management.ALL;
44
44
45 ENTITY leon3_soc IS
45 ENTITY leon3_soc IS
46 GENERIC (
46 GENERIC (
47 fabtech : INTEGER := CFG_FABTECH;
47 fabtech : INTEGER := CFG_FABTECH;
48 memtech : INTEGER := CFG_MEMTECH;
48 memtech : INTEGER := CFG_MEMTECH;
49 padtech : INTEGER := CFG_PADTECH;
49 padtech : INTEGER := CFG_PADTECH;
50 clktech : INTEGER := CFG_CLKTECH;
50 clktech : INTEGER := CFG_CLKTECH;
51 disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
51 disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
52 dbguart : INTEGER := CFG_DUART; -- Print UART on console
52 dbguart : INTEGER := CFG_DUART; -- Print UART on console
53 pclow : INTEGER := CFG_PCLOW
53 pclow : INTEGER := CFG_PCLOW
54 );
54 );
55 PORT (
55 PORT (
56 clk100MHz : IN STD_ULOGIC;
56 clk100MHz : IN STD_ULOGIC;
57 clk49_152MHz : IN STD_ULOGIC;
58 reset : IN STD_ULOGIC;
57 reset : IN STD_ULOGIC;
59
58
60 errorn : OUT STD_ULOGIC;
59 errorn : OUT STD_ULOGIC;
61
60
62 -- UART AHB ---------------------------------------------------------------
61 -- UART AHB ---------------------------------------------------------------
63 ahbrxd : IN STD_ULOGIC; -- DSU rx data
62 ahbrxd : IN STD_ULOGIC; -- DSU rx data
64 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
63 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
65
64
66 -- UART APB ---------------------------------------------------------------
65 -- UART APB ---------------------------------------------------------------
67 urxd1 : IN STD_ULOGIC; -- UART1 rx data
66 urxd1 : IN STD_ULOGIC; -- UART1 rx data
68 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
67 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
69
68
70 -- RAM --------------------------------------------------------------------
69 -- RAM --------------------------------------------------------------------
71 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
70 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
72 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
71 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 nSRAM_BE0 : OUT STD_LOGIC;
72 nSRAM_BE0 : OUT STD_LOGIC;
74 nSRAM_BE1 : OUT STD_LOGIC;
73 nSRAM_BE1 : OUT STD_LOGIC;
75 nSRAM_BE2 : OUT STD_LOGIC;
74 nSRAM_BE2 : OUT STD_LOGIC;
76 nSRAM_BE3 : OUT STD_LOGIC;
75 nSRAM_BE3 : OUT STD_LOGIC;
77 nSRAM_WE : OUT STD_LOGIC;
76 nSRAM_WE : OUT STD_LOGIC;
78 nSRAM_CE : OUT STD_LOGIC;
77 nSRAM_CE : OUT STD_LOGIC;
79 nSRAM_OE : OUT STD_LOGIC;
78 nSRAM_OE : OUT STD_LOGIC;
80
79
81 -- SPW --------------------------------------------------------------------
80 -- SPW --------------------------------------------------------------------
82 spw1_din : IN STD_LOGIC; -- PLE
81 spw1_din : IN STD_LOGIC; -- PLE
83 spw1_sin : IN STD_LOGIC; -- PLE
82 spw1_sin : IN STD_LOGIC; -- PLE
84 spw1_dout : OUT STD_LOGIC; -- PLE
83 spw1_dout : OUT STD_LOGIC; -- PLE
85 spw1_sout : OUT STD_LOGIC; -- PLE
84 spw1_sout : OUT STD_LOGIC; -- PLE
86
85
87 spw2_din : IN STD_LOGIC; -- JCPE --TODO
86 spw2_din : IN STD_LOGIC; -- JCPE --TODO
88 spw2_sin : IN STD_LOGIC; -- JCPE --TODO
87 spw2_sin : IN STD_LOGIC; -- JCPE --TODO
89 spw2_dout : OUT STD_LOGIC; -- JCPE --TODO
88 spw2_dout : OUT STD_LOGIC; -- JCPE --TODO
90 spw2_sout : OUT STD_LOGIC;
89 spw2_sout : OUT STD_LOGIC;
91
90
92 -- WAVEFORM PICKER --------------------------------------------------------
91 -- WAVEFORM PICKER --------------------------------------------------------
93 apbi_wfp : OUT apb_slv_in_type;
92 apbi_ext : OUT apb_slv_in_type;
94 apbo_wfp : IN apb_slv_out_type;
93 apbo_wfp : IN apb_slv_out_type;
95 ahbi_wfp : OUT AHB_Mst_In_Type;
94 apbo_ltm : IN apb_slv_out_type;
96 ahbo_wfp : IN AHB_Mst_Out_Type;
95 ahbi_ext : OUT AHB_Mst_In_Type;
97 -- TIME -------------------------------------------------------------------
96 ahbo_wfp : IN AHB_Mst_Out_Type
98 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
99 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
100
97
101 );
98 );
102 END;
99 END;
103
100
104 ARCHITECTURE Behavioral OF leon3_soc IS
101 ARCHITECTURE Behavioral OF leon3_soc IS
105
102
106 --constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
103 --constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
107 -- CFG_GRETH+CFG_AHB_JTAG;
104 -- CFG_GRETH+CFG_AHB_JTAG;
108 CONSTANT maxahbmsp : INTEGER := CFG_NCPU+
105 CONSTANT maxahbmsp : INTEGER := CFG_NCPU+
109 CFG_AHB_UART
106 CFG_AHB_UART
110 +2;
107 +2;
111 -- 1 is for the SpaceWire module grspw, which is a master
108 -- 1 is for the SpaceWire module grspw, which is a master
112 -- 1 is for the LFR
109 -- 1 is for the LFR
113
110
114 CONSTANT maxahbm : INTEGER := maxahbmsp;
111 CONSTANT maxahbm : INTEGER := maxahbmsp;
115
112
116 --Clk & Rst gοΏ½nοΏ½
113 --Clk & Rst gοΏ½nοΏ½
117 SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0);
114 SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
115 SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 SIGNAL resetnl : STD_ULOGIC;
116 SIGNAL resetnl : STD_ULOGIC;
120 SIGNAL clk2x : STD_ULOGIC;
117 SIGNAL clk2x : STD_ULOGIC;
121 SIGNAL lclk2x : STD_ULOGIC;
118 SIGNAL lclk2x : STD_ULOGIC;
122 SIGNAL lclk25MHz : STD_ULOGIC;
119 SIGNAL lclk25MHz : STD_ULOGIC;
123 SIGNAL lclk50MHz : STD_ULOGIC;
120 SIGNAL lclk50MHz : STD_ULOGIC;
124 SIGNAL lclk100MHz : STD_ULOGIC;
121 SIGNAL lclk100MHz : STD_ULOGIC;
125 SIGNAL clkm : STD_ULOGIC;
122 SIGNAL clkm : STD_ULOGIC;
126 SIGNAL rstn : STD_ULOGIC;
123 SIGNAL rstn : STD_ULOGIC;
127 SIGNAL rstraw : STD_ULOGIC;
124 SIGNAL rstraw : STD_ULOGIC;
128 SIGNAL pciclk : STD_ULOGIC;
125 SIGNAL pciclk : STD_ULOGIC;
129 SIGNAL sdclkl : STD_ULOGIC;
126 SIGNAL sdclkl : STD_ULOGIC;
130 SIGNAL cgi : clkgen_in_type;
127 SIGNAL cgi : clkgen_in_type;
131 SIGNAL cgo : clkgen_out_type;
128 SIGNAL cgo : clkgen_out_type;
132 --- AHB / APB
129 --- AHB / APB
133 SIGNAL apbi : apb_slv_in_type;
130 SIGNAL apbi : apb_slv_in_type;
134 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
131 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
135 SIGNAL ahbsi : ahb_slv_in_type;
132 SIGNAL ahbsi : ahb_slv_in_type;
136 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
133 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
137 SIGNAL ahbmi : ahb_mst_in_type;
134 SIGNAL ahbmi : ahb_mst_in_type;
138 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
135 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
139 --UART
136 --UART
140 SIGNAL ahbuarti : uart_in_type;
137 SIGNAL ahbuarti : uart_in_type;
141 SIGNAL ahbuarto : uart_out_type;
138 SIGNAL ahbuarto : uart_out_type;
142 SIGNAL apbuarti : uart_in_type;
139 SIGNAL apbuarti : uart_in_type;
143 SIGNAL apbuarto : uart_out_type;
140 SIGNAL apbuarto : uart_out_type;
144 --MEM CTRLR
141 --MEM CTRLR
145 SIGNAL memi : memory_in_type;
142 SIGNAL memi : memory_in_type;
146 SIGNAL memo : memory_out_type;
143 SIGNAL memo : memory_out_type;
147 SIGNAL wpo : wprot_out_type;
144 SIGNAL wpo : wprot_out_type;
148 SIGNAL sdo : sdram_out_type;
145 SIGNAL sdo : sdram_out_type;
149 SIGNAL ramcs : STD_ULOGIC;
146 SIGNAL ramcs : STD_ULOGIC;
150 --IRQ
147 --IRQ
151 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
148 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
152 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
149 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
153 --Timer
150 --Timer
154 SIGNAL gpti : gptimer_in_type;
151 SIGNAL gpti : gptimer_in_type;
155 SIGNAL gpto : gptimer_out_type;
152 SIGNAL gpto : gptimer_out_type;
156 --GPIO
153 --GPIO
157 SIGNAL gpioi : gpio_in_type;
154 SIGNAL gpioi : gpio_in_type;
158 SIGNAL gpioo : gpio_out_type;
155 SIGNAL gpioo : gpio_out_type;
159 --DSU
156 --DSU
160 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
157 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
161 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
158 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
162 SIGNAL dsui : dsu_in_type;
159 SIGNAL dsui : dsu_in_type;
163 SIGNAL dsuo : dsu_out_type;
160 SIGNAL dsuo : dsu_out_type;
164
161
165 ---------------------------------------------------------------------
162 ---------------------------------------------------------------------
166 --- AJOUT TEST ------------------------Signaux----------------------
163 --- AJOUT TEST ------------------------Signaux----------------------
167 ---------------------------------------------------------------------
164 ---------------------------------------------------------------------
168
165
169 ---------------------------------------------------------------------
166 ---------------------------------------------------------------------
170 CONSTANT IOAEN : INTEGER := CFG_CAN;
167 CONSTANT IOAEN : INTEGER := CFG_CAN;
171 CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz
168 CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz
172
169
173 -- Spacewire signals
170 -- Spacewire signals
174 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
171 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
175 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
172 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
176 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
173 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
177 SIGNAL spw_rxtxclk : STD_ULOGIC;
174 SIGNAL spw_rxtxclk : STD_ULOGIC;
178 SIGNAL spw_rxclkn : STD_ULOGIC;
175 SIGNAL spw_rxclkn : STD_ULOGIC;
179 SIGNAL spw_clk : STD_LOGIC;
176 SIGNAL spw_clk : STD_LOGIC;
180 SIGNAL swni : grspw_in_type; -- PLE
177 SIGNAL swni : grspw_in_type; -- PLE
181 SIGNAL swno : grspw_out_type; -- PLE
178 SIGNAL swno : grspw_out_type; -- PLE
182 SIGNAL clkmn : STD_ULOGIC; -- PLE
179 SIGNAL clkmn : STD_ULOGIC; -- PLE
183 SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14
180 SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14
184 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
185
182
186 BEGIN
183 BEGIN
187
184
188
185
189 ----------------------------------------------------------------------
186 ----------------------------------------------------------------------
190 --- Reset and Clock generation -------------------------------------
187 --- Reset and Clock generation -------------------------------------
191 ----------------------------------------------------------------------
188 ----------------------------------------------------------------------
192
189
193 vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0');
190 vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0');
194 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
191 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
195
192
196 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
193 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
197
194
198
195
199 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz);
196 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz);
200
197
201 clkgen0 : clkgen -- clock generator
198 clkgen0 : clkgen -- clock generator
202 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
199 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
203 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
200 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
204 PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
201 PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
205
202
206 PROCESS(lclk100MHz)
203 PROCESS(lclk100MHz)
207 BEGIN
204 BEGIN
208 IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN
205 IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN
209 lclk50MHz <= NOT lclk50MHz;
206 lclk50MHz <= NOT lclk50MHz;
210 END IF;
207 END IF;
211 END PROCESS;
208 END PROCESS;
212
209
213 PROCESS(lclk50MHz)
210 PROCESS(lclk50MHz)
214 BEGIN
211 BEGIN
215 IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN
212 IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN
216 lclk25MHz <= NOT lclk25MHz;
213 lclk25MHz <= NOT lclk25MHz;
217 END IF;
214 END IF;
218 END PROCESS;
215 END PROCESS;
219
216
220 lclk2x <= lclk50MHz;
217 lclk2x <= lclk50MHz;
221 spw_clk <= lclk50MHz;
218 spw_clk <= lclk50MHz;
222
219
223 ----------------------------------------------------------------------
220 ----------------------------------------------------------------------
224 --- LEON3 processor / DSU / IRQ ------------------------------------
221 --- LEON3 processor / DSU / IRQ ------------------------------------
225 ----------------------------------------------------------------------
222 ----------------------------------------------------------------------
226
223
227 l3 : IF CFG_LEON3 = 1 GENERATE
224 l3 : IF CFG_LEON3 = 1 GENERATE
228 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
225 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
229 u0 : leon3s -- LEON3 processor
226 u0 : leon3s -- LEON3 processor
230 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
227 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
231 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
228 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
232 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
229 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
233 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
230 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
234 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
231 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
235 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
232 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
236 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
233 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
237 irqi(i), irqo(i), dbgi(i), dbgo(i));
234 irqi(i), irqo(i), dbgi(i), dbgo(i));
238 END GENERATE;
235 END GENERATE;
239 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
236 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
240
237
241 dsugen : IF CFG_DSU = 1 GENERATE
238 dsugen : IF CFG_DSU = 1 GENERATE
242 dsu0 : dsu3 -- LEON3 Debug Support Unit
239 dsu0 : dsu3 -- LEON3 Debug Support Unit
243 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
240 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
244 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
241 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
245 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
242 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
246 dsui.enable <= '1';
243 dsui.enable <= '1';
247 dsui.break <= '0';
244 dsui.break <= '0';
248 END GENERATE;
245 END GENERATE;
249 END GENERATE;
246 END GENERATE;
250
247
251 nodsu : IF CFG_DSU = 0 GENERATE
248 nodsu : IF CFG_DSU = 0 GENERATE
252 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
249 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
253 END GENERATE;
250 END GENERATE;
254
251
255 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
252 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
256 irqctrl0 : irqmp -- interrupt controller
253 irqctrl0 : irqmp -- interrupt controller
257 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
254 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
258 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
255 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
259 END GENERATE;
256 END GENERATE;
260 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
257 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
261 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
258 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
262 irqi(i).irl <= "0000";
259 irqi(i).irl <= "0000";
263 END GENERATE;
260 END GENERATE;
264 apbo(2) <= apb_none;
261 apbo(2) <= apb_none;
265 END GENERATE;
262 END GENERATE;
266
263
267 ----------------------------------------------------------------------
264 ----------------------------------------------------------------------
268 --- Memory controllers ---------------------------------------------
265 --- Memory controllers ---------------------------------------------
269 ----------------------------------------------------------------------
266 ----------------------------------------------------------------------
270 memctrlr : mctrl GENERIC MAP (
267 memctrlr : mctrl GENERIC MAP (
271 hindex => 0,
268 hindex => 0,
272 pindex => 0,
269 pindex => 0,
273 paddr => 0,
270 paddr => 0,
274 srbanks => 1
271 srbanks => 1
275 )
272 )
276 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
273 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
277
274
278 memi.brdyn <= '1';
275 memi.brdyn <= '1';
279 memi.bexcn <= '1';
276 memi.bexcn <= '1';
280 memi.writen <= '1';
277 memi.writen <= '1';
281 memi.wrn <= "1111";
278 memi.wrn <= "1111";
282 memi.bwidth <= "10";
279 memi.bwidth <= "10";
283
280
284 bdr : FOR i IN 0 TO 3 GENERATE
281 bdr : FOR i IN 0 TO 3 GENERATE
285 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
282 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
286 PORT MAP (
283 PORT MAP (
287 data(31-i*8 DOWNTO 24-i*8),
284 data(31-i*8 DOWNTO 24-i*8),
288 memo.data(31-i*8 DOWNTO 24-i*8),
285 memo.data(31-i*8 DOWNTO 24-i*8),
289 memo.bdrive(i),
286 memo.bdrive(i),
290 memi.data(31-i*8 DOWNTO 24-i*8));
287 memi.data(31-i*8 DOWNTO 24-i*8));
291 END GENERATE;
288 END GENERATE;
292
289
293 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
290 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
294 PORT MAP (address, memo.address(21 DOWNTO 2));
291 PORT MAP (address, memo.address(21 DOWNTO 2));
295
292
296 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
293 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
297 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
294 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
298 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
295 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
299 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
296 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
300 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
297 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
301 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
298 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
302 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
299 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
303
300
304 ----------------------------------------------------------------------
301 ----------------------------------------------------------------------
305 --- AHB CONTROLLER -------------------------------------------------
302 --- AHB CONTROLLER -------------------------------------------------
306 ----------------------------------------------------------------------
303 ----------------------------------------------------------------------
307 ahb0 : ahbctrl -- AHB arbiter/multiplexer
304 ahb0 : ahbctrl -- AHB arbiter/multiplexer
308 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
305 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
309 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
306 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
310 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
307 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
311 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
308 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
312
309
313 ----------------------------------------------------------------------
310 ----------------------------------------------------------------------
314 --- AHB UART -------------------------------------------------------
311 --- AHB UART -------------------------------------------------------
315 ----------------------------------------------------------------------
312 ----------------------------------------------------------------------
316 dcomgen : IF CFG_AHB_UART = 1 GENERATE
313 dcomgen : IF CFG_AHB_UART = 1 GENERATE
317 dcom0 : ahbuart
314 dcom0 : ahbuart
318 GENERIC MAP (hindex => 3, pindex => 4, paddr => 4)
315 GENERIC MAP (hindex => 3, pindex => 4, paddr => 4)
319 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3));
316 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3));
320 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
317 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
321 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
318 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
322 END GENERATE;
319 END GENERATE;
323 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
320 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
324
321
325 ----------------------------------------------------------------------
322 ----------------------------------------------------------------------
326 --- APB Bridge -----------------------------------------------------
323 --- APB Bridge -----------------------------------------------------
327 ----------------------------------------------------------------------
324 ----------------------------------------------------------------------
328 apb0 : apbctrl -- AHB/APB bridge
325 apb0 : apbctrl -- AHB/APB bridge
329 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
326 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
330 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
327 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
331
328
332 ----------------------------------------------------------------------
329 ----------------------------------------------------------------------
333 --- GPT Timer ------------------------------------------------------
330 --- GPT Timer ------------------------------------------------------
334 ----------------------------------------------------------------------
331 ----------------------------------------------------------------------
335 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
332 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
336 timer0 : gptimer -- timer unit
333 timer0 : gptimer -- timer unit
337 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
334 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
338 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
335 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
339 nbits => CFG_GPT_TW)
336 nbits => CFG_GPT_TW)
340 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
337 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
341 gpti.dhalt <= dsuo.tstop;
338 gpti.dhalt <= dsuo.tstop;
342 gpti.extclk <= '0';
339 gpti.extclk <= '0';
343 END GENERATE;
340 END GENERATE;
344 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
341 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
345
342
346
343
347 ----------------------------------------------------------------------
344 ----------------------------------------------------------------------
348 --- APB UART -------------------------------------------------------
345 --- APB UART -------------------------------------------------------
349 ----------------------------------------------------------------------
346 ----------------------------------------------------------------------
350 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
347 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
351 uart1 : apbuart -- UART 1
348 uart1 : apbuart -- UART 1
352 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
349 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
353 fifosize => CFG_UART1_FIFO)
350 fifosize => CFG_UART1_FIFO)
354 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
351 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
355 apbuarti.rxd <= urxd1;
352 apbuarti.rxd <= urxd1;
356 apbuarti.extclk <= '0';
353 apbuarti.extclk <= '0';
357 utxd1 <= apbuarto.txd;
354 utxd1 <= apbuarto.txd;
358 apbuarti.ctsn <= '0';
355 apbuarti.ctsn <= '0';
359 END GENERATE;
356 END GENERATE;
360 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
357 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
361
358
362 -------------------------------------------------------------------------------
363 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
364 -------------------------------------------------------------------------------
365 apb_lfr_time_management_1: apb_lfr_time_management
366 GENERIC MAP (
367 pindex => 6,
368 paddr => 6,
369 pmask => 16#fff#,
370 pirq => 12)
371 PORT MAP (
372 clk25MHz => clkm,
373 clk49_152MHz => clk49_152MHz,
374 resetn => rstn,
375 grspw_tick => swno.tickout,
376 apbi => apbi,
377 apbo => apbo(6),
378 coarse_time => coarse_time,
379 fine_time => fine_time);
380
381 -----------------------------------------------------------------------
359 -----------------------------------------------------------------------
382 --- SpaceWire --------------------------------------------------------
360 --- SpaceWire --------------------------------------------------------
383 -----------------------------------------------------------------------
361 -----------------------------------------------------------------------
384
362
385 spw_rxtxclk <= spw_clk;
363 spw_rxtxclk <= spw_clk;
386 spw_rxclkn <= NOT spw_rxtxclk;
364 spw_rxclkn <= NOT spw_rxtxclk;
387
365
388 -- PADS for SPW1
366 -- PADS for SPW1
389 spw1_rxd_pad : inpad GENERIC MAP (tech => padtech)
367 spw1_rxd_pad : inpad GENERIC MAP (tech => padtech)
390 PORT MAP (spw1_din, dtmp(0));
368 PORT MAP (spw1_din, dtmp(0));
391 spw1_rxs_pad : inpad GENERIC MAP (tech => padtech)
369 spw1_rxs_pad : inpad GENERIC MAP (tech => padtech)
392 PORT MAP (spw1_sin, stmp(0));
370 PORT MAP (spw1_sin, stmp(0));
393 spw1_txd_pad : outpad GENERIC MAP (tech => padtech)
371 spw1_txd_pad : outpad GENERIC MAP (tech => padtech)
394 PORT MAP (spw1_dout, swno.d(0));
372 PORT MAP (spw1_dout, swno.d(0));
395 spw1_txs_pad : outpad GENERIC MAP (tech => padtech)
373 spw1_txs_pad : outpad GENERIC MAP (tech => padtech)
396 PORT MAP (spw1_sout, swno.s(0));
374 PORT MAP (spw1_sout, swno.s(0));
397 -- PADS FOR SPW2
375 -- PADS FOR SPW2
398 spw2_rxd_pad : inpad GENERIC MAP (tech => padtech)
376 spw2_rxd_pad : inpad GENERIC MAP (tech => padtech)
399 PORT MAP (spw2_din, dtmp(1));
377 PORT MAP (spw2_din, dtmp(1));
400 spw2_rxs_pad : inpad GENERIC MAP (tech => padtech)
378 spw2_rxs_pad : inpad GENERIC MAP (tech => padtech)
401 PORT MAP (spw2_sin, stmp(1));
379 PORT MAP (spw2_sin, stmp(1));
402 spw2_txd_pad : outpad GENERIC MAP (tech => padtech)
380 spw2_txd_pad : outpad GENERIC MAP (tech => padtech)
403 PORT MAP (spw2_dout, swno.d(1));
381 PORT MAP (spw2_dout, swno.d(1));
404 spw2_txs_pad : outpad GENERIC MAP (tech => padtech)
382 spw2_txs_pad : outpad GENERIC MAP (tech => padtech)
405 PORT MAP (spw2_sout, swno.s(1));
383 PORT MAP (spw2_sout, swno.s(1));
406
384
407 -- GRSPW PHY
385 -- GRSPW PHY
408 --spw1_input: if CFG_SPW_GRSPW = 1 generate
386 --spw1_input: if CFG_SPW_GRSPW = 1 generate
409 spw_inputloop : FOR j IN 0 TO 1 GENERATE
387 spw_inputloop : FOR j IN 0 TO 1 GENERATE
410 spw_phy0 : grspw_phy
388 spw_phy0 : grspw_phy
411 GENERIC MAP(
389 GENERIC MAP(
412 tech => fabtech,
390 tech => fabtech,
413 rxclkbuftype => 1,
391 rxclkbuftype => 1,
414 scantest => 0)
392 scantest => 0)
415 PORT MAP(
393 PORT MAP(
416 rxrst => swno.rxrst,
394 rxrst => swno.rxrst,
417 di => dtmp(j),
395 di => dtmp(j),
418 si => stmp(j),
396 si => stmp(j),
419 rxclko => spw_rxclk(j),
397 rxclko => spw_rxclk(j),
420 do => swni.d(j),
398 do => swni.d(j),
421 ndo => swni.nd(j*5+4 DOWNTO j*5),
399 ndo => swni.nd(j*5+4 DOWNTO j*5),
422 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
400 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
423 END GENERATE spw_inputloop;
401 END GENERATE spw_inputloop;
424
402
425 -- SPW core
403 -- SPW core
426 sw0 : grspwm
404 sw0 : grspwm
427 GENERIC MAP(
405 GENERIC MAP(
428 tech => apa3e,
406 tech => apa3e,
429 hindex => 1,
407 hindex => 1,
430 pindex => 5,
408 pindex => 5,
431 paddr => 5,
409 paddr => 5,
432 pirq => 11,
410 pirq => 11,
433 sysfreq => 25000, -- CPU_FREQ
411 sysfreq => 25000, -- CPU_FREQ
434 rmap => 1,
412 rmap => 1,
435 rmapcrc => 1,
413 rmapcrc => 1,
436 fifosize1 => 16,
414 fifosize1 => 16,
437 fifosize2 => 16,
415 fifosize2 => 16,
438 rxclkbuftype => 1,
416 rxclkbuftype => 1,
439 rxunaligned => 0,
417 rxunaligned => 0,
440 rmapbufs => 4,
418 rmapbufs => 4,
441 ft => 0,
419 ft => 0,
442 netlist => 0,
420 netlist => 0,
443 ports => 2,
421 ports => 2,
444 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
422 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
445 memtech => apa3e,
423 memtech => apa3e,
446 destkey => 2,
424 destkey => 2,
447 spwcore => 1
425 spwcore => 1
448 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
426 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
449 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
427 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
450 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
428 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
451 )
429 )
452 PORT MAP(rstn, clkm, spw_rxclk(0),
430 PORT MAP(rstn, clkm, spw_rxclk(0),
453 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
431 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
454 ahbmi, ahbmo(1), apbi, apbo(5),
432 ahbmi, ahbmo(1), apbi, apbo(5),
455 swni, swno);
433 swni, swno);
456
434
457 swni.tickin <= '0';
435 swni.tickin <= '0';
458 swni.rmapen <= '1';
436 swni.rmapen <= '1';
459 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
437 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
460 swni.tickinraw <= '0';
438 swni.tickinraw <= '0';
461 swni.timein <= (OTHERS => '0');
439 swni.timein <= (OTHERS => '0');
462 swni.dcrstval <= (OTHERS => '0');
440 swni.dcrstval <= (OTHERS => '0');
463 swni.timerrstval <= (OTHERS => '0');
441 swni.timerrstval <= (OTHERS => '0');
464
442
465 -------------------------------------------------------------------------------
443 -------------------------------------------------------------------------------
466 -- LFR
444 -- LFR
467 -------------------------------------------------------------------------------
445 -------------------------------------------------------------------------------
468 apbi_wfp <= apbi;
446 apbi_ext <= apbi;
469 apbo(15) <= apbo_wfp;
447 apbo(15) <= apbo_wfp;
470 ahbi_wfp <= ahbmi;
448 apbo(6) <= apbo_ltm;
449 ahbi_ext <= ahbmi;
471 ahbmo(2) <= ahbo_wfp;
450 ahbmo(2) <= ahbo_wfp;
472
451
473 END Behavioral;
452 END Behavioral;
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