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Exposed tech parameter from filters to top lpp_lfr_filter....
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1 #GRLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=testbench
6 BOARD=LFR-EQM
7 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd
16 VHDLSIMFILES= tb.vhd
17 SIMTOP=testbench
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc
21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
22 CLEAN=soft-clean
23
24 TECHLIBS = axcelerator
25
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 tmtc openchip hynix ihp gleichmann micron usbhc opencores
28
29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
30 pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 \
31 ./amba_lcd_16x2_ctrlr \
32 ./general_purpose/lpp_AMR \
33 ./general_purpose/lpp_balise \
34 ./general_purpose/lpp_delay \
35 ./lpp_bootloader \
36 ./lfr_management \
37 ./lpp_sim \
38 ./lpp_sim/CY7C1061DV33 \
39 ./lpp_cna \
40 ./lpp_uart \
41 ./lpp_usb \
42 ./dsp/lpp_fft \
43
44 FILESKIP = i2cmst.vhd \
45 APB_MULTI_DIODE.vhd \
46 APB_MULTI_DIODE.vhd \
47 Top_MatrixSpec.vhd \
48 APB_FFT.vhd \
49 lpp_lfr_apbreg.vhd \
50 CoreFFT.vhd
51
52 include $(GRLIB)/bin/Makefile
53 include $(GRLIB)/software/leon3/Makefile
54
55 ################## project specific targets ##########################
56
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26 use ieee.numeric_std.all;
27 USE IEEE.std_logic_signed.ALL;
28 USE IEEE.MATH_real.ALL;
29
30 ENTITY generator IS
31
32 GENERIC (
33 AMPLITUDE : INTEGER := 100;
34 NB_BITS : INTEGER := 16);
35
36 PORT (
37 clk : IN STD_LOGIC;
38 rstn : IN STD_LOGIC;
39 run : IN STD_LOGIC;
40
41 data_ack : IN STD_LOGIC;
42 offset : IN STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
43 data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
44 );
45
46 END generator;
47
48 ARCHITECTURE beh OF generator IS
49
50 SIGNAL reg : STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
51 BEGIN -- beh
52
53
54 PROCESS (clk, rstn)
55 variable seed1, seed2: positive; -- seed values for random generator
56 variable rand: real; -- random real-number value in range 0 to 1.0
57 BEGIN -- PROCESS
58 uniform(seed1, seed2, rand);--more entropy by skipping values
59 IF rstn = '0' THEN -- asynchronous reset (active low)
60 reg <= (OTHERS => '0');
61 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
62 IF run = '0' THEN
63 reg <= (OTHERS => '0');
64 ELSE
65 IF data_ack = '1' THEN
66 reg <= std_logic_vector(to_signed(INTEGER( (REAL(AMPLITUDE) * rand) + REAL(to_integer(SIGNED(offset))) ),NB_BITS));
67 END IF;
68 END IF;
69 END IF;
70 END PROCESS;
71
72 data <= reg;
73
74 END beh;
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1
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
4 USE ieee.numeric_std.ALL;
5 USE IEEE.std_logic_signed.ALL;
6 USE IEEE.MATH_real.ALL;
7
8 LIBRARY techmap;
9 USE techmap.gencomp.ALL;
10
11 LIBRARY std;
12 USE std.textio.ALL;
13
14 LIBRARY lpp;
15 USE lpp.iir_filter.ALL;
16 USE lpp.lpp_ad_conv.ALL;
17 USE lpp.FILTERcfg.ALL;
18 USE lpp.lpp_lfr_filter_coeff.ALL;
19 USE lpp.general_purpose.ALL;
20 USE lpp.data_type_pkg.ALL;
21 USE lpp.lpp_lfr_pkg.ALL;
22 USE lpp.general_purpose.ALL;
23
24 ENTITY testbench IS
25 END;
26
27 ARCHITECTURE behav OF testbench IS
28 CONSTANT ChanelCount : INTEGER := 8;
29 CONSTANT Coef_SZ : INTEGER := 9;
30 CONSTANT CoefCntPerCel : INTEGER := 6;
31 CONSTANT CoefPerCel : INTEGER := 5;
32 CONSTANT Cels_count : INTEGER := 5;
33
34 SIGNAL sample : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
35 SIGNAL sample_val : STD_LOGIC;
36
37 SIGNAL sample_fx : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
38 SIGNAL sample_fx_val : STD_LOGIC;
39
40
41
42
43
44
45 SIGNAL TSTAMP : INTEGER := 0;
46 SIGNAL clk : STD_LOGIC := '0';
47 SIGNAL clk_24k : STD_LOGIC := '0';
48 SIGNAL clk_24k_r : STD_LOGIC := '0';
49 SIGNAL rstn : STD_LOGIC;
50
51 SIGNAL signal_gen : Samples(7 DOWNTO 0);
52 SIGNAL offset_gen : Samples(7 DOWNTO 0);
53
54 --SIGNAL sample_fx_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
55
56 SIGNAL sample_fx_wdata : Samples(ChanelCount-1 DOWNTO 0);
57
58
59 COMPONENT generator IS
60 GENERIC (
61 AMPLITUDE : INTEGER := 100;
62 NB_BITS : INTEGER := 16);
63
64 PORT (
65 clk : IN STD_LOGIC;
66 rstn : IN STD_LOGIC;
67 run : IN STD_LOGIC;
68
69 data_ack : IN STD_LOGIC;
70 offset : IN STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
71 data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
72 );
73 END COMPONENT;
74
75
76 FILE log_input : TEXT OPEN write_mode IS "log_input.txt";
77 FILE log_output_fx : TEXT OPEN write_mode IS "log_output_fx.txt";
78
79 SIGNAL end_of_simu : STD_LOGIC := '0';
80
81 BEGIN
82
83 -----------------------------------------------------------------------------
84 -- CLOCK and RESET
85 -----------------------------------------------------------------------------
86 clk <= NOT clk AFTER 5 ns;
87 PROCESS
88 BEGIN -- PROCESS
89 end_of_simu <= '0';
90 WAIT UNTIL clk = '1';
91 rstn <= '0';
92 WAIT UNTIL clk = '1';
93 WAIT UNTIL clk = '1';
94 WAIT UNTIL clk = '1';
95 rstn <= '1';
96 WAIT FOR 2000 ms;
97 end_of_simu <= '1';
98 WAIT UNTIL clk = '1';
99 REPORT "*** END simulation ***" SEVERITY failure;
100 WAIT;
101 END PROCESS;
102 -----------------------------------------------------------------------------
103
104
105 -----------------------------------------------------------------------------
106 -- COMMON TIMESTAMPS
107 -----------------------------------------------------------------------------
108
109 PROCESS(clk)
110 BEGIN
111 IF clk'EVENT AND clk = '1' THEN
112 TSTAMP <= TSTAMP+1;
113 END IF;
114 END PROCESS;
115 -----------------------------------------------------------------------------
116
117
118 -----------------------------------------------------------------------------
119 -- LPP_LFR_FILTER f0
120 -----------------------------------------------------------------------------
121
122 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
123 GENERIC MAP (
124 tech => axcel,
125 Mem_use => use_RAM,
126 Sample_SZ => 18,
127 Coef_SZ => Coef_SZ,
128 Coef_Nb => 25,
129 Coef_sel_SZ => 5,
130 Cels_count => Cels_count,
131 ChanelsCount => ChanelCount)
132 PORT MAP (
133 rstn => rstn,
134 clk => clk,
135 virg_pos => 7,
136 coefs => CoefsInitValCst_v2,
137
138 sample_in_val => sample_val,
139 sample_in => sample,
140 sample_out_val => sample_fx_val,
141 sample_out => sample_fx);
142 -----------------------------------------------------------------------------
143
144
145 -----------------------------------------------------------------------------
146 -- SAMPLE GENERATION
147 -----------------------------------------------------------------------------
148 clk_24k <= NOT clk_24k AFTER 20345 ns;
149
150 PROCESS (clk, rstn)
151 BEGIN -- PROCESS
152 IF rstn = '0' THEN -- asynchronous reset (active low)
153 sample_val <= '0';
154 clk_24k_r <= '0';
155 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
156 clk_24k_r <= clk_24k;
157 IF clk_24k = '1' AND clk_24k_r = '0' THEN
158 sample_val <= '1';
159 ELSE
160 sample_val <= '0';
161 END IF;
162 END IF;
163 END PROCESS;
164 -----------------------------------------------------------------------------
165 generators : FOR I IN 0 TO 7 GENERATE
166 gen1 : generator
167 GENERIC MAP (
168 AMPLITUDE => 100,
169 NB_BITS => 16)
170 PORT MAP (
171 clk => clk,
172 rstn => rstn,
173 run => '1',
174 data_ack => sample_val,
175 offset => offset_gen(I),
176 data => signal_gen(I)
177 );
178 offset_gen(I) <= STD_LOGIC_VECTOR(to_signed((I*200), 16));
179 END GENERATE generators;
180
181 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
182 SampleLoop : FOR j IN 0 TO 15 GENERATE
183 sample(i,j) <= signal_gen(i)(j);
184 sample_fx_wdata(i)(j) <= sample_fx(i,j);
185 END GENERATE;
186
187 sample(i, 16) <= signal_gen(i)(15);
188 sample(i, 17) <= signal_gen(i)(15);
189 END GENERATE;
190
191
192
193 -----------------------------------------------------------------------------
194 -- RECORD SIGNALS
195 -----------------------------------------------------------------------------
196
197 -- PROCESS(sample_val)
198 -- VARIABLE line_var : LINE;
199 -- BEGIN
200 -- IF sample_val'EVENT AND sample_val = '1' THEN
201 -- write(line_var, INTEGER'IMAGE(TSTAMP));
202 -- FOR I IN 0 TO 7 LOOP
203 -- write(line_var, " " & INTEGER'IMAGE(to_integer(SIGNED(signal_gen(I)))));
204 -- END LOOP;
205 -- writeline(log_input, line_var);
206 -- END IF;
207 -- END PROCESS;
208
209 PROCESS(sample_fx_val,end_of_simu)
210 VARIABLE line_var : LINE;
211 BEGIN
212 IF sample_fx_val'EVENT AND sample_fx_val = '1' THEN
213 write(line_var, INTEGER'IMAGE(TSTAMP));
214 FOR I IN 0 TO 5 LOOP
215 write(line_var, " " & INTEGER'IMAGE(to_integer(SIGNED(sample_fx_wdata(I)))));
216 END LOOP;
217 writeline(log_output_fx, line_var);
218 END IF;
219 IF end_of_simu = '1' THEN
220 file_close(log_output_fx);
221 END IF;
222 END PROCESS;
223
224
225
226
227 END;
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1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 tech : INTEGER := inferred;
28 tech : INTEGER := inferred;
29 nb_data_by_buffer_size : INTEGER := 32;
29 nb_data_by_buffer_size : INTEGER := 32;
30 nb_snapshot_param_size : INTEGER := 32;
30 nb_snapshot_param_size : INTEGER := 32;
31 delta_vector_size : INTEGER := 32;
31 delta_vector_size : INTEGER := 32;
32 delta_vector_size_f0_2 : INTEGER := 7;
32 delta_vector_size_f0_2 : INTEGER := 7;
33
33
34 pindex : INTEGER := 15;
34 pindex : INTEGER := 15;
35 paddr : INTEGER := 15;
35 paddr : INTEGER := 15;
36 pmask : INTEGER := 16#fff#;
36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 6;
37 pirq_ms : INTEGER := 6;
38 pirq_wfp : INTEGER := 14;
38 pirq_wfp : INTEGER := 14;
39
39
40 hindex : INTEGER := 2;
40 hindex : INTEGER := 2;
41
41
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"020153";
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"020153";
43
43
44 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
44 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
45 RTL_DESIGN_LIGHT : INTEGER := 0;
45 RTL_DESIGN_LIGHT : INTEGER := 0;
46 WINDOWS_HAANNING_PARAM_SIZE : INTEGER := 15
46 WINDOWS_HAANNING_PARAM_SIZE : INTEGER := 15
47 );
47 );
48 PORT (
48 PORT (
49 clk : IN STD_LOGIC;
49 clk : IN STD_LOGIC;
50 rstn : IN STD_LOGIC;
50 rstn : IN STD_LOGIC;
51 -- SAMPLE
51 -- SAMPLE
52 sample_B : IN Samples(2 DOWNTO 0);
52 sample_B : IN Samples(2 DOWNTO 0);
53 sample_E : IN Samples(4 DOWNTO 0);
53 sample_E : IN Samples(4 DOWNTO 0);
54 sample_val : IN STD_LOGIC;
54 sample_val : IN STD_LOGIC;
55 -- APB
55 -- APB
56 apbi : IN apb_slv_in_type;
56 apbi : IN apb_slv_in_type;
57 apbo : OUT apb_slv_out_type;
57 apbo : OUT apb_slv_out_type;
58 -- AHB
58 -- AHB
59 ahbi : IN AHB_Mst_In_Type;
59 ahbi : IN AHB_Mst_In_Type;
60 ahbo : OUT AHB_Mst_Out_Type;
60 ahbo : OUT AHB_Mst_Out_Type;
61 -- TIME
61 -- TIME
62 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
62 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
63 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
63 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
64 --
64 --
65 data_shaping_BW : OUT STD_LOGIC;
65 data_shaping_BW : OUT STD_LOGIC;
66 --
66 --
67 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
67 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
68 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
68 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
69 );
69 );
70 END lpp_lfr;
70 END lpp_lfr;
71
71
72 ARCHITECTURE beh OF lpp_lfr IS
72 ARCHITECTURE beh OF lpp_lfr IS
73 SIGNAL sample_s : Samples(7 DOWNTO 0);
73 SIGNAL sample_s : Samples(7 DOWNTO 0);
74 --
74 --
75 SIGNAL data_shaping_SP0 : STD_LOGIC;
75 SIGNAL data_shaping_SP0 : STD_LOGIC;
76 SIGNAL data_shaping_SP1 : STD_LOGIC;
76 SIGNAL data_shaping_SP1 : STD_LOGIC;
77 SIGNAL data_shaping_R0 : STD_LOGIC;
77 SIGNAL data_shaping_R0 : STD_LOGIC;
78 SIGNAL data_shaping_R1 : STD_LOGIC;
78 SIGNAL data_shaping_R1 : STD_LOGIC;
79 SIGNAL data_shaping_R2 : STD_LOGIC;
79 SIGNAL data_shaping_R2 : STD_LOGIC;
80 --
80 --
81 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
81 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
82 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
82 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
83 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
83 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
84 --
84 --
85 SIGNAL sample_f0_val : STD_LOGIC;
85 SIGNAL sample_f0_val : STD_LOGIC;
86 SIGNAL sample_f1_val : STD_LOGIC;
86 SIGNAL sample_f1_val : STD_LOGIC;
87 SIGNAL sample_f2_val : STD_LOGIC;
87 SIGNAL sample_f2_val : STD_LOGIC;
88 SIGNAL sample_f3_val : STD_LOGIC;
88 SIGNAL sample_f3_val : STD_LOGIC;
89 --
89 --
90 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
90 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
91 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
91 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
92 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
92 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
93 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
93 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
94 --
94 --
95 SIGNAL sample_f0_data_sim : Samples(5 DOWNTO 0);
95 SIGNAL sample_f0_data_sim : Samples(5 DOWNTO 0);
96 SIGNAL sample_f1_data_sim : Samples(5 DOWNTO 0);
96 SIGNAL sample_f1_data_sim : Samples(5 DOWNTO 0);
97 SIGNAL sample_f2_data_sim : Samples(5 DOWNTO 0);
97 SIGNAL sample_f2_data_sim : Samples(5 DOWNTO 0);
98 SIGNAL sample_f3_data_sim : Samples(5 DOWNTO 0);
98 SIGNAL sample_f3_data_sim : Samples(5 DOWNTO 0);
99 --
99 --
100 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
100 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
101 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
101 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
102 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
102 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
103
103
104 -- SM
104 -- SM
105 SIGNAL ready_matrix_f0 : STD_LOGIC;
105 SIGNAL ready_matrix_f0 : STD_LOGIC;
106 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
106 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
107 SIGNAL ready_matrix_f1 : STD_LOGIC;
107 SIGNAL ready_matrix_f1 : STD_LOGIC;
108 SIGNAL ready_matrix_f2 : STD_LOGIC;
108 SIGNAL ready_matrix_f2 : STD_LOGIC;
109 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
109 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
110 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
110 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
111 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
111 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
112 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
112 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
113 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
113 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
114 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
114 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
115 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
115 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
116 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
116 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
117 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
117 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
118 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
118 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
119
119
120 -- WFP
120 -- WFP
121 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
121 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
122 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
122 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
123 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
123 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
124 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
124 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
125 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
125 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
126 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
126 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
127
127
128 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
128 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
129 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
129 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
130 SIGNAL enable_f0 : STD_LOGIC;
130 SIGNAL enable_f0 : STD_LOGIC;
131 SIGNAL enable_f1 : STD_LOGIC;
131 SIGNAL enable_f1 : STD_LOGIC;
132 SIGNAL enable_f2 : STD_LOGIC;
132 SIGNAL enable_f2 : STD_LOGIC;
133 SIGNAL enable_f3 : STD_LOGIC;
133 SIGNAL enable_f3 : STD_LOGIC;
134 SIGNAL burst_f0 : STD_LOGIC;
134 SIGNAL burst_f0 : STD_LOGIC;
135 SIGNAL burst_f1 : STD_LOGIC;
135 SIGNAL burst_f1 : STD_LOGIC;
136 SIGNAL burst_f2 : STD_LOGIC;
136 SIGNAL burst_f2 : STD_LOGIC;
137
137
138 --SIGNAL run : STD_LOGIC;
138 --SIGNAL run : STD_LOGIC;
139 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
139 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
140
140
141 -----------------------------------------------------------------------------
141 -----------------------------------------------------------------------------
142 --
142 --
143 -----------------------------------------------------------------------------
143 -----------------------------------------------------------------------------
144
144
145 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
145 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
146 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
146 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
147 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
147 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
148 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
148 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
149 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
149 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
150 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
150 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
151
151
152 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
152 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
153 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
153 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
154 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
154 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
155
155
156
156
157 SIGNAL error_buffer_full : STD_LOGIC;
157 SIGNAL error_buffer_full : STD_LOGIC;
158 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
158 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
159
159
160 -----------------------------------------------------------------------------
160 -----------------------------------------------------------------------------
161 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
161 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
162 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
162 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
163 SIGNAL dma_fifo_data_forced_gen : STD_LOGIC_VECTOR(32-1 DOWNTO 0); --21-04-2015
163 SIGNAL dma_fifo_data_forced_gen : STD_LOGIC_VECTOR(32-1 DOWNTO 0); --21-04-2015
164 SIGNAL dma_fifo_data_forced : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015
164 SIGNAL dma_fifo_data_forced : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015
165 SIGNAL dma_fifo_data_debug : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015
165 SIGNAL dma_fifo_data_debug : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015
166 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
168 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
169 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
169 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
170 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
170 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 SIGNAL dma_grant_error : STD_LOGIC;
172 SIGNAL dma_grant_error : STD_LOGIC;
173
173
174 SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
174 SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
175 -----------------------------------------------------------------------------
175 -----------------------------------------------------------------------------
176 SIGNAL sample_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
176 SIGNAL sample_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
177 SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
177 SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
178 SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
178 SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
179 SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
179 SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
180 SIGNAL sample_f3_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
180 SIGNAL sample_f3_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
181
181
182 BEGIN
182 BEGIN
183
183
184 -----------------------------------------------------------------------------
184 -----------------------------------------------------------------------------
185
185
186 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
186 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
187 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
187 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
188 sample_time <= coarse_time & fine_time;
188 sample_time <= coarse_time & fine_time;
189
189
190 -----------------------------------------------------------------------------
190 -----------------------------------------------------------------------------
191 lpp_lfr_filter_1 : lpp_lfr_filter
191 lpp_lfr_filter_1 : lpp_lfr_filter
192 GENERIC MAP (
192 GENERIC MAP (
193 tech => tech,
193 Mem_use => Mem_use,
194 Mem_use => Mem_use,
194 RTL_DESIGN_LIGHT => RTL_DESIGN_LIGHT)
195 RTL_DESIGN_LIGHT => RTL_DESIGN_LIGHT)
195 PORT MAP (
196 PORT MAP (
196 sample => sample_s,
197 sample => sample_s,
197 sample_val => sample_val,
198 sample_val => sample_val,
198 sample_time => sample_time,
199 sample_time => sample_time,
199 clk => clk,
200 clk => clk,
200 rstn => rstn,
201 rstn => rstn,
201 data_shaping_SP0 => data_shaping_SP0,
202 data_shaping_SP0 => data_shaping_SP0,
202 data_shaping_SP1 => data_shaping_SP1,
203 data_shaping_SP1 => data_shaping_SP1,
203 data_shaping_R0 => data_shaping_R0,
204 data_shaping_R0 => data_shaping_R0,
204 data_shaping_R1 => data_shaping_R1,
205 data_shaping_R1 => data_shaping_R1,
205 data_shaping_R2 => data_shaping_R2,
206 data_shaping_R2 => data_shaping_R2,
206 sample_f0_val => sample_f0_val,
207 sample_f0_val => sample_f0_val,
207 sample_f1_val => sample_f1_val,
208 sample_f1_val => sample_f1_val,
208 sample_f2_val => sample_f2_val,
209 sample_f2_val => sample_f2_val,
209 sample_f3_val => sample_f3_val,
210 sample_f3_val => sample_f3_val,
210 sample_f0_wdata => sample_f0_data,
211 sample_f0_wdata => sample_f0_data,
211 sample_f1_wdata => sample_f1_data,
212 sample_f1_wdata => sample_f1_data,
212 sample_f2_wdata => sample_f2_data,
213 sample_f2_wdata => sample_f2_data,
213 sample_f3_wdata => sample_f3_data,
214 sample_f3_wdata => sample_f3_data,
214 sample_f0_time => sample_f0_time,
215 sample_f0_time => sample_f0_time,
215 sample_f1_time => sample_f1_time,
216 sample_f1_time => sample_f1_time,
216 sample_f2_time => sample_f2_time,
217 sample_f2_time => sample_f2_time,
217 sample_f3_time => sample_f3_time
218 sample_f3_time => sample_f3_time
218 );
219 );
219
220
220 -----------------------------------------------------------------------------
221 -----------------------------------------------------------------------------
221 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
222 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
222 GENERIC MAP (
223 GENERIC MAP (
223 nb_data_by_buffer_size => nb_data_by_buffer_size,
224 nb_data_by_buffer_size => nb_data_by_buffer_size,
224 nb_snapshot_param_size => nb_snapshot_param_size,
225 nb_snapshot_param_size => nb_snapshot_param_size,
225 delta_vector_size => delta_vector_size,
226 delta_vector_size => delta_vector_size,
226 delta_vector_size_f0_2 => delta_vector_size_f0_2,
227 delta_vector_size_f0_2 => delta_vector_size_f0_2,
227 pindex => pindex,
228 pindex => pindex,
228 paddr => paddr,
229 paddr => paddr,
229 pmask => pmask,
230 pmask => pmask,
230 pirq_ms => pirq_ms,
231 pirq_ms => pirq_ms,
231 pirq_wfp => pirq_wfp,
232 pirq_wfp => pirq_wfp,
232 top_lfr_version => top_lfr_version)
233 top_lfr_version => top_lfr_version)
233 PORT MAP (
234 PORT MAP (
234 HCLK => clk,
235 HCLK => clk,
235 HRESETn => rstn,
236 HRESETn => rstn,
236 apbi => apbi,
237 apbi => apbi,
237 apbo => apbo,
238 apbo => apbo,
238
239
239 -- run_ms => OPEN,--run_ms,
240 -- run_ms => OPEN,--run_ms,
240
241
241 ready_matrix_f0 => ready_matrix_f0,
242 ready_matrix_f0 => ready_matrix_f0,
242 ready_matrix_f1 => ready_matrix_f1,
243 ready_matrix_f1 => ready_matrix_f1,
243 ready_matrix_f2 => ready_matrix_f2,
244 ready_matrix_f2 => ready_matrix_f2,
244 error_buffer_full => error_buffer_full,
245 error_buffer_full => error_buffer_full,
245 error_input_fifo_write => error_input_fifo_write,
246 error_input_fifo_write => error_input_fifo_write,
246 status_ready_matrix_f0 => status_ready_matrix_f0,
247 status_ready_matrix_f0 => status_ready_matrix_f0,
247 status_ready_matrix_f1 => status_ready_matrix_f1,
248 status_ready_matrix_f1 => status_ready_matrix_f1,
248 status_ready_matrix_f2 => status_ready_matrix_f2,
249 status_ready_matrix_f2 => status_ready_matrix_f2,
249
250
250 matrix_time_f0 => matrix_time_f0,
251 matrix_time_f0 => matrix_time_f0,
251 matrix_time_f1 => matrix_time_f1,
252 matrix_time_f1 => matrix_time_f1,
252 matrix_time_f2 => matrix_time_f2,
253 matrix_time_f2 => matrix_time_f2,
253
254
254 addr_matrix_f0 => addr_matrix_f0,
255 addr_matrix_f0 => addr_matrix_f0,
255 addr_matrix_f1 => addr_matrix_f1,
256 addr_matrix_f1 => addr_matrix_f1,
256 addr_matrix_f2 => addr_matrix_f2,
257 addr_matrix_f2 => addr_matrix_f2,
257
258
258 length_matrix_f0 => length_matrix_f0,
259 length_matrix_f0 => length_matrix_f0,
259 length_matrix_f1 => length_matrix_f1,
260 length_matrix_f1 => length_matrix_f1,
260 length_matrix_f2 => length_matrix_f2,
261 length_matrix_f2 => length_matrix_f2,
261 status_new_err => status_new_err,
262 status_new_err => status_new_err,
262 data_shaping_BW => data_shaping_BW,
263 data_shaping_BW => data_shaping_BW,
263 data_shaping_SP0 => data_shaping_SP0,
264 data_shaping_SP0 => data_shaping_SP0,
264 data_shaping_SP1 => data_shaping_SP1,
265 data_shaping_SP1 => data_shaping_SP1,
265 data_shaping_R0 => data_shaping_R0,
266 data_shaping_R0 => data_shaping_R0,
266 data_shaping_R1 => data_shaping_R1,
267 data_shaping_R1 => data_shaping_R1,
267 data_shaping_R2 => data_shaping_R2,
268 data_shaping_R2 => data_shaping_R2,
268 delta_snapshot => delta_snapshot,
269 delta_snapshot => delta_snapshot,
269 delta_f0 => delta_f0,
270 delta_f0 => delta_f0,
270 delta_f0_2 => delta_f0_2,
271 delta_f0_2 => delta_f0_2,
271 delta_f1 => delta_f1,
272 delta_f1 => delta_f1,
272 delta_f2 => delta_f2,
273 delta_f2 => delta_f2,
273 nb_data_by_buffer => nb_data_by_buffer,
274 nb_data_by_buffer => nb_data_by_buffer,
274 nb_snapshot_param => nb_snapshot_param,
275 nb_snapshot_param => nb_snapshot_param,
275 enable_f0 => enable_f0,
276 enable_f0 => enable_f0,
276 enable_f1 => enable_f1,
277 enable_f1 => enable_f1,
277 enable_f2 => enable_f2,
278 enable_f2 => enable_f2,
278 enable_f3 => enable_f3,
279 enable_f3 => enable_f3,
279 burst_f0 => burst_f0,
280 burst_f0 => burst_f0,
280 burst_f1 => burst_f1,
281 burst_f1 => burst_f1,
281 burst_f2 => burst_f2,
282 burst_f2 => burst_f2,
282 run => OPEN,
283 run => OPEN,
283 start_date => start_date,
284 start_date => start_date,
284 wfp_status_buffer_ready => wfp_status_buffer_ready,
285 wfp_status_buffer_ready => wfp_status_buffer_ready,
285 wfp_addr_buffer => wfp_addr_buffer,
286 wfp_addr_buffer => wfp_addr_buffer,
286 wfp_length_buffer => wfp_length_buffer,
287 wfp_length_buffer => wfp_length_buffer,
287
288
288 wfp_ready_buffer => wfp_ready_buffer,
289 wfp_ready_buffer => wfp_ready_buffer,
289 wfp_buffer_time => wfp_buffer_time,
290 wfp_buffer_time => wfp_buffer_time,
290 wfp_error_buffer_full => wfp_error_buffer_full,
291 wfp_error_buffer_full => wfp_error_buffer_full,
291 -------------------------------------------------------------------------
292 -------------------------------------------------------------------------
292 sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16),
293 sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16),
293 sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16),
294 sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16),
294 sample_f3_e2 => sample_f3_data(3*16-1 DOWNTO 2*16),
295 sample_f3_e2 => sample_f3_data(3*16-1 DOWNTO 2*16),
295 sample_f3_valid => sample_f3_val,
296 sample_f3_valid => sample_f3_val,
296 debug_vector => apb_reg_debug_vector
297 debug_vector => apb_reg_debug_vector
297 );
298 );
298
299
299 -----------------------------------------------------------------------------
300 -----------------------------------------------------------------------------
300 -----------------------------------------------------------------------------
301 -----------------------------------------------------------------------------
301 lpp_waveform_1 : lpp_waveform
302 lpp_waveform_1 : lpp_waveform
302 GENERIC MAP (
303 GENERIC MAP (
303 tech => tech,
304 tech => tech,
304 data_size => 6*16,
305 data_size => 6*16,
305 nb_data_by_buffer_size => nb_data_by_buffer_size,
306 nb_data_by_buffer_size => nb_data_by_buffer_size,
306 nb_snapshot_param_size => nb_snapshot_param_size,
307 nb_snapshot_param_size => nb_snapshot_param_size,
307 delta_vector_size => delta_vector_size,
308 delta_vector_size => delta_vector_size,
308 delta_vector_size_f0_2 => delta_vector_size_f0_2
309 delta_vector_size_f0_2 => delta_vector_size_f0_2
309 )
310 )
310 PORT MAP (
311 PORT MAP (
311 clk => clk,
312 clk => clk,
312 rstn => rstn,
313 rstn => rstn,
313
314
314 reg_run => '1',--run,
315 reg_run => '1',--run,
315 reg_start_date => start_date,
316 reg_start_date => start_date,
316 reg_delta_snapshot => delta_snapshot,
317 reg_delta_snapshot => delta_snapshot,
317 reg_delta_f0 => delta_f0,
318 reg_delta_f0 => delta_f0,
318 reg_delta_f0_2 => delta_f0_2,
319 reg_delta_f0_2 => delta_f0_2,
319 reg_delta_f1 => delta_f1,
320 reg_delta_f1 => delta_f1,
320 reg_delta_f2 => delta_f2,
321 reg_delta_f2 => delta_f2,
321
322
322 enable_f0 => enable_f0,
323 enable_f0 => enable_f0,
323 enable_f1 => enable_f1,
324 enable_f1 => enable_f1,
324 enable_f2 => enable_f2,
325 enable_f2 => enable_f2,
325 enable_f3 => enable_f3,
326 enable_f3 => enable_f3,
326 burst_f0 => burst_f0,
327 burst_f0 => burst_f0,
327 burst_f1 => burst_f1,
328 burst_f1 => burst_f1,
328 burst_f2 => burst_f2,
329 burst_f2 => burst_f2,
329
330
330 nb_data_by_buffer => nb_data_by_buffer,
331 nb_data_by_buffer => nb_data_by_buffer,
331 nb_snapshot_param => nb_snapshot_param,
332 nb_snapshot_param => nb_snapshot_param,
332 status_new_err => status_new_err,
333 status_new_err => status_new_err,
333
334
334 status_buffer_ready => wfp_status_buffer_ready,
335 status_buffer_ready => wfp_status_buffer_ready,
335 addr_buffer => wfp_addr_buffer,
336 addr_buffer => wfp_addr_buffer,
336 length_buffer => wfp_length_buffer,
337 length_buffer => wfp_length_buffer,
337 ready_buffer => wfp_ready_buffer,
338 ready_buffer => wfp_ready_buffer,
338 buffer_time => wfp_buffer_time,
339 buffer_time => wfp_buffer_time,
339 error_buffer_full => wfp_error_buffer_full,
340 error_buffer_full => wfp_error_buffer_full,
340
341
341 coarse_time => coarse_time,
342 coarse_time => coarse_time,
342 -- fine_time => fine_time,
343 -- fine_time => fine_time,
343
344
344 --f0
345 --f0
345 data_f0_in_valid => sample_f0_val,
346 data_f0_in_valid => sample_f0_val,
346 data_f0_in => sample_f0_data,
347 data_f0_in => sample_f0_data,
347 data_f0_time => sample_f0_time,
348 data_f0_time => sample_f0_time,
348 --f1
349 --f1
349 data_f1_in_valid => sample_f1_val,
350 data_f1_in_valid => sample_f1_val,
350 data_f1_in => sample_f1_data,
351 data_f1_in => sample_f1_data,
351 data_f1_time => sample_f1_time,
352 data_f1_time => sample_f1_time,
352 --f2
353 --f2
353 data_f2_in_valid => sample_f2_val,
354 data_f2_in_valid => sample_f2_val,
354 data_f2_in => sample_f2_data,
355 data_f2_in => sample_f2_data,
355 data_f2_time => sample_f2_time,
356 data_f2_time => sample_f2_time,
356 --f3
357 --f3
357 data_f3_in_valid => sample_f3_val,
358 data_f3_in_valid => sample_f3_val,
358 data_f3_in => sample_f3_data,
359 data_f3_in => sample_f3_data,
359 data_f3_time => sample_f3_time,
360 data_f3_time => sample_f3_time,
360 -- OUTPUT -- DMA interface
361 -- OUTPUT -- DMA interface
361
362
362 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
363 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
363 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
364 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
364 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
365 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
365 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
366 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
366 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
367 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
367 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
368 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
368 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
369 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
369 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
370 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
370
371
371 );
372 );
372
373
373 -----------------------------------------------------------------------------
374 -----------------------------------------------------------------------------
374 -- Matrix Spectral
375 -- Matrix Spectral
375 -----------------------------------------------------------------------------
376 -----------------------------------------------------------------------------
376 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
377 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
377 NOT(sample_f0_val) & NOT(sample_f0_val);
378 NOT(sample_f0_val) & NOT(sample_f0_val);
378 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
379 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
379 NOT(sample_f1_val) & NOT(sample_f1_val);
380 NOT(sample_f1_val) & NOT(sample_f1_val);
380 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
381 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
381 NOT(sample_f2_val) & NOT(sample_f2_val);
382 NOT(sample_f2_val) & NOT(sample_f2_val);
382
383
383
384
384 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
385 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
385 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
386 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
386 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
387 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
387
388
388 -----------------------------------------------------------------------------
389 -----------------------------------------------------------------------------
389 lpp_lfr_ms_1 : lpp_lfr_ms
390 lpp_lfr_ms_1 : lpp_lfr_ms
390 GENERIC MAP (
391 GENERIC MAP (
391 Mem_use => Mem_use,
392 Mem_use => Mem_use,
392 WINDOWS_HAANNING_PARAM_SIZE => WINDOWS_HAANNING_PARAM_SIZE)
393 WINDOWS_HAANNING_PARAM_SIZE => WINDOWS_HAANNING_PARAM_SIZE)
393 PORT MAP (
394 PORT MAP (
394 clk => clk,
395 clk => clk,
395 rstn => rstn,
396 rstn => rstn,
396
397
397 run => '1',--run_ms,
398 run => '1',--run_ms,
398
399
399 start_date => start_date,
400 start_date => start_date,
400
401
401 coarse_time => coarse_time,
402 coarse_time => coarse_time,
402
403
403 sample_f0_wen => sample_f0_wen,
404 sample_f0_wen => sample_f0_wen,
404 sample_f0_wdata => sample_f0_wdata,
405 sample_f0_wdata => sample_f0_wdata,
405 sample_f0_time => sample_f0_time,
406 sample_f0_time => sample_f0_time,
406 sample_f1_wen => sample_f1_wen,
407 sample_f1_wen => sample_f1_wen,
407 sample_f1_wdata => sample_f1_wdata,
408 sample_f1_wdata => sample_f1_wdata,
408 sample_f1_time => sample_f1_time,
409 sample_f1_time => sample_f1_time,
409 sample_f2_wen => sample_f2_wen,
410 sample_f2_wen => sample_f2_wen,
410 sample_f2_wdata => sample_f2_wdata,
411 sample_f2_wdata => sample_f2_wdata,
411 sample_f2_time => sample_f2_time,
412 sample_f2_time => sample_f2_time,
412
413
413 --DMA
414 --DMA
414 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
415 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
415 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
416 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
416 dma_fifo_ren => dma_fifo_ren(4), -- IN
417 dma_fifo_ren => dma_fifo_ren(4), -- IN
417 dma_buffer_new => dma_buffer_new(4), -- OUT
418 dma_buffer_new => dma_buffer_new(4), -- OUT
418 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
419 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
419 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
420 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
420 dma_buffer_full => dma_buffer_full(4), -- IN
421 dma_buffer_full => dma_buffer_full(4), -- IN
421 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
422 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
422
423
423
424
424
425
425 --REG
426 --REG
426 ready_matrix_f0 => ready_matrix_f0,
427 ready_matrix_f0 => ready_matrix_f0,
427 ready_matrix_f1 => ready_matrix_f1,
428 ready_matrix_f1 => ready_matrix_f1,
428 ready_matrix_f2 => ready_matrix_f2,
429 ready_matrix_f2 => ready_matrix_f2,
429 error_buffer_full => error_buffer_full,
430 error_buffer_full => error_buffer_full,
430 error_input_fifo_write => error_input_fifo_write,
431 error_input_fifo_write => error_input_fifo_write,
431
432
432 status_ready_matrix_f0 => status_ready_matrix_f0,
433 status_ready_matrix_f0 => status_ready_matrix_f0,
433 status_ready_matrix_f1 => status_ready_matrix_f1,
434 status_ready_matrix_f1 => status_ready_matrix_f1,
434 status_ready_matrix_f2 => status_ready_matrix_f2,
435 status_ready_matrix_f2 => status_ready_matrix_f2,
435 addr_matrix_f0 => addr_matrix_f0,
436 addr_matrix_f0 => addr_matrix_f0,
436 addr_matrix_f1 => addr_matrix_f1,
437 addr_matrix_f1 => addr_matrix_f1,
437 addr_matrix_f2 => addr_matrix_f2,
438 addr_matrix_f2 => addr_matrix_f2,
438
439
439 length_matrix_f0 => length_matrix_f0,
440 length_matrix_f0 => length_matrix_f0,
440 length_matrix_f1 => length_matrix_f1,
441 length_matrix_f1 => length_matrix_f1,
441 length_matrix_f2 => length_matrix_f2,
442 length_matrix_f2 => length_matrix_f2,
442
443
443 matrix_time_f0 => matrix_time_f0,
444 matrix_time_f0 => matrix_time_f0,
444 matrix_time_f1 => matrix_time_f1,
445 matrix_time_f1 => matrix_time_f1,
445 matrix_time_f2 => matrix_time_f2,
446 matrix_time_f2 => matrix_time_f2,
446
447
447 debug_vector => debug_vector_ms);
448 debug_vector => debug_vector_ms);
448
449
449 -----------------------------------------------------------------------------
450 -----------------------------------------------------------------------------
450 PROCESS (clk, rstn)
451 PROCESS (clk, rstn)
451 BEGIN
452 BEGIN
452 IF rstn = '0' THEN
453 IF rstn = '0' THEN
453 dma_fifo_data_forced_gen <= X"00040003";
454 dma_fifo_data_forced_gen <= X"00040003";
454 ELSIF clk'event AND clk = '1' THEN
455 ELSIF clk'event AND clk = '1' THEN
455 IF dma_fifo_ren(0) = '0' THEN
456 IF dma_fifo_ren(0) = '0' THEN
456 CASE dma_fifo_data_forced_gen IS
457 CASE dma_fifo_data_forced_gen IS
457 WHEN X"00040003" => dma_fifo_data_forced_gen <= X"00050002";
458 WHEN X"00040003" => dma_fifo_data_forced_gen <= X"00050002";
458 WHEN X"00050002" => dma_fifo_data_forced_gen <= X"00060001";
459 WHEN X"00050002" => dma_fifo_data_forced_gen <= X"00060001";
459 WHEN X"00060001" => dma_fifo_data_forced_gen <= X"00040003";
460 WHEN X"00060001" => dma_fifo_data_forced_gen <= X"00040003";
460 WHEN OTHERS => NULL;
461 WHEN OTHERS => NULL;
461 END CASE;
462 END CASE;
462 END IF;
463 END IF;
463 END IF;
464 END IF;
464 END PROCESS;
465 END PROCESS;
465
466
466 dma_fifo_data_forced(32 * 1 -1 DOWNTO 32 * 0) <= dma_fifo_data_forced_gen;
467 dma_fifo_data_forced(32 * 1 -1 DOWNTO 32 * 0) <= dma_fifo_data_forced_gen;
467 dma_fifo_data_forced(32 * 2 -1 DOWNTO 32 * 1) <= X"A0000100";
468 dma_fifo_data_forced(32 * 2 -1 DOWNTO 32 * 1) <= X"A0000100";
468 dma_fifo_data_forced(32 * 3 -1 DOWNTO 32 * 2) <= X"08001000";
469 dma_fifo_data_forced(32 * 3 -1 DOWNTO 32 * 2) <= X"08001000";
469 dma_fifo_data_forced(32 * 4 -1 DOWNTO 32 * 3) <= X"80007000";
470 dma_fifo_data_forced(32 * 4 -1 DOWNTO 32 * 3) <= X"80007000";
470 dma_fifo_data_forced(32 * 5 -1 DOWNTO 32 * 4) <= X"0A000B00";
471 dma_fifo_data_forced(32 * 5 -1 DOWNTO 32 * 4) <= X"0A000B00";
471
472
472 dma_fifo_data_debug <= dma_fifo_data WHEN DEBUG_FORCE_DATA_DMA = 0 ELSE dma_fifo_data_forced;
473 dma_fifo_data_debug <= dma_fifo_data WHEN DEBUG_FORCE_DATA_DMA = 0 ELSE dma_fifo_data_forced;
473
474
474 DMA_SubSystem_1 : DMA_SubSystem
475 DMA_SubSystem_1 : DMA_SubSystem
475 GENERIC MAP (
476 GENERIC MAP (
476 hindex => hindex,
477 hindex => hindex,
477 CUSTOM_DMA => 1)
478 CUSTOM_DMA => 1)
478 PORT MAP (
479 PORT MAP (
479 clk => clk,
480 clk => clk,
480 rstn => rstn,
481 rstn => rstn,
481 run => '1',--run_dma,
482 run => '1',--run_dma,
482 ahbi => ahbi,
483 ahbi => ahbi,
483 ahbo => ahbo,
484 ahbo => ahbo,
484
485
485 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
486 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
486 fifo_data => dma_fifo_data_debug, --fifo_data,
487 fifo_data => dma_fifo_data_debug, --fifo_data,
487 fifo_ren => dma_fifo_ren, --fifo_ren,
488 fifo_ren => dma_fifo_ren, --fifo_ren,
488
489
489 buffer_new => dma_buffer_new, --buffer_new,
490 buffer_new => dma_buffer_new, --buffer_new,
490 buffer_addr => dma_buffer_addr, --buffer_addr,
491 buffer_addr => dma_buffer_addr, --buffer_addr,
491 buffer_length => dma_buffer_length, --buffer_length,
492 buffer_length => dma_buffer_length, --buffer_length,
492 buffer_full => dma_buffer_full, --buffer_full,
493 buffer_full => dma_buffer_full, --buffer_full,
493 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
494 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
494 grant_error => dma_grant_error,
495 grant_error => dma_grant_error,
495 debug_vector => debug_vector(8 DOWNTO 0)
496 debug_vector => debug_vector(8 DOWNTO 0)
496 ); --grant_error);
497 ); --grant_error);
497
498
498 -----------------------------------------------------------------------------
499 -----------------------------------------------------------------------------
499 -- OBSERVATION for SIMULATION
500 -- OBSERVATION for SIMULATION
500 all_channel_sim: FOR I IN 0 TO 5 GENERATE
501 all_channel_sim: FOR I IN 0 TO 5 GENERATE
501 PROCESS (clk, rstn)
502 PROCESS (clk, rstn)
502 BEGIN -- PROCESS
503 BEGIN -- PROCESS
503 IF rstn = '0' THEN -- asynchronous reset (active low)
504 IF rstn = '0' THEN -- asynchronous reset (active low)
504 sample_f0_data_sim(I) <= (OTHERS => '0');
505 sample_f0_data_sim(I) <= (OTHERS => '0');
505 sample_f1_data_sim(I) <= (OTHERS => '0');
506 sample_f1_data_sim(I) <= (OTHERS => '0');
506 sample_f2_data_sim(I) <= (OTHERS => '0');
507 sample_f2_data_sim(I) <= (OTHERS => '0');
507 sample_f3_data_sim(I) <= (OTHERS => '0');
508 sample_f3_data_sim(I) <= (OTHERS => '0');
508 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
509 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
509 IF sample_f0_val = '1' THEN sample_f0_data_sim(I) <= sample_f0_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
510 IF sample_f0_val = '1' THEN sample_f0_data_sim(I) <= sample_f0_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
510 IF sample_f1_val = '1' THEN sample_f1_data_sim(I) <= sample_f1_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
511 IF sample_f1_val = '1' THEN sample_f1_data_sim(I) <= sample_f1_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
511 IF sample_f2_val = '1' THEN sample_f2_data_sim(I) <= sample_f2_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
512 IF sample_f2_val = '1' THEN sample_f2_data_sim(I) <= sample_f2_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
512 IF sample_f3_val = '1' THEN sample_f3_data_sim(I) <= sample_f3_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
513 IF sample_f3_val = '1' THEN sample_f3_data_sim(I) <= sample_f3_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
513 END IF;
514 END IF;
514 END PROCESS;
515 END PROCESS;
515 END GENERATE all_channel_sim;
516 END GENERATE all_channel_sim;
516 -----------------------------------------------------------------------------
517 -----------------------------------------------------------------------------
517
518
518 END beh;
519 END beh;
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@@ -1,666 +1,667
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26
26
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.lpp_ad_conv.ALL;
28 USE lpp.lpp_ad_conv.ALL;
29 USE lpp.iir_filter.ALL;
29 USE lpp.iir_filter.ALL;
30 USE lpp.FILTERcfg.ALL;
30 USE lpp.FILTERcfg.ALL;
31 USE lpp.lpp_memory.ALL;
31 USE lpp.lpp_memory.ALL;
32 USE lpp.lpp_waveform_pkg.ALL;
32 USE lpp.lpp_waveform_pkg.ALL;
33 USE lpp.cic_pkg.ALL;
33 USE lpp.cic_pkg.ALL;
34 USE lpp.data_type_pkg.ALL;
34 USE lpp.data_type_pkg.ALL;
35 USE lpp.lpp_lfr_filter_coeff.ALL;
35 USE lpp.lpp_lfr_filter_coeff.ALL;
36
36
37 LIBRARY techmap;
37 LIBRARY techmap;
38 USE techmap.gencomp.ALL;
38 USE techmap.gencomp.ALL;
39
39
40 LIBRARY grlib;
40 LIBRARY grlib;
41 USE grlib.amba.ALL;
41 USE grlib.amba.ALL;
42 USE grlib.stdlib.ALL;
42 USE grlib.stdlib.ALL;
43 USE grlib.devices.ALL;
43 USE grlib.devices.ALL;
44 USE GRLIB.DMA2AHB_Package.ALL;
44 USE GRLIB.DMA2AHB_Package.ALL;
45
45
46 ENTITY lpp_lfr_filter IS
46 ENTITY lpp_lfr_filter IS
47 GENERIC(
47 GENERIC(
48 tech : INTEGER := 0;
48 Mem_use : INTEGER := use_RAM;
49 Mem_use : INTEGER := use_RAM;
49 RTL_DESIGN_LIGHT : INTEGER := 0
50 RTL_DESIGN_LIGHT : INTEGER := 0
50 );
51 );
51 PORT (
52 PORT (
52 sample : IN Samples(7 DOWNTO 0);
53 sample : IN Samples(7 DOWNTO 0);
53 sample_val : IN STD_LOGIC;
54 sample_val : IN STD_LOGIC;
54 sample_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
55 sample_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
55 --
56 --
56 clk : IN STD_LOGIC;
57 clk : IN STD_LOGIC;
57 rstn : IN STD_LOGIC;
58 rstn : IN STD_LOGIC;
58 --
59 --
59 data_shaping_SP0 : IN STD_LOGIC;
60 data_shaping_SP0 : IN STD_LOGIC;
60 data_shaping_SP1 : IN STD_LOGIC;
61 data_shaping_SP1 : IN STD_LOGIC;
61 data_shaping_R0 : IN STD_LOGIC;
62 data_shaping_R0 : IN STD_LOGIC;
62 data_shaping_R1 : IN STD_LOGIC;
63 data_shaping_R1 : IN STD_LOGIC;
63 data_shaping_R2 : IN STD_LOGIC;
64 data_shaping_R2 : IN STD_LOGIC;
64 --
65 --
65 sample_f0_val : OUT STD_LOGIC;
66 sample_f0_val : OUT STD_LOGIC;
66 sample_f1_val : OUT STD_LOGIC;
67 sample_f1_val : OUT STD_LOGIC;
67 sample_f2_val : OUT STD_LOGIC;
68 sample_f2_val : OUT STD_LOGIC;
68 sample_f3_val : OUT STD_LOGIC;
69 sample_f3_val : OUT STD_LOGIC;
69 --
70 --
70 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
71 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
71 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
72 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
72 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
73 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
73 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
74 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
74 --
75 --
75 sample_f0_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 sample_f0_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 sample_f1_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
77 sample_f1_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
77 sample_f2_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
78 sample_f2_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
78 sample_f3_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
79 sample_f3_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
79 );
80 );
80 END lpp_lfr_filter;
81 END lpp_lfr_filter;
81
82
82 ARCHITECTURE tb OF lpp_lfr_filter IS
83 ARCHITECTURE tb OF lpp_lfr_filter IS
83
84
84 COMPONENT Downsampling
85 COMPONENT Downsampling
85 GENERIC (
86 GENERIC (
86 ChanelCount : INTEGER;
87 ChanelCount : INTEGER;
87 SampleSize : INTEGER;
88 SampleSize : INTEGER;
88 DivideParam : INTEGER);
89 DivideParam : INTEGER);
89 PORT (
90 PORT (
90 clk : IN STD_LOGIC;
91 clk : IN STD_LOGIC;
91 rstn : IN STD_LOGIC;
92 rstn : IN STD_LOGIC;
92 sample_in_val : IN STD_LOGIC;
93 sample_in_val : IN STD_LOGIC;
93 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
94 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
94 sample_out_val : OUT STD_LOGIC;
95 sample_out_val : OUT STD_LOGIC;
95 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
96 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
96 END COMPONENT;
97 END COMPONENT;
97
98
98 -----------------------------------------------------------------------------
99 -----------------------------------------------------------------------------
99 CONSTANT ChanelCount : INTEGER := 8;
100 CONSTANT ChanelCount : INTEGER := 8;
100
101
101 -----------------------------------------------------------------------------
102 -----------------------------------------------------------------------------
102 SIGNAL sample_val_delay : STD_LOGIC;
103 SIGNAL sample_val_delay : STD_LOGIC;
103 -----------------------------------------------------------------------------
104 -----------------------------------------------------------------------------
104 CONSTANT Coef_SZ : INTEGER := 9;
105 CONSTANT Coef_SZ : INTEGER := 9;
105 CONSTANT CoefCntPerCel : INTEGER := 6;
106 CONSTANT CoefCntPerCel : INTEGER := 6;
106 CONSTANT CoefPerCel : INTEGER := 5;
107 CONSTANT CoefPerCel : INTEGER := 5;
107 CONSTANT Cels_count : INTEGER := 5;
108 CONSTANT Cels_count : INTEGER := 5;
108
109
109 --SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
110 --SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
110 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
111 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
111 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
112 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
112 --SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
113 --SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
113 --
114 --
114 SIGNAL sample_filter_v2_out_sim : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
115 SIGNAL sample_filter_v2_out_sim : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
115
116
116 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
117 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
117 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
118 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
118 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
119 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
120 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
120 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
121 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
121 SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
122 SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
122 SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
123 SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
123 SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
124 SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
124 SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
125 SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
125 SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
126 SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
126 -----------------------------------------------------------------------------
127 -----------------------------------------------------------------------------
127 SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
128 SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
128 SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
129 SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
129 -----------------------------------------------------------------------------
130 -----------------------------------------------------------------------------
130 -- SIGNAL sample_f0_val : STD_LOGIC;
131 -- SIGNAL sample_f0_val : STD_LOGIC;
131 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
132 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
132 SIGNAL sample_f0_s : sample_vector(7 DOWNTO 0, 15 DOWNTO 0);
133 SIGNAL sample_f0_s : sample_vector(7 DOWNTO 0, 15 DOWNTO 0);
133 --
134 --
134 -- SIGNAL sample_f1_val : STD_LOGIC;
135 -- SIGNAL sample_f1_val : STD_LOGIC;
135
136
136 SIGNAL sample_f0_f1_s : samplT(5 DOWNTO 0, 17 DOWNTO 0);
137 SIGNAL sample_f0_f1_s : samplT(5 DOWNTO 0, 17 DOWNTO 0);
137 SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 17 DOWNTO 0);
138 SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 17 DOWNTO 0);
138 SIGNAL sample_f1 : samplT(5 DOWNTO 0, 17 DOWNTO 0);
139 SIGNAL sample_f1 : samplT(5 DOWNTO 0, 17 DOWNTO 0);
139 --
140 --
140 -- SIGNAL sample_f2_val : STD_LOGIC;
141 -- SIGNAL sample_f2_val : STD_LOGIC;
141 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
142 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
142 SIGNAL sample_f2_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
143 SIGNAL sample_f2_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
143 SIGNAL sample_f2_cic_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0);
144 SIGNAL sample_f2_cic_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0);
144 SIGNAL sample_f2_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0);
145 SIGNAL sample_f2_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0);
145 SIGNAL sample_f2_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
146 SIGNAL sample_f2_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
146 SIGNAL sample_f2_cic_val : STD_LOGIC;
147 SIGNAL sample_f2_cic_val : STD_LOGIC;
147 SIGNAL sample_f2_filter_val : STD_LOGIC;
148 SIGNAL sample_f2_filter_val : STD_LOGIC;
148
149
149 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
150 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
150 SIGNAL sample_f3_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
151 SIGNAL sample_f3_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
151 SIGNAL sample_f3_cic_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0);
152 SIGNAL sample_f3_cic_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0);
152 SIGNAL sample_f3_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0);
153 SIGNAL sample_f3_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0);
153 SIGNAL sample_f3_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
154 SIGNAL sample_f3_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
154 SIGNAL sample_f3_cic_val : STD_LOGIC;
155 SIGNAL sample_f3_cic_val : STD_LOGIC;
155 SIGNAL sample_f3_filter_val : STD_LOGIC;
156 SIGNAL sample_f3_filter_val : STD_LOGIC;
156
157
157 -----------------------------------------------------------------------------
158 -----------------------------------------------------------------------------
158 --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
159 --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
159 --SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
160 --SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
160 --SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
161 --SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
161 --SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
162 --SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
162 -----------------------------------------------------------------------------
163 -----------------------------------------------------------------------------
163
164
164 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
165 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
165 SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
166 SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
166 SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
167 SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
167 SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
168 SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
168
169
169 SIGNAL sample_f0_val_s : STD_LOGIC;
170 SIGNAL sample_f0_val_s : STD_LOGIC;
170 SIGNAL sample_f1_val_s : STD_LOGIC;
171 SIGNAL sample_f1_val_s : STD_LOGIC;
171 SIGNAL sample_f1_val_ss : STD_LOGIC;
172 SIGNAL sample_f1_val_ss : STD_LOGIC;
172 SIGNAL sample_f2_val_s : STD_LOGIC;
173 SIGNAL sample_f2_val_s : STD_LOGIC;
173 SIGNAL sample_f3_val_s : STD_LOGIC;
174 SIGNAL sample_f3_val_s : STD_LOGIC;
174
175
175 -----------------------------------------------------------------------------
176 -----------------------------------------------------------------------------
176 -- CONFIG FILTER IIR f0 to f1
177 -- CONFIG FILTER IIR f0 to f1
177 -----------------------------------------------------------------------------
178 -----------------------------------------------------------------------------
178 CONSTANT f0_to_f1_CEL_NUMBER : INTEGER := 5;
179 CONSTANT f0_to_f1_CEL_NUMBER : INTEGER := 5;
179 CONSTANT f0_to_f1_COEFFICIENT_SIZE : INTEGER := 10;
180 CONSTANT f0_to_f1_COEFFICIENT_SIZE : INTEGER := 10;
180 CONSTANT f0_to_f1_POINT_POSITION : INTEGER := 8;
181 CONSTANT f0_to_f1_POINT_POSITION : INTEGER := 8;
181
182
182 CONSTANT f0_to_f1_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) :=
183 CONSTANT f0_to_f1_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) :=
183 (
184 (
184 (1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583),
185 (1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583),
185 (1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351),
186 (1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351),
186 (1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102),
187 (1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102),
187 (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464),
188 (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464),
188 (1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691)
189 (1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691)
189 );
190 );
190 CONSTANT f0_to_f1_gain : COEFF_CEL_REAL :=
191 CONSTANT f0_to_f1_gain : COEFF_CEL_REAL :=
191 ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0);
192 ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0);
192
193
193 CONSTANT coefs_iir_cel_f0_to_f1 : STD_LOGIC_VECTOR((f0_to_f1_CEL_NUMBER*f0_to_f1_COEFFICIENT_SIZE*5)-1 DOWNTO 0)
194 CONSTANT coefs_iir_cel_f0_to_f1 : STD_LOGIC_VECTOR((f0_to_f1_CEL_NUMBER*f0_to_f1_COEFFICIENT_SIZE*5)-1 DOWNTO 0)
194 := get_IIR_CEL_FILTER_CONFIG(
195 := get_IIR_CEL_FILTER_CONFIG(
195 f0_to_f1_COEFFICIENT_SIZE,
196 f0_to_f1_COEFFICIENT_SIZE,
196 f0_to_f1_POINT_POSITION,
197 f0_to_f1_POINT_POSITION,
197 f0_to_f1_CEL_NUMBER,
198 f0_to_f1_CEL_NUMBER,
198 f0_to_f1_sos,
199 f0_to_f1_sos,
199 f0_to_f1_gain);
200 f0_to_f1_gain);
200 -----------------------------------------------------------------------------
201 -----------------------------------------------------------------------------
201
202
202 -----------------------------------------------------------------------------
203 -----------------------------------------------------------------------------
203 -- CONFIG FILTER IIR f2 and f3
204 -- CONFIG FILTER IIR f2 and f3
204 -----------------------------------------------------------------------------
205 -----------------------------------------------------------------------------
205 CONSTANT f2_f3_CEL_NUMBER : INTEGER := 5;
206 CONSTANT f2_f3_CEL_NUMBER : INTEGER := 5;
206 CONSTANT f2_f3_COEFFICIENT_SIZE : INTEGER := 10;
207 CONSTANT f2_f3_COEFFICIENT_SIZE : INTEGER := 10;
207 CONSTANT f2_f3_POINT_POSITION : INTEGER := 8;
208 CONSTANT f2_f3_POINT_POSITION : INTEGER := 8;
208
209
209 CONSTANT f2_f3_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) :=
210 CONSTANT f2_f3_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) :=
210 (
211 (
211 (1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583),
212 (1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583),
212 (1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351),
213 (1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351),
213 (1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102),
214 (1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102),
214 (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464),
215 (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464),
215 (1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691)
216 (1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691)
216 );
217 );
217 CONSTANT f2_f3_gain : COEFF_CEL_REAL :=
218 CONSTANT f2_f3_gain : COEFF_CEL_REAL :=
218 ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0);
219 ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0);
219
220
220 CONSTANT coefs_iir_cel_f2_f3 : STD_LOGIC_VECTOR((f2_f3_CEL_NUMBER*f2_f3_COEFFICIENT_SIZE*5)-1 DOWNTO 0)
221 CONSTANT coefs_iir_cel_f2_f3 : STD_LOGIC_VECTOR((f2_f3_CEL_NUMBER*f2_f3_COEFFICIENT_SIZE*5)-1 DOWNTO 0)
221 := get_IIR_CEL_FILTER_CONFIG(
222 := get_IIR_CEL_FILTER_CONFIG(
222 f2_f3_COEFFICIENT_SIZE,
223 f2_f3_COEFFICIENT_SIZE,
223 f2_f3_POINT_POSITION,
224 f2_f3_POINT_POSITION,
224 f2_f3_CEL_NUMBER,
225 f2_f3_CEL_NUMBER,
225 f2_f3_sos,
226 f2_f3_sos,
226 f2_f3_gain);
227 f2_f3_gain);
227 -----------------------------------------------------------------------------
228 -----------------------------------------------------------------------------
228
229
229 SIGNAL sample_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
230 SIGNAL sample_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
230 SIGNAL sample_f0_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
231 SIGNAL sample_f0_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
231 SIGNAL sample_f1_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
232 SIGNAL sample_f1_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
232 SIGNAL sample_f2_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
233 SIGNAL sample_f2_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
233 SIGNAL sample_f3_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
234 SIGNAL sample_f3_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
234 SIGNAL sample_f0_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
235 SIGNAL sample_f0_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
235 SIGNAL sample_f1_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
236 SIGNAL sample_f1_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
236 -- SIGNAL sample_f2_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
237 -- SIGNAL sample_f2_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
237 -- SIGNAL sample_f3_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
238 -- SIGNAL sample_f3_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
238 SIGNAL sample_filter_v2_out_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
239 SIGNAL sample_filter_v2_out_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
239
240
240 BEGIN
241 BEGIN
241
242
242 -----------------------------------------------------------------------------
243 -----------------------------------------------------------------------------
243 PROCESS (clk, rstn)
244 PROCESS (clk, rstn)
244 BEGIN -- PROCESS
245 BEGIN -- PROCESS
245 IF rstn = '0' THEN -- asynchronous reset (active low)
246 IF rstn = '0' THEN -- asynchronous reset (active low)
246 sample_val_delay <= '0';
247 sample_val_delay <= '0';
247 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
248 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
248 sample_val_delay <= sample_val;
249 sample_val_delay <= sample_val;
249 END IF;
250 END IF;
250 END PROCESS;
251 END PROCESS;
251
252
252 -----------------------------------------------------------------------------
253 -----------------------------------------------------------------------------
253 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
254 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
254 SampleLoop : FOR j IN 0 TO 15 GENERATE
255 SampleLoop : FOR j IN 0 TO 15 GENERATE
255 sample_filter_in(i, j) <= sample(i)(j);
256 sample_filter_in(i, j) <= sample(i)(j);
256 END GENERATE;
257 END GENERATE;
257
258
258 sample_filter_in(i, 16) <= sample(i)(15);
259 sample_filter_in(i, 16) <= sample(i)(15);
259 sample_filter_in(i, 17) <= sample(i)(15);
260 sample_filter_in(i, 17) <= sample(i)(15);
260 END GENERATE;
261 END GENERATE;
261
262
262 coefs_v2 <= CoefsInitValCst_v2;
263 coefs_v2 <= CoefsInitValCst_v2;
263
264
264 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
265 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
265 GENERIC MAP (
266 GENERIC MAP (
266 tech => 0,
267 tech => tech,
267 Mem_use => Mem_use, -- use_RAM
268 Mem_use => Mem_use, -- use_RAM
268 Sample_SZ => 18,
269 Sample_SZ => 18,
269 Coef_SZ => Coef_SZ,
270 Coef_SZ => Coef_SZ,
270 Coef_Nb => 25,
271 Coef_Nb => 25,
271 Coef_sel_SZ => 5,
272 Coef_sel_SZ => 5,
272 Cels_count => Cels_count,
273 Cels_count => Cels_count,
273 ChanelsCount => ChanelCount)
274 ChanelsCount => ChanelCount)
274 PORT MAP (
275 PORT MAP (
275 rstn => rstn,
276 rstn => rstn,
276 clk => clk,
277 clk => clk,
277 virg_pos => 7,
278 virg_pos => 7,
278 coefs => coefs_v2,
279 coefs => coefs_v2,
279 sample_in_val => sample_val_delay,
280 sample_in_val => sample_val_delay,
280 sample_in => sample_filter_in,
281 sample_in => sample_filter_in,
281 sample_out_val => sample_filter_v2_out_val,
282 sample_out_val => sample_filter_v2_out_val,
282 sample_out => sample_filter_v2_out);
283 sample_out => sample_filter_v2_out);
283
284
284 -- TIME --
285 -- TIME --
285 PROCESS (clk, rstn)
286 PROCESS (clk, rstn)
286 BEGIN -- PROCESS
287 BEGIN -- PROCESS
287 IF rstn = '0' THEN -- asynchronous reset (active low)
288 IF rstn = '0' THEN -- asynchronous reset (active low)
288 sample_time_reg <= (OTHERS => '0');
289 sample_time_reg <= (OTHERS => '0');
289 sample_filter_v2_out_time <= (OTHERS => '0');
290 sample_filter_v2_out_time <= (OTHERS => '0');
290 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
291 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
291 IF sample_val = '1' THEN
292 IF sample_val = '1' THEN
292 sample_time_reg <= sample_time;
293 sample_time_reg <= sample_time;
293 END IF;
294 END IF;
294 IF sample_filter_v2_out_val = '1' THEN
295 IF sample_filter_v2_out_val = '1' THEN
295 sample_filter_v2_out_time <= sample_time_reg;
296 sample_filter_v2_out_time <= sample_time_reg;
296 END IF;
297 END IF;
297 END IF;
298 END IF;
298 END PROCESS;
299 END PROCESS;
299 ----------
300 ----------
300
301
301 --for simulation/observation-------------------------------------------------
302 --for simulation/observation-------------------------------------------------
302 ALL_channel_f0_sim: FOR I IN 0 TO ChanelCount-1 GENERATE
303 ALL_channel_f0_sim: FOR I IN 0 TO ChanelCount-1 GENERATE
303 all_bit: FOR J IN 0 TO 17 GENERATE
304 all_bit: FOR J IN 0 TO 17 GENERATE
304 PROCESS (clk, rstn)
305 PROCESS (clk, rstn)
305 BEGIN -- PROCESS
306 BEGIN -- PROCESS
306 IF rstn = '0' THEN -- asynchronous reset (active low)
307 IF rstn = '0' THEN -- asynchronous reset (active low)
307 sample_filter_v2_out_sim(I,J) <= '0';
308 sample_filter_v2_out_sim(I,J) <= '0';
308 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
309 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
309 IF sample_filter_v2_out_val = '1' THEN
310 IF sample_filter_v2_out_val = '1' THEN
310 sample_filter_v2_out_sim(I,J) <= sample_filter_v2_out(I,J);
311 sample_filter_v2_out_sim(I,J) <= sample_filter_v2_out(I,J);
311 END IF;
312 END IF;
312 END IF;
313 END IF;
313 END PROCESS;
314 END PROCESS;
314 END GENERATE all_bit;
315 END GENERATE all_bit;
315 END GENERATE ALL_channel_f0_sim;
316 END GENERATE ALL_channel_f0_sim;
316 -----------------------------------------------------------------------------
317 -----------------------------------------------------------------------------
317
318
318
319
319 -----------------------------------------------------------------------------
320 -----------------------------------------------------------------------------
320 -- DATA_SHAPING
321 -- DATA_SHAPING
321 -----------------------------------------------------------------------------
322 -----------------------------------------------------------------------------
322 all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
323 all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
323 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
324 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
324 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
325 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
325 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
326 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
326 END GENERATE all_data_shaping_in_loop;
327 END GENERATE all_data_shaping_in_loop;
327
328
328 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
329 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
329 sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
330 sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
330
331
331 PROCESS (clk, rstn)
332 PROCESS (clk, rstn)
332 BEGIN -- PROCESS
333 BEGIN -- PROCESS
333 IF rstn = '0' THEN -- asynchronous reset (active low)
334 IF rstn = '0' THEN -- asynchronous reset (active low)
334 sample_data_shaping_out_val <= '0';
335 sample_data_shaping_out_val <= '0';
335 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
336 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
336 sample_data_shaping_out_val <= sample_filter_v2_out_val;
337 sample_data_shaping_out_val <= sample_filter_v2_out_val;
337 END IF;
338 END IF;
338 END PROCESS;
339 END PROCESS;
339
340
340 SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE
341 SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE
341 PROCESS (clk, rstn)
342 PROCESS (clk, rstn)
342 BEGIN
343 BEGIN
343 IF rstn = '0' THEN
344 IF rstn = '0' THEN
344 sample_data_shaping_out(0, j) <= '0';
345 sample_data_shaping_out(0, j) <= '0';
345 sample_data_shaping_out(1, j) <= '0';
346 sample_data_shaping_out(1, j) <= '0';
346 sample_data_shaping_out(2, j) <= '0';
347 sample_data_shaping_out(2, j) <= '0';
347 sample_data_shaping_out(3, j) <= '0';
348 sample_data_shaping_out(3, j) <= '0';
348 sample_data_shaping_out(4, j) <= '0';
349 sample_data_shaping_out(4, j) <= '0';
349 sample_data_shaping_out(5, j) <= '0';
350 sample_data_shaping_out(5, j) <= '0';
350 sample_data_shaping_out(6, j) <= '0';
351 sample_data_shaping_out(6, j) <= '0';
351 sample_data_shaping_out(7, j) <= '0';
352 sample_data_shaping_out(7, j) <= '0';
352 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
353 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
353 sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
354 sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
354 IF data_shaping_SP0 = '1' THEN
355 IF data_shaping_SP0 = '1' THEN
355 sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
356 sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
356 ELSE
357 ELSE
357 sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
358 sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
358 END IF;
359 END IF;
359 IF data_shaping_SP1 = '1' THEN
360 IF data_shaping_SP1 = '1' THEN
360 sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
361 sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
361 ELSE
362 ELSE
362 sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
363 sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
363 END IF;
364 END IF;
364 sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
365 sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
365 sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
366 sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
366 sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
367 sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
367 sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
368 sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
368 sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
369 sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
369 END IF;
370 END IF;
370 END PROCESS;
371 END PROCESS;
371 END GENERATE;
372 END GENERATE;
372
373
373 sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
374 sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
374 ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
375 ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
375 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
376 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
376 sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j);
377 sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j);
377 END GENERATE;
378 END GENERATE;
378 END GENERATE;
379 END GENERATE;
379 -----------------------------------------------------------------------------
380 -----------------------------------------------------------------------------
380 -- F0 -- @24.576 kHz
381 -- F0 -- @24.576 kHz
381 -----------------------------------------------------------------------------
382 -----------------------------------------------------------------------------
382
383
383 Downsampling_f0 : Downsampling
384 Downsampling_f0 : Downsampling
384 GENERIC MAP (
385 GENERIC MAP (
385 ChanelCount => 8,
386 ChanelCount => 8,
386 SampleSize => 16,
387 SampleSize => 16,
387 DivideParam => 4)
388 DivideParam => 4)
388 PORT MAP (
389 PORT MAP (
389 clk => clk,
390 clk => clk,
390 rstn => rstn,
391 rstn => rstn,
391 sample_in_val => sample_filter_v2_out_val_s,
392 sample_in_val => sample_filter_v2_out_val_s,
392 sample_in => sample_filter_v2_out_s,
393 sample_in => sample_filter_v2_out_s,
393 sample_out_val => sample_f0_val_s,
394 sample_out_val => sample_f0_val_s,
394 sample_out => sample_f0);
395 sample_out => sample_f0);
395
396
396 -- TIME --
397 -- TIME --
397 PROCESS (clk, rstn)
398 PROCESS (clk, rstn)
398 BEGIN
399 BEGIN
399 IF rstn = '0' THEN
400 IF rstn = '0' THEN
400 sample_f0_time_reg <= (OTHERS => '0');
401 sample_f0_time_reg <= (OTHERS => '0');
401 ELSIF clk'event AND clk = '1' THEN
402 ELSIF clk'event AND clk = '1' THEN
402 IF sample_f0_val_s = '1' THEN
403 IF sample_f0_val_s = '1' THEN
403 sample_f0_time_reg <= sample_filter_v2_out_time;
404 sample_f0_time_reg <= sample_filter_v2_out_time;
404 END IF;
405 END IF;
405 END IF;
406 END IF;
406 END PROCESS;
407 END PROCESS;
407 sample_f0_time_s <= sample_filter_v2_out_time WHEN sample_f0_val_s = '1' ELSE sample_f0_time_reg;
408 sample_f0_time_s <= sample_filter_v2_out_time WHEN sample_f0_val_s = '1' ELSE sample_f0_time_reg;
408 sample_f0_time <= sample_f0_time_s;
409 sample_f0_time <= sample_f0_time_s;
409 ----------
410 ----------
410
411
411 sample_f0_val <= sample_f0_val_s;
412 sample_f0_val <= sample_f0_val_s;
412
413
413 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
414 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
414 sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
415 sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
415 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
416 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
416 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2
417 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2
417 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1
418 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1
418 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2
419 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2
419 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3
420 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3
420 END GENERATE all_bit_sample_f0;
421 END GENERATE all_bit_sample_f0;
421
422
422 -----------------------------------------------------------------------------
423 -----------------------------------------------------------------------------
423 -- F1 -- @4096 Hz
424 -- F1 -- @4096 Hz
424 -----------------------------------------------------------------------------
425 -----------------------------------------------------------------------------
425
426
426 all_bit_sample_f0_f1 : FOR I IN 15 DOWNTO 0 GENERATE
427 all_bit_sample_f0_f1 : FOR I IN 15 DOWNTO 0 GENERATE
427 sample_f0_f1_s(0,I) <= sample_f0(0,I); --V
428 sample_f0_f1_s(0,I) <= sample_f0(0,I); --V
428 sample_f0_f1_s(1,I) <= sample_f0(1,I) WHEN data_shaping_R1 = '1' ELSE sample_f0(3,I); --E1
429 sample_f0_f1_s(1,I) <= sample_f0(1,I) WHEN data_shaping_R1 = '1' ELSE sample_f0(3,I); --E1
429 sample_f0_f1_s(2,I) <= sample_f0(2,I) WHEN data_shaping_R1 = '1' ELSE sample_f0(4,I); --E2
430 sample_f0_f1_s(2,I) <= sample_f0(2,I) WHEN data_shaping_R1 = '1' ELSE sample_f0(4,I); --E2
430 sample_f0_f1_s(3,I) <= sample_f0(5,I); --B1
431 sample_f0_f1_s(3,I) <= sample_f0(5,I); --B1
431 sample_f0_f1_s(4,I) <= sample_f0(6,I); --B2
432 sample_f0_f1_s(4,I) <= sample_f0(6,I); --B2
432 sample_f0_f1_s(5,I) <= sample_f0(7,I); --B3
433 sample_f0_f1_s(5,I) <= sample_f0(7,I); --B3
433 END GENERATE all_bit_sample_f0_f1;
434 END GENERATE all_bit_sample_f0_f1;
434 all_bit_sample_f0_f1_extended : FOR I IN 17 DOWNTO 16 GENERATE
435 all_bit_sample_f0_f1_extended : FOR I IN 17 DOWNTO 16 GENERATE
435 sample_f0_f1_s(0,I) <= sample_f0(0,15);
436 sample_f0_f1_s(0,I) <= sample_f0(0,15);
436 sample_f0_f1_s(1,I) <= sample_f0(1,15) WHEN data_shaping_R1 = '1' ELSE sample_f0(3,15); --E1
437 sample_f0_f1_s(1,I) <= sample_f0(1,15) WHEN data_shaping_R1 = '1' ELSE sample_f0(3,15); --E1
437 sample_f0_f1_s(2,I) <= sample_f0(2,15) WHEN data_shaping_R1 = '1' ELSE sample_f0(4,15); --E2
438 sample_f0_f1_s(2,I) <= sample_f0(2,15) WHEN data_shaping_R1 = '1' ELSE sample_f0(4,15); --E2
438 sample_f0_f1_s(3,I) <= sample_f0(5,15); --B1
439 sample_f0_f1_s(3,I) <= sample_f0(5,15); --B1
439 sample_f0_f1_s(4,I) <= sample_f0(6,15); --B2
440 sample_f0_f1_s(4,I) <= sample_f0(6,15); --B2
440 sample_f0_f1_s(5,I) <= sample_f0(7,15); --B3
441 sample_f0_f1_s(5,I) <= sample_f0(7,15); --B3
441 END GENERATE all_bit_sample_f0_f1_extended;
442 END GENERATE all_bit_sample_f0_f1_extended;
442
443
443
444
444 IIR_CEL_f0_to_f1 : IIR_CEL_CTRLR_v2
445 IIR_CEL_f0_to_f1 : IIR_CEL_CTRLR_v2
445 GENERIC MAP (
446 GENERIC MAP (
446 tech => 0,
447 tech => tech,
447 Mem_use => Mem_use, -- use_RAM
448 Mem_use => Mem_use, -- use_RAM
448 Sample_SZ => 18,
449 Sample_SZ => 18,
449 Coef_SZ => f0_to_f1_COEFFICIENT_SIZE,
450 Coef_SZ => f0_to_f1_COEFFICIENT_SIZE,
450 Coef_Nb => f0_to_f1_CEL_NUMBER*5,
451 Coef_Nb => f0_to_f1_CEL_NUMBER*5,
451 Coef_sel_SZ => 5,
452 Coef_sel_SZ => 5,
452 Cels_count => f0_to_f1_CEL_NUMBER,
453 Cels_count => f0_to_f1_CEL_NUMBER,
453 ChanelsCount => 6)
454 ChanelsCount => 6)
454 PORT MAP (
455 PORT MAP (
455 rstn => rstn,
456 rstn => rstn,
456 clk => clk,
457 clk => clk,
457 virg_pos => f0_to_f1_POINT_POSITION,
458 virg_pos => f0_to_f1_POINT_POSITION,
458 coefs => coefs_iir_cel_f0_to_f1,
459 coefs => coefs_iir_cel_f0_to_f1,
459
460
460 sample_in_val => sample_f0_val_s,
461 sample_in_val => sample_f0_val_s,
461 sample_in => sample_f0_f1_s,
462 sample_in => sample_f0_f1_s,
462
463
463 sample_out_val => sample_f1_val_s,
464 sample_out_val => sample_f1_val_s,
464 sample_out => sample_f1_s);
465 sample_out => sample_f1_s);
465
466
466 Downsampling_f1 : Downsampling
467 Downsampling_f1 : Downsampling
467 GENERIC MAP (
468 GENERIC MAP (
468 ChanelCount => 6,
469 ChanelCount => 6,
469 SampleSize => 18,
470 SampleSize => 18,
470 DivideParam => 6)
471 DivideParam => 6)
471 PORT MAP (
472 PORT MAP (
472 clk => clk,
473 clk => clk,
473 rstn => rstn,
474 rstn => rstn,
474 sample_in_val => sample_f1_val_s,
475 sample_in_val => sample_f1_val_s,
475 sample_in => sample_f1_s,
476 sample_in => sample_f1_s,
476 sample_out_val => sample_f1_val_ss,
477 sample_out_val => sample_f1_val_ss,
477 sample_out => sample_f1);
478 sample_out => sample_f1);
478
479
479 sample_f1_val <= sample_f1_val_ss;
480 sample_f1_val <= sample_f1_val_ss;
480
481
481 -- TIME --
482 -- TIME --
482 PROCESS (clk, rstn)
483 PROCESS (clk, rstn)
483 BEGIN
484 BEGIN
484 IF rstn = '0' THEN
485 IF rstn = '0' THEN
485 sample_f1_time_reg <= (OTHERS => '0');
486 sample_f1_time_reg <= (OTHERS => '0');
486 ELSIF clk'event AND clk = '1' THEN
487 ELSIF clk'event AND clk = '1' THEN
487 IF sample_f1_val_ss = '1' THEN
488 IF sample_f1_val_ss = '1' THEN
488 sample_f1_time_reg <= sample_f0_time_s;
489 sample_f1_time_reg <= sample_f0_time_s;
489 END IF;
490 END IF;
490 END IF;
491 END IF;
491 END PROCESS;
492 END PROCESS;
492 sample_f1_time_s <= sample_f0_time_s WHEN sample_f1_val_ss = '1' ELSE sample_f1_time_reg;
493 sample_f1_time_s <= sample_f0_time_s WHEN sample_f1_val_ss = '1' ELSE sample_f1_time_reg;
493 sample_f1_time <= sample_f1_time_s;
494 sample_f1_time <= sample_f1_time_s;
494 ----------
495 ----------
495
496
496
497
497 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
498 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
498 all_channel_sample_f1: FOR J IN 5 DOWNTO 0 GENERATE
499 all_channel_sample_f1: FOR J IN 5 DOWNTO 0 GENERATE
499 sample_f1_wdata_s(16*J+I) <= sample_f1(J, I);
500 sample_f1_wdata_s(16*J+I) <= sample_f1(J, I);
500 END GENERATE all_channel_sample_f1;
501 END GENERATE all_channel_sample_f1;
501 END GENERATE all_bit_sample_f1;
502 END GENERATE all_bit_sample_f1;
502
503
503 -----------------------------------------------------------------------------
504 -----------------------------------------------------------------------------
504 -- F2 -- @256 Hz
505 -- F2 -- @256 Hz
505 -- F3 -- @16 Hz
506 -- F3 -- @16 Hz
506 -----------------------------------------------------------------------------
507 -----------------------------------------------------------------------------
507 all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
508 all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
508 sample_f0_s(0, I) <= sample_f0(0, I); -- V
509 sample_f0_s(0, I) <= sample_f0(0, I); -- V
509 sample_f0_s(1, I) <= sample_f0(1, I); -- E1
510 sample_f0_s(1, I) <= sample_f0(1, I); -- E1
510 sample_f0_s(2, I) <= sample_f0(2, I); -- E2
511 sample_f0_s(2, I) <= sample_f0(2, I); -- E2
511 sample_f0_s(3, I) <= sample_f0(5, I); -- B1
512 sample_f0_s(3, I) <= sample_f0(5, I); -- B1
512 sample_f0_s(4, I) <= sample_f0(6, I); -- B2
513 sample_f0_s(4, I) <= sample_f0(6, I); -- B2
513 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
514 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
514 sample_f0_s(6, I) <= sample_f0(3, I); --
515 sample_f0_s(6, I) <= sample_f0(3, I); --
515 sample_f0_s(7, I) <= sample_f0(4, I); --
516 sample_f0_s(7, I) <= sample_f0(4, I); --
516 END GENERATE all_bit_sample_f0_s;
517 END GENERATE all_bit_sample_f0_s;
517
518
518
519
519 cic_lfr_1: cic_lfr_r2
520 cic_lfr_1: cic_lfr_r2
520 GENERIC MAP (
521 GENERIC MAP (
521 tech => 0,
522 tech => tech,
522 use_RAM_nCEL => Mem_use)
523 use_RAM_nCEL => Mem_use)
523 PORT MAP (
524 PORT MAP (
524 clk => clk,
525 clk => clk,
525 rstn => rstn,
526 rstn => rstn,
526 run => '1',
527 run => '1',
527
528
528 param_r2 => data_shaping_R2,
529 param_r2 => data_shaping_R2,
529
530
530 data_in => sample_f0_s,
531 data_in => sample_f0_s,
531 data_in_valid => sample_f0_val_s,
532 data_in_valid => sample_f0_val_s,
532
533
533 data_out_16 => sample_f2_cic,
534 data_out_16 => sample_f2_cic,
534 data_out_16_valid => sample_f2_cic_val,
535 data_out_16_valid => sample_f2_cic_val,
535
536
536 data_out_256 => sample_f3_cic,
537 data_out_256 => sample_f3_cic,
537 data_out_256_valid => sample_f3_cic_val);
538 data_out_256_valid => sample_f3_cic_val);
538
539
539
540
540
541
541 all_channel_sample_f_cic : FOR J IN 5 DOWNTO 0 GENERATE
542 all_channel_sample_f_cic : FOR J IN 5 DOWNTO 0 GENERATE
542 all_bit_sample_f_cic : FOR I IN 15 DOWNTO 0 GENERATE
543 all_bit_sample_f_cic : FOR I IN 15 DOWNTO 0 GENERATE
543 sample_f2_cic_filter(J,I) <= sample_f2_cic(J,I);
544 sample_f2_cic_filter(J,I) <= sample_f2_cic(J,I);
544 sample_f3_cic_filter(J,I) <= sample_f3_cic(J,I);
545 sample_f3_cic_filter(J,I) <= sample_f3_cic(J,I);
545 END GENERATE all_bit_sample_f_cic;
546 END GENERATE all_bit_sample_f_cic;
546 sample_f2_cic_filter(J,16) <= sample_f2_cic(J,15);
547 sample_f2_cic_filter(J,16) <= sample_f2_cic(J,15);
547 sample_f2_cic_filter(J,17) <= sample_f2_cic(J,15);
548 sample_f2_cic_filter(J,17) <= sample_f2_cic(J,15);
548
549
549 sample_f3_cic_filter(J,16) <= sample_f3_cic(J,15);
550 sample_f3_cic_filter(J,16) <= sample_f3_cic(J,15);
550 sample_f3_cic_filter(J,17) <= sample_f3_cic(J,15);
551 sample_f3_cic_filter(J,17) <= sample_f3_cic(J,15);
551 END GENERATE all_channel_sample_f_cic;
552 END GENERATE all_channel_sample_f_cic;
552
553
553 NO_IIR_FILTER_f2_f3: IF RTL_DESIGN_LIGHT = 1 GENERATE
554 NO_IIR_FILTER_f2_f3: IF RTL_DESIGN_LIGHT = 1 GENERATE
554 sample_f2_filter_val <= sample_f2_cic_val;
555 sample_f2_filter_val <= sample_f2_cic_val;
555 sample_f2_filter <= sample_f2_cic_filter;
556 sample_f2_filter <= sample_f2_cic_filter;
556 sample_f3_filter_val <= sample_f3_cic_val;
557 sample_f3_filter_val <= sample_f3_cic_val;
557 sample_f3_filter <= sample_f3_cic_filter;
558 sample_f3_filter <= sample_f3_cic_filter;
558 END GENERATE NO_IIR_FILTER_f2_f3;
559 END GENERATE NO_IIR_FILTER_f2_f3;
559
560
560 YES_IIR_FILTER_f2_f3: IF RTL_DESIGN_LIGHT = 0 GENERATE
561 YES_IIR_FILTER_f2_f3: IF RTL_DESIGN_LIGHT = 0 GENERATE
561 IIR_CEL_CTRLR_v3_1:IIR_CEL_CTRLR_v3
562 IIR_CEL_CTRLR_v3_1:IIR_CEL_CTRLR_v3
562 GENERIC MAP (
563 GENERIC MAP (
563 tech => 0,
564 tech => tech,
564 Mem_use => Mem_use,
565 Mem_use => Mem_use,
565 Sample_SZ => 18,
566 Sample_SZ => 18,
566 Coef_SZ => f2_f3_COEFFICIENT_SIZE,
567 Coef_SZ => f2_f3_COEFFICIENT_SIZE,
567 Coef_Nb => f2_f3_CEL_NUMBER*5,
568 Coef_Nb => f2_f3_CEL_NUMBER*5,
568 Coef_sel_SZ => 5,
569 Coef_sel_SZ => 5,
569 Cels_count => f2_f3_CEL_NUMBER,
570 Cels_count => f2_f3_CEL_NUMBER,
570 ChanelsCount => 6)
571 ChanelsCount => 6)
571 PORT MAP (
572 PORT MAP (
572 rstn => rstn,
573 rstn => rstn,
573 clk => clk,
574 clk => clk,
574 virg_pos => f2_f3_POINT_POSITION,
575 virg_pos => f2_f3_POINT_POSITION,
575 coefs => coefs_iir_cel_f2_f3,
576 coefs => coefs_iir_cel_f2_f3,
576
577
577 sample_in1_val => sample_f2_cic_val,
578 sample_in1_val => sample_f2_cic_val,
578 sample_in1 => sample_f2_cic_filter,
579 sample_in1 => sample_f2_cic_filter,
579
580
580 sample_in2_val => sample_f3_cic_val,
581 sample_in2_val => sample_f3_cic_val,
581 sample_in2 => sample_f3_cic_filter,
582 sample_in2 => sample_f3_cic_filter,
582
583
583 sample_out1_val => sample_f2_filter_val,
584 sample_out1_val => sample_f2_filter_val,
584 sample_out1 => sample_f2_filter,
585 sample_out1 => sample_f2_filter,
585 sample_out2_val => sample_f3_filter_val,
586 sample_out2_val => sample_f3_filter_val,
586 sample_out2 => sample_f3_filter);
587 sample_out2 => sample_f3_filter);
587 END GENERATE YES_IIR_FILTER_f2_f3;
588 END GENERATE YES_IIR_FILTER_f2_f3;
588
589
589 all_channel_sample_f_filter : FOR J IN 5 DOWNTO 0 GENERATE
590 all_channel_sample_f_filter : FOR J IN 5 DOWNTO 0 GENERATE
590 all_bit_sample_f_filter : FOR I IN 15 DOWNTO 0 GENERATE
591 all_bit_sample_f_filter : FOR I IN 15 DOWNTO 0 GENERATE
591 sample_f2_cic_s(J,I) <= sample_f2_filter(J,I);
592 sample_f2_cic_s(J,I) <= sample_f2_filter(J,I);
592 sample_f3_cic_s(J,I) <= sample_f3_filter(J,I);
593 sample_f3_cic_s(J,I) <= sample_f3_filter(J,I);
593 END GENERATE all_bit_sample_f_filter;
594 END GENERATE all_bit_sample_f_filter;
594 END GENERATE all_channel_sample_f_filter;
595 END GENERATE all_channel_sample_f_filter;
595
596
596 -----------------------------------------------------------------------------
597 -----------------------------------------------------------------------------
597
598
598 Downsampling_f2 : Downsampling
599 Downsampling_f2 : Downsampling
599 GENERIC MAP (
600 GENERIC MAP (
600 ChanelCount => 6,
601 ChanelCount => 6,
601 SampleSize => 16,
602 SampleSize => 16,
602 DivideParam => 6)
603 DivideParam => 6)
603 PORT MAP (
604 PORT MAP (
604 clk => clk,
605 clk => clk,
605 rstn => rstn,
606 rstn => rstn,
606 sample_in_val => sample_f2_filter_val ,
607 sample_in_val => sample_f2_filter_val ,
607 sample_in => sample_f2_cic_s,
608 sample_in => sample_f2_cic_s,
608 sample_out_val => sample_f2_val_s,
609 sample_out_val => sample_f2_val_s,
609 sample_out => sample_f2);
610 sample_out => sample_f2);
610
611
611 sample_f2_val <= sample_f2_val_s;
612 sample_f2_val <= sample_f2_val_s;
612
613
613 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
614 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
614 all_channel_sample_f2 : FOR J IN 5 DOWNTO 0 GENERATE
615 all_channel_sample_f2 : FOR J IN 5 DOWNTO 0 GENERATE
615 sample_f2_wdata_s(16*J+I) <= sample_f2(J,I);
616 sample_f2_wdata_s(16*J+I) <= sample_f2(J,I);
616 END GENERATE all_channel_sample_f2;
617 END GENERATE all_channel_sample_f2;
617 END GENERATE all_bit_sample_f2;
618 END GENERATE all_bit_sample_f2;
618
619
619 -----------------------------------------------------------------------------
620 -----------------------------------------------------------------------------
620
621
621 Downsampling_f3 : Downsampling
622 Downsampling_f3 : Downsampling
622 GENERIC MAP (
623 GENERIC MAP (
623 ChanelCount => 6,
624 ChanelCount => 6,
624 SampleSize => 16,
625 SampleSize => 16,
625 DivideParam => 6)
626 DivideParam => 6)
626 PORT MAP (
627 PORT MAP (
627 clk => clk,
628 clk => clk,
628 rstn => rstn,
629 rstn => rstn,
629 sample_in_val => sample_f3_filter_val ,
630 sample_in_val => sample_f3_filter_val ,
630 sample_in => sample_f3_cic_s,
631 sample_in => sample_f3_cic_s,
631 sample_out_val => sample_f3_val_s,
632 sample_out_val => sample_f3_val_s,
632 sample_out => sample_f3);
633 sample_out => sample_f3);
633 sample_f3_val <= sample_f3_val_s;
634 sample_f3_val <= sample_f3_val_s;
634
635
635 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
636 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
636 all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE
637 all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE
637 sample_f3_wdata_s(16*J+I) <= sample_f3(J,I);
638 sample_f3_wdata_s(16*J+I) <= sample_f3(J,I);
638 END GENERATE all_channel_sample_f3;
639 END GENERATE all_channel_sample_f3;
639 END GENERATE all_bit_sample_f3;
640 END GENERATE all_bit_sample_f3;
640
641
641 -----------------------------------------------------------------------------
642 -----------------------------------------------------------------------------
642
643
643 -- TIME --
644 -- TIME --
644 PROCESS (clk, rstn)
645 PROCESS (clk, rstn)
645 BEGIN
646 BEGIN
646 IF rstn = '0' THEN
647 IF rstn = '0' THEN
647 sample_f2_time_reg <= (OTHERS => '0');
648 sample_f2_time_reg <= (OTHERS => '0');
648 sample_f3_time_reg <= (OTHERS => '0');
649 sample_f3_time_reg <= (OTHERS => '0');
649 ELSIF clk'event AND clk = '1' THEN
650 ELSIF clk'event AND clk = '1' THEN
650 IF sample_f2_val_s = '1' THEN sample_f2_time_reg <= sample_f0_time_s; END IF;
651 IF sample_f2_val_s = '1' THEN sample_f2_time_reg <= sample_f0_time_s; END IF;
651 IF sample_f3_val_s = '1' THEN sample_f3_time_reg <= sample_f0_time_s; END IF;
652 IF sample_f3_val_s = '1' THEN sample_f3_time_reg <= sample_f0_time_s; END IF;
652 END IF;
653 END IF;
653 END PROCESS;
654 END PROCESS;
654 sample_f2_time <= sample_f0_time_s WHEN sample_f2_val_s = '1' ELSE sample_f2_time_reg;
655 sample_f2_time <= sample_f0_time_s WHEN sample_f2_val_s = '1' ELSE sample_f2_time_reg;
655 sample_f3_time <= sample_f0_time_s WHEN sample_f3_val_s = '1' ELSE sample_f3_time_reg;
656 sample_f3_time <= sample_f0_time_s WHEN sample_f3_val_s = '1' ELSE sample_f3_time_reg;
656 ----------
657 ----------
657
658
658 -----------------------------------------------------------------------------
659 -----------------------------------------------------------------------------
659 --
660 --
660 -----------------------------------------------------------------------------
661 -----------------------------------------------------------------------------
661 sample_f0_wdata <= sample_f0_wdata_s;
662 sample_f0_wdata <= sample_f0_wdata_s;
662 sample_f1_wdata <= sample_f1_wdata_s;
663 sample_f1_wdata <= sample_f1_wdata_s;
663 sample_f2_wdata <= sample_f2_wdata_s;
664 sample_f2_wdata <= sample_f2_wdata_s;
664 sample_f3_wdata <= sample_f3_wdata_s;
665 sample_f3_wdata <= sample_f3_wdata_s;
665
666
666 END tb;
667 END tb;
Show file before | Show file after | Hide comments
@@ -1,412 +1,413
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_lfr_pkg IS
15 PACKAGE lpp_lfr_pkg IS
16 -----------------------------------------------------------------------------
16 -----------------------------------------------------------------------------
17 -- TEMP
17 -- TEMP
18 -----------------------------------------------------------------------------
18 -----------------------------------------------------------------------------
19 COMPONENT lpp_lfr_ms_test
19 COMPONENT lpp_lfr_ms_test
20 GENERIC (
20 GENERIC (
21 Mem_use : INTEGER);
21 Mem_use : INTEGER);
22 PORT (
22 PORT (
23 clk : IN STD_LOGIC;
23 clk : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
25
25
26 -- TIME
26 -- TIME
27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
29 --
29 --
30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 --
32 --
33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 --
35 --
36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
38
38
39
39
40
40
41 ---------------------------------------------------------------------------
41 ---------------------------------------------------------------------------
42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
43
43
44 --
44 --
45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
49
49
50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
51
51
52 -- IN
52 -- IN
53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
54
54
55 -----------------------------------------------------------------------------
55 -----------------------------------------------------------------------------
56
56
57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
61
61
62 SM_correlation_start : OUT STD_LOGIC;
62 SM_correlation_start : OUT STD_LOGIC;
63 SM_correlation_auto : OUT STD_LOGIC;
63 SM_correlation_auto : OUT STD_LOGIC;
64 SM_correlation_done : IN STD_LOGIC
64 SM_correlation_done : IN STD_LOGIC
65 );
65 );
66 END COMPONENT;
66 END COMPONENT;
67
67
68
68
69 -----------------------------------------------------------------------------
69 -----------------------------------------------------------------------------
70 COMPONENT lpp_lfr_ms
70 COMPONENT lpp_lfr_ms
71 GENERIC (
71 GENERIC (
72 Mem_use : INTEGER;
72 Mem_use : INTEGER;
73 WINDOWS_HAANNING_PARAM_SIZE : INTEGER);
73 WINDOWS_HAANNING_PARAM_SIZE : INTEGER);
74 PORT (
74 PORT (
75 clk : IN STD_LOGIC;
75 clk : IN STD_LOGIC;
76 rstn : IN STD_LOGIC;
76 rstn : IN STD_LOGIC;
77 run : IN STD_LOGIC;
77 run : IN STD_LOGIC;
78 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
78 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
79 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
79 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
80 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
80 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
81 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
81 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
82 sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
82 sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
83 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
83 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
84 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
84 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
85 sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
85 sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
86 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
86 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
87 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
87 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
88 sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
88 sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
89 dma_fifo_burst_valid : OUT STD_LOGIC;
89 dma_fifo_burst_valid : OUT STD_LOGIC;
90 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 dma_fifo_ren : IN STD_LOGIC;
91 dma_fifo_ren : IN STD_LOGIC;
92 dma_buffer_new : OUT STD_LOGIC;
92 dma_buffer_new : OUT STD_LOGIC;
93 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
93 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
94 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
95 dma_buffer_full : IN STD_LOGIC;
95 dma_buffer_full : IN STD_LOGIC;
96 dma_buffer_full_err : IN STD_LOGIC;
96 dma_buffer_full_err : IN STD_LOGIC;
97 ready_matrix_f0 : OUT STD_LOGIC;
97 ready_matrix_f0 : OUT STD_LOGIC;
98 ready_matrix_f1 : OUT STD_LOGIC;
98 ready_matrix_f1 : OUT STD_LOGIC;
99 ready_matrix_f2 : OUT STD_LOGIC;
99 ready_matrix_f2 : OUT STD_LOGIC;
100 error_buffer_full : OUT STD_LOGIC;
100 error_buffer_full : OUT STD_LOGIC;
101 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
101 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
102 status_ready_matrix_f0 : IN STD_LOGIC;
102 status_ready_matrix_f0 : IN STD_LOGIC;
103 status_ready_matrix_f1 : IN STD_LOGIC;
103 status_ready_matrix_f1 : IN STD_LOGIC;
104 status_ready_matrix_f2 : IN STD_LOGIC;
104 status_ready_matrix_f2 : IN STD_LOGIC;
105 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
105 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
106 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
106 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
107 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
107 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
108 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
108 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
109 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
109 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
110 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
110 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
111 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
111 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
112 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
112 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
113 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
113 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
114 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
114 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
115 END COMPONENT;
115 END COMPONENT;
116
116
117 COMPONENT lpp_lfr_ms_fsmdma
117 COMPONENT lpp_lfr_ms_fsmdma
118 PORT (
118 PORT (
119 clk : IN STD_ULOGIC;
119 clk : IN STD_ULOGIC;
120 rstn : IN STD_ULOGIC;
120 rstn : IN STD_ULOGIC;
121 run : IN STD_LOGIC;
121 run : IN STD_LOGIC;
122 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
122 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
123 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
123 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
124 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
124 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
125 fifo_empty : IN STD_LOGIC;
125 fifo_empty : IN STD_LOGIC;
126 fifo_empty_threshold : IN STD_LOGIC;
126 fifo_empty_threshold : IN STD_LOGIC;
127 fifo_ren : OUT STD_LOGIC;
127 fifo_ren : OUT STD_LOGIC;
128 dma_fifo_valid_burst : OUT STD_LOGIC;
128 dma_fifo_valid_burst : OUT STD_LOGIC;
129 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 dma_fifo_ren : IN STD_LOGIC;
130 dma_fifo_ren : IN STD_LOGIC;
131 dma_buffer_new : OUT STD_LOGIC;
131 dma_buffer_new : OUT STD_LOGIC;
132 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
132 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
133 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
133 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
134 dma_buffer_full : IN STD_LOGIC;
134 dma_buffer_full : IN STD_LOGIC;
135 dma_buffer_full_err : IN STD_LOGIC;
135 dma_buffer_full_err : IN STD_LOGIC;
136 status_ready_matrix_f0 : IN STD_LOGIC;
136 status_ready_matrix_f0 : IN STD_LOGIC;
137 status_ready_matrix_f1 : IN STD_LOGIC;
137 status_ready_matrix_f1 : IN STD_LOGIC;
138 status_ready_matrix_f2 : IN STD_LOGIC;
138 status_ready_matrix_f2 : IN STD_LOGIC;
139 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
139 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
140 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
140 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
141 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
141 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
142 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
142 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
143 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
143 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
144 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
144 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
145 ready_matrix_f0 : OUT STD_LOGIC;
145 ready_matrix_f0 : OUT STD_LOGIC;
146 ready_matrix_f1 : OUT STD_LOGIC;
146 ready_matrix_f1 : OUT STD_LOGIC;
147 ready_matrix_f2 : OUT STD_LOGIC;
147 ready_matrix_f2 : OUT STD_LOGIC;
148 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
148 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
149 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
149 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
150 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
150 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
151 error_buffer_full : OUT STD_LOGIC);
151 error_buffer_full : OUT STD_LOGIC);
152 END COMPONENT;
152 END COMPONENT;
153
153
154 COMPONENT lpp_lfr_ms_FFT
154 COMPONENT lpp_lfr_ms_FFT
155 GENERIC (
155 GENERIC (
156 WINDOWS_HAANNING_PARAM_SIZE : INTEGER);
156 WINDOWS_HAANNING_PARAM_SIZE : INTEGER);
157 PORT (
157 PORT (
158 clk : IN STD_LOGIC;
158 clk : IN STD_LOGIC;
159 rstn : IN STD_LOGIC;
159 rstn : IN STD_LOGIC;
160 sample_valid : IN STD_LOGIC;
160 sample_valid : IN STD_LOGIC;
161 fft_read : IN STD_LOGIC;
161 fft_read : IN STD_LOGIC;
162 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
162 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
163 sample_load : OUT STD_LOGIC;
163 sample_load : OUT STD_LOGIC;
164 fft_pong : OUT STD_LOGIC;
164 fft_pong : OUT STD_LOGIC;
165 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
165 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
166 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
166 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
167 fft_data_valid : OUT STD_LOGIC;
167 fft_data_valid : OUT STD_LOGIC;
168 fft_ready : OUT STD_LOGIC);
168 fft_ready : OUT STD_LOGIC);
169 END COMPONENT;
169 END COMPONENT;
170
170
171 COMPONENT lpp_lfr_filter
171 COMPONENT lpp_lfr_filter
172 GENERIC (
172 GENERIC (
173 tech : INTEGER;
173 Mem_use : INTEGER;
174 Mem_use : INTEGER;
174 RTL_DESIGN_LIGHT : INTEGER
175 RTL_DESIGN_LIGHT : INTEGER
175 );
176 );
176 PORT (
177 PORT (
177 sample : IN Samples(7 DOWNTO 0);
178 sample : IN Samples(7 DOWNTO 0);
178 sample_val : IN STD_LOGIC;
179 sample_val : IN STD_LOGIC;
179 sample_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
180 sample_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
180 clk : IN STD_LOGIC;
181 clk : IN STD_LOGIC;
181 rstn : IN STD_LOGIC;
182 rstn : IN STD_LOGIC;
182 data_shaping_SP0 : IN STD_LOGIC;
183 data_shaping_SP0 : IN STD_LOGIC;
183 data_shaping_SP1 : IN STD_LOGIC;
184 data_shaping_SP1 : IN STD_LOGIC;
184 data_shaping_R0 : IN STD_LOGIC;
185 data_shaping_R0 : IN STD_LOGIC;
185 data_shaping_R1 : IN STD_LOGIC;
186 data_shaping_R1 : IN STD_LOGIC;
186 data_shaping_R2 : IN STD_LOGIC;
187 data_shaping_R2 : IN STD_LOGIC;
187 sample_f0_val : OUT STD_LOGIC;
188 sample_f0_val : OUT STD_LOGIC;
188 sample_f1_val : OUT STD_LOGIC;
189 sample_f1_val : OUT STD_LOGIC;
189 sample_f2_val : OUT STD_LOGIC;
190 sample_f2_val : OUT STD_LOGIC;
190 sample_f3_val : OUT STD_LOGIC;
191 sample_f3_val : OUT STD_LOGIC;
191 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
192 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
192 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
193 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
193 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
194 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
194 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
195 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
195 sample_f0_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
196 sample_f0_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
196 sample_f1_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
197 sample_f1_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
197 sample_f2_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
198 sample_f2_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
198 sample_f3_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
199 sample_f3_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
199 );
200 );
200 END COMPONENT;
201 END COMPONENT;
201
202
202 COMPONENT lpp_lfr
203 COMPONENT lpp_lfr
203 GENERIC (
204 GENERIC (
204 Mem_use : INTEGER;
205 Mem_use : INTEGER;
205 tech : INTEGER;
206 tech : INTEGER;
206 nb_data_by_buffer_size : INTEGER;
207 nb_data_by_buffer_size : INTEGER;
207 -- nb_word_by_buffer_size : INTEGER;
208 -- nb_word_by_buffer_size : INTEGER;
208 nb_snapshot_param_size : INTEGER;
209 nb_snapshot_param_size : INTEGER;
209 delta_vector_size : INTEGER;
210 delta_vector_size : INTEGER;
210 delta_vector_size_f0_2 : INTEGER;
211 delta_vector_size_f0_2 : INTEGER;
211 pindex : INTEGER;
212 pindex : INTEGER;
212 paddr : INTEGER;
213 paddr : INTEGER;
213 pmask : INTEGER;
214 pmask : INTEGER;
214 pirq_ms : INTEGER;
215 pirq_ms : INTEGER;
215 pirq_wfp : INTEGER;
216 pirq_wfp : INTEGER;
216 hindex : INTEGER;
217 hindex : INTEGER;
217 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0);
218 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0);
218 DEBUG_FORCE_DATA_DMA : INTEGER;
219 DEBUG_FORCE_DATA_DMA : INTEGER;
219 RTL_DESIGN_LIGHT : INTEGER;
220 RTL_DESIGN_LIGHT : INTEGER;
220 WINDOWS_HAANNING_PARAM_SIZE : INTEGER
221 WINDOWS_HAANNING_PARAM_SIZE : INTEGER
221 );
222 );
222 PORT (
223 PORT (
223 clk : IN STD_LOGIC;
224 clk : IN STD_LOGIC;
224 rstn : IN STD_LOGIC;
225 rstn : IN STD_LOGIC;
225 sample_B : IN Samples(2 DOWNTO 0);
226 sample_B : IN Samples(2 DOWNTO 0);
226 sample_E : IN Samples(4 DOWNTO 0);
227 sample_E : IN Samples(4 DOWNTO 0);
227 sample_val : IN STD_LOGIC;
228 sample_val : IN STD_LOGIC;
228 apbi : IN apb_slv_in_type;
229 apbi : IN apb_slv_in_type;
229 apbo : OUT apb_slv_out_type;
230 apbo : OUT apb_slv_out_type;
230 ahbi : IN AHB_Mst_In_Type;
231 ahbi : IN AHB_Mst_In_Type;
231 ahbo : OUT AHB_Mst_Out_Type;
232 ahbo : OUT AHB_Mst_Out_Type;
232 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
233 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
233 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
234 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
234 data_shaping_BW : OUT STD_LOGIC;
235 data_shaping_BW : OUT STD_LOGIC;
235 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
236 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
236 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
237 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
237 );
238 );
238 END COMPONENT;
239 END COMPONENT;
239
240
240 -----------------------------------------------------------------------------
241 -----------------------------------------------------------------------------
241 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
242 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
242 -----------------------------------------------------------------------------
243 -----------------------------------------------------------------------------
243 COMPONENT lpp_lfr_WFP_nMS
244 COMPONENT lpp_lfr_WFP_nMS
244 GENERIC (
245 GENERIC (
245 Mem_use : INTEGER;
246 Mem_use : INTEGER;
246 nb_data_by_buffer_size : INTEGER;
247 nb_data_by_buffer_size : INTEGER;
247 nb_word_by_buffer_size : INTEGER;
248 nb_word_by_buffer_size : INTEGER;
248 nb_snapshot_param_size : INTEGER;
249 nb_snapshot_param_size : INTEGER;
249 delta_vector_size : INTEGER;
250 delta_vector_size : INTEGER;
250 delta_vector_size_f0_2 : INTEGER;
251 delta_vector_size_f0_2 : INTEGER;
251 pindex : INTEGER;
252 pindex : INTEGER;
252 paddr : INTEGER;
253 paddr : INTEGER;
253 pmask : INTEGER;
254 pmask : INTEGER;
254 pirq_ms : INTEGER;
255 pirq_ms : INTEGER;
255 pirq_wfp : INTEGER;
256 pirq_wfp : INTEGER;
256 hindex : INTEGER;
257 hindex : INTEGER;
257 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
258 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
258 PORT (
259 PORT (
259 clk : IN STD_LOGIC;
260 clk : IN STD_LOGIC;
260 rstn : IN STD_LOGIC;
261 rstn : IN STD_LOGIC;
261 sample_B : IN Samples(2 DOWNTO 0);
262 sample_B : IN Samples(2 DOWNTO 0);
262 sample_E : IN Samples(4 DOWNTO 0);
263 sample_E : IN Samples(4 DOWNTO 0);
263 sample_val : IN STD_LOGIC;
264 sample_val : IN STD_LOGIC;
264 apbi : IN apb_slv_in_type;
265 apbi : IN apb_slv_in_type;
265 apbo : OUT apb_slv_out_type;
266 apbo : OUT apb_slv_out_type;
266 ahbi : IN AHB_Mst_In_Type;
267 ahbi : IN AHB_Mst_In_Type;
267 ahbo : OUT AHB_Mst_Out_Type;
268 ahbo : OUT AHB_Mst_Out_Type;
268 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
269 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
269 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
270 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
270 data_shaping_BW : OUT STD_LOGIC;
271 data_shaping_BW : OUT STD_LOGIC;
271 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
272 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
272 END COMPONENT;
273 END COMPONENT;
273 -----------------------------------------------------------------------------
274 -----------------------------------------------------------------------------
274
275
275 COMPONENT lpp_lfr_apbreg
276 COMPONENT lpp_lfr_apbreg
276 GENERIC (
277 GENERIC (
277 nb_data_by_buffer_size : INTEGER;
278 nb_data_by_buffer_size : INTEGER;
278 nb_snapshot_param_size : INTEGER;
279 nb_snapshot_param_size : INTEGER;
279 delta_vector_size : INTEGER;
280 delta_vector_size : INTEGER;
280 delta_vector_size_f0_2 : INTEGER;
281 delta_vector_size_f0_2 : INTEGER;
281 pindex : INTEGER;
282 pindex : INTEGER;
282 paddr : INTEGER;
283 paddr : INTEGER;
283 pmask : INTEGER;
284 pmask : INTEGER;
284 pirq_ms : INTEGER;
285 pirq_ms : INTEGER;
285 pirq_wfp : INTEGER;
286 pirq_wfp : INTEGER;
286 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
287 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
287 PORT (
288 PORT (
288 HCLK : IN STD_ULOGIC;
289 HCLK : IN STD_ULOGIC;
289 HRESETn : IN STD_ULOGIC;
290 HRESETn : IN STD_ULOGIC;
290 apbi : IN apb_slv_in_type;
291 apbi : IN apb_slv_in_type;
291 apbo : OUT apb_slv_out_type;
292 apbo : OUT apb_slv_out_type;
292 -- run_ms : OUT STD_LOGIC;
293 -- run_ms : OUT STD_LOGIC;
293 ready_matrix_f0 : IN STD_LOGIC;
294 ready_matrix_f0 : IN STD_LOGIC;
294 ready_matrix_f1 : IN STD_LOGIC;
295 ready_matrix_f1 : IN STD_LOGIC;
295 ready_matrix_f2 : IN STD_LOGIC;
296 ready_matrix_f2 : IN STD_LOGIC;
296 error_buffer_full : IN STD_LOGIC;
297 error_buffer_full : IN STD_LOGIC;
297 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
298 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
298 status_ready_matrix_f0 : OUT STD_LOGIC;
299 status_ready_matrix_f0 : OUT STD_LOGIC;
299 status_ready_matrix_f1 : OUT STD_LOGIC;
300 status_ready_matrix_f1 : OUT STD_LOGIC;
300 status_ready_matrix_f2 : OUT STD_LOGIC;
301 status_ready_matrix_f2 : OUT STD_LOGIC;
301 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
302 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
302 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
303 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
303 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
304 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
304 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
305 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
305 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
306 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
306 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
307 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
307 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
308 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
308 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
309 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
309 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
310 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
310 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
311 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
311 data_shaping_BW : OUT STD_LOGIC;
312 data_shaping_BW : OUT STD_LOGIC;
312 data_shaping_SP0 : OUT STD_LOGIC;
313 data_shaping_SP0 : OUT STD_LOGIC;
313 data_shaping_SP1 : OUT STD_LOGIC;
314 data_shaping_SP1 : OUT STD_LOGIC;
314 data_shaping_R0 : OUT STD_LOGIC;
315 data_shaping_R0 : OUT STD_LOGIC;
315 data_shaping_R1 : OUT STD_LOGIC;
316 data_shaping_R1 : OUT STD_LOGIC;
316 data_shaping_R2 : OUT STD_LOGIC;
317 data_shaping_R2 : OUT STD_LOGIC;
317 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
318 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
318 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
319 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
319 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
320 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
320 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
321 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
321 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
322 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
322 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
323 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
323 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
324 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
324 enable_f0 : OUT STD_LOGIC;
325 enable_f0 : OUT STD_LOGIC;
325 enable_f1 : OUT STD_LOGIC;
326 enable_f1 : OUT STD_LOGIC;
326 enable_f2 : OUT STD_LOGIC;
327 enable_f2 : OUT STD_LOGIC;
327 enable_f3 : OUT STD_LOGIC;
328 enable_f3 : OUT STD_LOGIC;
328 burst_f0 : OUT STD_LOGIC;
329 burst_f0 : OUT STD_LOGIC;
329 burst_f1 : OUT STD_LOGIC;
330 burst_f1 : OUT STD_LOGIC;
330 burst_f2 : OUT STD_LOGIC;
331 burst_f2 : OUT STD_LOGIC;
331 run : OUT STD_LOGIC;
332 run : OUT STD_LOGIC;
332 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
333 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
333 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
334 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
334 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
335 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
335 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
336 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
336 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
337 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
337 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
338 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
338 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
339 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
339 sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
340 sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
340 sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
341 sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
341 sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
342 sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
342 sample_f3_valid : IN STD_LOGIC;
343 sample_f3_valid : IN STD_LOGIC;
343 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
344 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
344 END COMPONENT;
345 END COMPONENT;
345
346
346 COMPONENT lpp_top_ms
347 COMPONENT lpp_top_ms
347 GENERIC (
348 GENERIC (
348 Mem_use : INTEGER;
349 Mem_use : INTEGER;
349 nb_burst_available_size : INTEGER;
350 nb_burst_available_size : INTEGER;
350 nb_snapshot_param_size : INTEGER;
351 nb_snapshot_param_size : INTEGER;
351 delta_snapshot_size : INTEGER;
352 delta_snapshot_size : INTEGER;
352 delta_f2_f0_size : INTEGER;
353 delta_f2_f0_size : INTEGER;
353 delta_f2_f1_size : INTEGER;
354 delta_f2_f1_size : INTEGER;
354 pindex : INTEGER;
355 pindex : INTEGER;
355 paddr : INTEGER;
356 paddr : INTEGER;
356 pmask : INTEGER;
357 pmask : INTEGER;
357 pirq_ms : INTEGER;
358 pirq_ms : INTEGER;
358 pirq_wfp : INTEGER;
359 pirq_wfp : INTEGER;
359 hindex_wfp : INTEGER;
360 hindex_wfp : INTEGER;
360 hindex_ms : INTEGER);
361 hindex_ms : INTEGER);
361 PORT (
362 PORT (
362 clk : IN STD_LOGIC;
363 clk : IN STD_LOGIC;
363 rstn : IN STD_LOGIC;
364 rstn : IN STD_LOGIC;
364 sample_B : IN Samples14v(2 DOWNTO 0);
365 sample_B : IN Samples14v(2 DOWNTO 0);
365 sample_E : IN Samples14v(4 DOWNTO 0);
366 sample_E : IN Samples14v(4 DOWNTO 0);
366 sample_val : IN STD_LOGIC;
367 sample_val : IN STD_LOGIC;
367 apbi : IN apb_slv_in_type;
368 apbi : IN apb_slv_in_type;
368 apbo : OUT apb_slv_out_type;
369 apbo : OUT apb_slv_out_type;
369 ahbi_ms : IN AHB_Mst_In_Type;
370 ahbi_ms : IN AHB_Mst_In_Type;
370 ahbo_ms : OUT AHB_Mst_Out_Type;
371 ahbo_ms : OUT AHB_Mst_Out_Type;
371 data_shaping_BW : OUT STD_LOGIC;
372 data_shaping_BW : OUT STD_LOGIC;
372 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
373 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
373 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
374 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
374 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
375 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
375 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
376 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
376 );
377 );
377 END COMPONENT;
378 END COMPONENT;
378
379
379 COMPONENT lpp_apbreg_ms_pointer
380 COMPONENT lpp_apbreg_ms_pointer
380 PORT (
381 PORT (
381 clk : IN STD_LOGIC;
382 clk : IN STD_LOGIC;
382 rstn : IN STD_LOGIC;
383 rstn : IN STD_LOGIC;
383 run : IN STD_LOGIC;
384 run : IN STD_LOGIC;
384 reg0_status_ready_matrix : IN STD_LOGIC;
385 reg0_status_ready_matrix : IN STD_LOGIC;
385 reg0_ready_matrix : OUT STD_LOGIC;
386 reg0_ready_matrix : OUT STD_LOGIC;
386 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
387 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
387 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
388 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
388 reg1_status_ready_matrix : IN STD_LOGIC;
389 reg1_status_ready_matrix : IN STD_LOGIC;
389 reg1_ready_matrix : OUT STD_LOGIC;
390 reg1_ready_matrix : OUT STD_LOGIC;
390 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
391 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
391 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
392 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
392 ready_matrix : IN STD_LOGIC;
393 ready_matrix : IN STD_LOGIC;
393 status_ready_matrix : OUT STD_LOGIC;
394 status_ready_matrix : OUT STD_LOGIC;
394 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
395 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
395 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
396 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
396 END COMPONENT;
397 END COMPONENT;
397
398
398 COMPONENT lpp_lfr_ms_reg_head
399 COMPONENT lpp_lfr_ms_reg_head
399 PORT (
400 PORT (
400 clk : IN STD_LOGIC;
401 clk : IN STD_LOGIC;
401 rstn : IN STD_LOGIC;
402 rstn : IN STD_LOGIC;
402 in_wen : IN STD_LOGIC;
403 in_wen : IN STD_LOGIC;
403 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
404 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
404 in_full : IN STD_LOGIC;
405 in_full : IN STD_LOGIC;
405 in_empty : IN STD_LOGIC;
406 in_empty : IN STD_LOGIC;
406 out_write_error : OUT STD_LOGIC;
407 out_write_error : OUT STD_LOGIC;
407 out_wen : OUT STD_LOGIC;
408 out_wen : OUT STD_LOGIC;
408 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
409 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
409 out_full : OUT STD_LOGIC);
410 out_full : OUT STD_LOGIC);
410 END COMPONENT;
411 END COMPONENT;
411
412
412 END lpp_lfr_pkg;
413 END lpp_lfr_pkg;
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