diff --git a/designs/Validation_IIR_f0_LFR/Makefile b/designs/Validation_IIR_f0_LFR/Makefile new file mode 100644 --- /dev/null +++ b/designs/Validation_IIR_f0_LFR/Makefile @@ -0,0 +1,56 @@ +#GRLIB=../.. +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=testbench +BOARD=LFR-EQM +include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf +QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf +EFFORT=high +XSTOPT= +SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" +#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd +VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd +VHDLSIMFILES= tb.vhd +SIMTOP=testbench +#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc +PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc +SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc +BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut +CLEAN=soft-clean + +TECHLIBS = axcelerator + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc opencores + +DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./lfr_management \ + ./lpp_sim \ + ./lpp_sim/CY7C1061DV33 \ + ./lpp_cna \ + ./lpp_uart \ + ./lpp_usb \ + ./dsp/lpp_fft \ + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_MULTI_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd \ + lpp_lfr_apbreg.vhd \ + CoreFFT.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + diff --git a/designs/Validation_IIR_f0_LFR/generator.vhd b/designs/Validation_IIR_f0_LFR/generator.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_IIR_f0_LFR/generator.vhd @@ -0,0 +1,74 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +---------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +use ieee.numeric_std.all; +USE IEEE.std_logic_signed.ALL; +USE IEEE.MATH_real.ALL; + +ENTITY generator IS + + GENERIC ( + AMPLITUDE : INTEGER := 100; + NB_BITS : INTEGER := 16); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + + data_ack : IN STD_LOGIC; + offset : IN STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0); + data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0) + ); + +END generator; + +ARCHITECTURE beh OF generator IS + + SIGNAL reg : STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0); +BEGIN -- beh + + + PROCESS (clk, rstn) + variable seed1, seed2: positive; -- seed values for random generator + variable rand: real; -- random real-number value in range 0 to 1.0 + BEGIN -- PROCESS + uniform(seed1, seed2, rand);--more entropy by skipping values + IF rstn = '0' THEN -- asynchronous reset (active low) + reg <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF run = '0' THEN + reg <= (OTHERS => '0'); + ELSE + IF data_ack = '1' THEN + reg <= std_logic_vector(to_signed(INTEGER( (REAL(AMPLITUDE) * rand) + REAL(to_integer(SIGNED(offset))) ),NB_BITS)); + END IF; + END IF; + END IF; + END PROCESS; + + data <= reg; + +END beh; diff --git a/designs/Validation_IIR_f0_LFR/tb.vhd b/designs/Validation_IIR_f0_LFR/tb.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_IIR_f0_LFR/tb.vhd @@ -0,0 +1,227 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +USE IEEE.std_logic_signed.ALL; +USE IEEE.MATH_real.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY std; +USE std.textio.ALL; + +LIBRARY lpp; +USE lpp.iir_filter.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_lfr_filter_coeff.ALL; +USE lpp.general_purpose.ALL; +USE lpp.data_type_pkg.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.general_purpose.ALL; + +ENTITY testbench IS +END; + +ARCHITECTURE behav OF testbench IS + CONSTANT ChanelCount : INTEGER := 8; + CONSTANT Coef_SZ : INTEGER := 9; + CONSTANT CoefCntPerCel : INTEGER := 6; + CONSTANT CoefPerCel : INTEGER := 5; + CONSTANT Cels_count : INTEGER := 5; + + SIGNAL sample : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + + SIGNAL sample_fx : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_fx_val : STD_LOGIC; + + + + + + + SIGNAL TSTAMP : INTEGER := 0; + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL clk_24k : STD_LOGIC := '0'; + SIGNAL clk_24k_r : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC; + + SIGNAL signal_gen : Samples(7 DOWNTO 0); + SIGNAL offset_gen : Samples(7 DOWNTO 0); + + --SIGNAL sample_fx_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + + SIGNAL sample_fx_wdata : Samples(ChanelCount-1 DOWNTO 0); + + + COMPONENT generator IS + GENERIC ( + AMPLITUDE : INTEGER := 100; + NB_BITS : INTEGER := 16); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + + data_ack : IN STD_LOGIC; + offset : IN STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0); + data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0) + ); + END COMPONENT; + + + FILE log_input : TEXT OPEN write_mode IS "log_input.txt"; + FILE log_output_fx : TEXT OPEN write_mode IS "log_output_fx.txt"; + + SIGNAL end_of_simu : STD_LOGIC := '0'; + +BEGIN + + ----------------------------------------------------------------------------- + -- CLOCK and RESET + ----------------------------------------------------------------------------- + clk <= NOT clk AFTER 5 ns; + PROCESS + BEGIN -- PROCESS + end_of_simu <= '0'; + WAIT UNTIL clk = '1'; + rstn <= '0'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + rstn <= '1'; + WAIT FOR 2000 ms; + end_of_simu <= '1'; + WAIT UNTIL clk = '1'; + REPORT "*** END simulation ***" SEVERITY failure; + WAIT; + END PROCESS; + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- COMMON TIMESTAMPS + ----------------------------------------------------------------------------- + + PROCESS(clk) + BEGIN + IF clk'EVENT AND clk = '1' THEN + TSTAMP <= TSTAMP+1; + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- LPP_LFR_FILTER f0 + ----------------------------------------------------------------------------- + + IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 + GENERIC MAP ( + tech => axcel, + Mem_use => use_RAM, + Sample_SZ => 18, + Coef_SZ => Coef_SZ, + Coef_Nb => 25, + Coef_sel_SZ => 5, + Cels_count => Cels_count, + ChanelsCount => ChanelCount) + PORT MAP ( + rstn => rstn, + clk => clk, + virg_pos => 7, + coefs => CoefsInitValCst_v2, + + sample_in_val => sample_val, + sample_in => sample, + sample_out_val => sample_fx_val, + sample_out => sample_fx); + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- SAMPLE GENERATION + ----------------------------------------------------------------------------- + clk_24k <= NOT clk_24k AFTER 20345 ns; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_val <= '0'; + clk_24k_r <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + clk_24k_r <= clk_24k; + IF clk_24k = '1' AND clk_24k_r = '0' THEN + sample_val <= '1'; + ELSE + sample_val <= '0'; + END IF; + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + generators : FOR I IN 0 TO 7 GENERATE + gen1 : generator + GENERIC MAP ( + AMPLITUDE => 100, + NB_BITS => 16) + PORT MAP ( + clk => clk, + rstn => rstn, + run => '1', + data_ack => sample_val, + offset => offset_gen(I), + data => signal_gen(I) + ); + offset_gen(I) <= STD_LOGIC_VECTOR(to_signed((I*200), 16)); + END GENERATE generators; + + ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE + SampleLoop : FOR j IN 0 TO 15 GENERATE + sample(i,j) <= signal_gen(i)(j); + sample_fx_wdata(i)(j) <= sample_fx(i,j); + END GENERATE; + + sample(i, 16) <= signal_gen(i)(15); + sample(i, 17) <= signal_gen(i)(15); + END GENERATE; + + + + ----------------------------------------------------------------------------- + -- RECORD SIGNALS + ----------------------------------------------------------------------------- + + -- PROCESS(sample_val) + -- VARIABLE line_var : LINE; + -- BEGIN + -- IF sample_val'EVENT AND sample_val = '1' THEN + -- write(line_var, INTEGER'IMAGE(TSTAMP)); + -- FOR I IN 0 TO 7 LOOP + -- write(line_var, " " & INTEGER'IMAGE(to_integer(SIGNED(signal_gen(I))))); + -- END LOOP; + -- writeline(log_input, line_var); + -- END IF; + -- END PROCESS; + + PROCESS(sample_fx_val,end_of_simu) + VARIABLE line_var : LINE; + BEGIN + IF sample_fx_val'EVENT AND sample_fx_val = '1' THEN + write(line_var, INTEGER'IMAGE(TSTAMP)); + FOR I IN 0 TO 5 LOOP + write(line_var, " " & INTEGER'IMAGE(to_integer(SIGNED(sample_fx_wdata(I))))); + END LOOP; + writeline(log_output_fx, line_var); + END IF; + IF end_of_simu = '1' THEN + file_close(log_output_fx); + END IF; + END PROCESS; + + + + +END; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -190,6 +190,7 @@ BEGIN ----------------------------------------------------------------------------- lpp_lfr_filter_1 : lpp_lfr_filter GENERIC MAP ( + tech => tech, Mem_use => Mem_use, RTL_DESIGN_LIGHT => RTL_DESIGN_LIGHT) PORT MAP ( diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd @@ -45,6 +45,7 @@ USE GRLIB.DMA2AHB_Package.ALL; ENTITY lpp_lfr_filter IS GENERIC( + tech : INTEGER := 0; Mem_use : INTEGER := use_RAM; RTL_DESIGN_LIGHT : INTEGER := 0 ); @@ -263,7 +264,7 @@ BEGIN IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 GENERIC MAP ( - tech => 0, + tech => tech, Mem_use => Mem_use, -- use_RAM Sample_SZ => 18, Coef_SZ => Coef_SZ, @@ -443,7 +444,7 @@ BEGIN IIR_CEL_f0_to_f1 : IIR_CEL_CTRLR_v2 GENERIC MAP ( - tech => 0, + tech => tech, Mem_use => Mem_use, -- use_RAM Sample_SZ => 18, Coef_SZ => f0_to_f1_COEFFICIENT_SIZE, @@ -518,7 +519,7 @@ BEGIN cic_lfr_1: cic_lfr_r2 GENERIC MAP ( - tech => 0, + tech => tech, use_RAM_nCEL => Mem_use) PORT MAP ( clk => clk, @@ -560,7 +561,7 @@ BEGIN YES_IIR_FILTER_f2_f3: IF RTL_DESIGN_LIGHT = 0 GENERATE IIR_CEL_CTRLR_v3_1:IIR_CEL_CTRLR_v3 GENERIC MAP ( - tech => 0, + tech => tech, Mem_use => Mem_use, Sample_SZ => 18, Coef_SZ => f2_f3_COEFFICIENT_SIZE, diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd @@ -170,6 +170,7 @@ PACKAGE lpp_lfr_pkg IS COMPONENT lpp_lfr_filter GENERIC ( + tech : INTEGER; Mem_use : INTEGER; RTL_DESIGN_LIGHT : INTEGER );