HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Files · boards/LeonLPP-A3PE3kL/Makefile.inc

EM Design : GRSPW 2 ports, WFP, FILTER, BW/SP/R OK...

EM Design : GRSPW 2 ports, WFP, FILTER, BW/SP/R OK (Redmine : 2013-07-22-leon3mp-grspw-wfrm.pdb)

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             Makefile.inc
        
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        martin
    
Mise a jour Projets blanc

              r100
            
      TECHNOLOGY=PROASIC3

      PACKAGE=\"\"

      SPEED=Std

      SYNFREQ=50

      PART=A3PE3000L

      DESIGNER_PACKAGE=FBGA

      DESIGNER_PINS=324

      DESIGNER_VOLTAGE=COM

      DESIGNER_TEMP=COM

      MANUFACTURER=Actel

      MGCPART=$(PART)

      MGCTECHNOLOGY=PROASIC3

      MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}

      LIBERO_DIE=IT14X14M4LDP

      LIBERO_PACKAGE=fg$(DESIGNER_PINS)

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martin Mise a jour Projets blanc	r100	TECHNOLOGY=PROASIC3
		PACKAGE=\"\"
		SPEED=Std
		SYNFREQ=50

		PART=A3PE3000L
		DESIGNER_PACKAGE=FBGA
		DESIGNER_PINS=324
		DESIGNER_VOLTAGE=COM
		DESIGNER_TEMP=COM

		MANUFACTURER=Actel
		MGCPART=$(PART)
		MGCTECHNOLOGY=PROASIC3
		MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
		LIBERO_DIE=IT14X14M4LDP
		LIBERO_PACKAGE=fg$(DESIGNER_PINS)