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EM Design : GRSPW 2 ports, WFP, FILTER, BW/SP/R OK...
pellion -
r201:afe160da7247 JC
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1 PACKAGE=\"\"
2 SPEED=Std
3 SYNFREQ=50
4
5 TECHNOLOGY=ProASIC3E
6 LIBERO_DIE=IT14X14M4
7 PART=A3PE3000
8
9 DESIGNER_VOLTAGE=COM
10 DESIGNER_TEMP=COM
11 DESIGNER_PACKAGE=FBGA
12 DESIGNER_PINS=324
13
14 MANUFACTURER=Actel
15 MGCTECHNOLOGY=Proasic3
16 MGCPART=$(PART)
17 MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
18 LIBERO_PACKAGE=fg$(DESIGNER_PINS)
19
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1 # Synplicity, Inc. constraint file
2 # /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc
3 # Written on Wed Aug 1 19:29:24 2007
4 # by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor
5
6 #
7 # Collections
8 #
9
10 #
11 # Clocks
12 #
13 define_clock {clk} -name {clk} -freq 60 -clockgroup default_clkgroup -route 5
14
15 #
16 # Clock to Clock
17 #
18
19 #
20 # Inputs/Outputs
21 #
22 define_output_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r}
23 define_input_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r}
24
25
26 #
27 # Registers
28 #
29
30 #
31 # Multicycle Path
32 #
33
34 #
35 # False Path
36 #
37
38 #
39 # Path Delay
40 #
41
42 #
43 # Attributes
44 #
45 define_global_attribute syn_useioff {1}
46 define_global_attribute -disable syn_netlist_hierarchy {0}
47 define_attribute {etx_clk} syn_noclockbuf {1}
48
49 #
50 # I/O standards
51 #
52
53 #
54 # Compile Points
55 #
56
57 #
58 # Other Constraints
59 #
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1 set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout
2 set_io clk100MHz -pinname B3 -fixed yes -DIRECTION Inout
3 set_io reset -pinname N18 -fixed yes -DIRECTION Inout
4
5 set_io {address[0]} -pinname H16 -fixed yes -DIRECTION Inout
6 set_io {address[1]} -pinname J15 -fixed yes -DIRECTION Inout
7 set_io {address[2]} -pinname B18 -fixed yes -DIRECTION Inout
8 set_io {address[3]} -pinname C17 -fixed yes -DIRECTION Inout
9 set_io {address[4]} -pinname C18 -fixed yes -DIRECTION Inout
10 set_io {address[5]} -pinname U2 -fixed yes -DIRECTION Inout
11 set_io {address[6]} -pinname U3 -fixed yes -DIRECTION Inout
12 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
13 set_io {address[8]} -pinname N11 -fixed yes -DIRECTION Inout
14 set_io {address[9]} -pinname R13 -fixed yes -DIRECTION Inout
15 set_io {address[10]} -pinname V13 -fixed yes -DIRECTION Inout
16 set_io {address[11]} -pinname U13 -fixed yes -DIRECTION Inout
17 set_io {address[12]} -pinname V15 -fixed yes -DIRECTION Inout
18 set_io {address[13]} -pinname V16 -fixed yes -DIRECTION Inout
19 set_io {address[14]} -pinname V17 -fixed yes -DIRECTION Inout
20 set_io {address[15]} -pinname N1 -fixed yes -DIRECTION Inout
21 set_io {address[16]} -pinname R3 -fixed yes -DIRECTION Inout
22 set_io {address[17]} -pinname P4 -fixed yes -DIRECTION Inout
23 set_io {address[18]} -pinname N3 -fixed yes -DIRECTION Inout
24 set_io {address[19]} -pinname M7 -fixed yes -DIRECTION Inout
25
26 set_io {data[0]} -pinname P17 -fixed yes -DIRECTION Inout
27 set_io {data[1]} -pinname R18 -fixed yes -DIRECTION Inout
28 set_io {data[2]} -pinname T18 -fixed yes -DIRECTION Inout
29 set_io {data[3]} -pinname J13 -fixed yes -DIRECTION Inout
30 set_io {data[4]} -pinname T13 -fixed yes -DIRECTION Inout
31 set_io {data[5]} -pinname T12 -fixed yes -DIRECTION Inout
32 set_io {data[6]} -pinname R12 -fixed yes -DIRECTION Inout
33 set_io {data[7]} -pinname T11 -fixed yes -DIRECTION Inout
34 set_io {data[8]} -pinname N2 -fixed yes -DIRECTION Inout
35 set_io {data[9]} -pinname P1 -fixed yes -DIRECTION Inout
36 set_io {data[10]} -pinname R1 -fixed yes -DIRECTION Inout
37 set_io {data[11]} -pinname T1 -fixed yes -DIRECTION Inout
38 set_io {data[12]} -pinname M4 -fixed yes -DIRECTION Inout
39 set_io {data[13]} -pinname K1 -fixed yes -DIRECTION Inout
40 set_io {data[14]} -pinname J1 -fixed yes -DIRECTION Inout
41 set_io {data[15]} -pinname H1 -fixed yes -DIRECTION Inout
42 set_io {data[16]} -pinname H15 -fixed yes -DIRECTION Inout
43 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
44 set_io {data[18]} -pinname H13 -fixed yes -DIRECTION Inout
45 set_io {data[19]} -pinname G12 -fixed yes -DIRECTION Inout
46 set_io {data[20]} -pinname V14 -fixed yes -DIRECTION Inout
47 set_io {data[21]} -pinname N9 -fixed yes -DIRECTION Inout
48 set_io {data[22]} -pinname M13 -fixed yes -DIRECTION Inout
49 set_io {data[23]} -pinname M15 -fixed yes -DIRECTION Inout
50 set_io {data[24]} -pinname J17 -fixed yes -DIRECTION Inout
51 set_io {data[25]} -pinname K15 -fixed yes -DIRECTION Inout
52 set_io {data[26]} -pinname J14 -fixed yes -DIRECTION Inout
53 set_io {data[27]} -pinname U18 -fixed yes -DIRECTION Inout
54 set_io {data[28]} -pinname H18 -fixed yes -DIRECTION Inout
55 set_io {data[29]} -pinname J18 -fixed yes -DIRECTION Inout
56 set_io {data[30]} -pinname G17 -fixed yes -DIRECTION Inout
57 set_io {data[31]} -pinname F18 -fixed yes -DIRECTION Inout
58
59 set_io nSRAM_BE0 -pinname U12 -fixed yes -DIRECTION Inout
60 set_io nSRAM_BE1 -pinname K18 -fixed yes -DIRECTION Inout
61 set_io nSRAM_BE2 -pinname K12 -fixed yes -DIRECTION Inout
62 set_io nSRAM_BE3 -pinname F17 -fixed yes -DIRECTION Inout
63 set_io nSRAM_WE -pinname D18 -fixed yes -DIRECTION Inout
64 set_io nSRAM_CE -pinname M6 -fixed yes -DIRECTION Inout
65 set_io nSRAM_OE -pinname N12 -fixed yes -DIRECTION Inout
66
67 set_io spw1_din -pinname D6 -fixed yes -DIRECTION Inout
68 set_io spw1_sin -pinname C6 -fixed yes -DIRECTION Inout
69 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
71
72 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
73 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
74 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
75 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
76
77 set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout
78 set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout
79 set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout
80
81 set_io ahbtxd -pinname J12 -fixed yes -DIRECTION Inout
82 #set_io TAG2 -pinname K13 -fixed yes -DIRECTION Inout
83 set_io ahbrxd -pinname L16 -fixed yes -DIRECTION Inout
84 #set_io TAG4 -pinname L15 -fixed yes -DIRECTION Inout
85 set_io urxd1 -pinname M16 -fixed yes -DIRECTION Inout
86 set_io utxd1 -pinname L13 -fixed yes -DIRECTION Inout
87 set_io errorn -pinname P6 -fixed yes -DIRECTION Inout
88 #set_io TAG8 -pinname R6 -fixed yes -DIRECTION Inout
89 #set_io TAG9 -pinname T4 -fixed yes -DIRECTION Inout
90
91 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
92
93 set_io {ADC_OEB_bar_CH[0]} -pinname A13 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[1]} -pinname A14 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[2]} -pinname A10 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[3]} -pinname B10 -fixed yes -DIRECTION Inout
97 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
98 set_io {ADC_OEB_bar_CH[5]} -pinname D13 -fixed yes -DIRECTION Inout
99 set_io {ADC_OEB_bar_CH[6]} -pinname A11 -fixed yes -DIRECTION Inout
100 set_io {ADC_OEB_bar_CH[7]} -pinname B12 -fixed yes -DIRECTION Inout
101
102 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
103
104 set_io {ADC_data[0]} -pinname A16 -fixed yes -DIRECTION Inout
105 set_io {ADC_data[1]} -pinname B16 -fixed yes -DIRECTION Inout
106 set_io {ADC_data[2]} -pinname A17 -fixed yes -DIRECTION Inout
107 set_io {ADC_data[3]} -pinname C12 -fixed yes -DIRECTION Inout
108 set_io {ADC_data[4]} -pinname B17 -fixed yes -DIRECTION Inout
109 set_io {ADC_data[5]} -pinname C13 -fixed yes -DIRECTION Inout
110 set_io {ADC_data[6]} -pinname D15 -fixed yes -DIRECTION Inout
111 set_io {ADC_data[7]} -pinname E15 -fixed yes -DIRECTION Inout
112 set_io {ADC_data[8]} -pinname D16 -fixed yes -DIRECTION Inout
113 set_io {ADC_data[9]} -pinname F16 -fixed yes -DIRECTION Inout
114 set_io {ADC_data[10]} -pinname F15 -fixed yes -DIRECTION Inout
115 set_io {ADC_data[11]} -pinname G16 -fixed yes -DIRECTION Inout
116 set_io {ADC_data[12]} -pinname F13 -fixed yes -DIRECTION Inout
117 set_io {ADC_data[13]} -pinname G13 -fixed yes -DIRECTION Inout
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1 #
2 # Automatically generated make config: don't edit
3 #
4
5 #
6 # Synthesis
7 #
8 # CONFIG_SYN_INFERRED is not set
9 # CONFIG_SYN_STRATIX is not set
10 # CONFIG_SYN_STRATIXII is not set
11 # CONFIG_SYN_STRATIXIII is not set
12 # CONFIG_SYN_CYCLONEIII is not set
13 # CONFIG_SYN_ALTERA is not set
14 # CONFIG_SYN_AXCEL is not set
15 # CONFIG_SYN_PROASIC is not set
16 # CONFIG_SYN_PROASICPLUS is not set
17 CONFIG_SYN_PROASIC3=y
18 # CONFIG_SYN_UT025CRH is not set
19 # CONFIG_SYN_ATC18 is not set
20 # CONFIG_SYN_ATC18RHA is not set
21 # CONFIG_SYN_CUSTOM1 is not set
22 # CONFIG_SYN_EASIC90 is not set
23 # CONFIG_SYN_IHP25 is not set
24 # CONFIG_SYN_IHP25RH is not set
25 # CONFIG_SYN_LATTICE is not set
26 # CONFIG_SYN_ECLIPSE is not set
27 # CONFIG_SYN_PEREGRINE is not set
28 # CONFIG_SYN_RH_LIB18T is not set
29 # CONFIG_SYN_RHUMC is not set
30 # CONFIG_SYN_SMIC13 is not set
31 # CONFIG_SYN_SPARTAN2 is not set
32 # CONFIG_SYN_SPARTAN3 is not set
33 # CONFIG_SYN_SPARTAN3E is not set
34 # CONFIG_SYN_VIRTEX is not set
35 # CONFIG_SYN_VIRTEXE is not set
36 # CONFIG_SYN_VIRTEX2 is not set
37 # CONFIG_SYN_VIRTEX4 is not set
38 # CONFIG_SYN_VIRTEX5 is not set
39 # CONFIG_SYN_UMC is not set
40 # CONFIG_SYN_TSMC90 is not set
41 # CONFIG_SYN_INFER_RAM is not set
42 # CONFIG_SYN_INFER_PADS is not set
43 # CONFIG_SYN_NO_ASYNC is not set
44 # CONFIG_SYN_SCAN is not set
45
46 #
47 # Clock generation
48 #
49 # CONFIG_CLK_INFERRED is not set
50 # CONFIG_CLK_HCLKBUF is not set
51 # CONFIG_CLK_ALTDLL is not set
52 # CONFIG_CLK_LATDLL is not set
53 CONFIG_CLK_PRO3PLL=y
54 # CONFIG_CLK_LIB18T is not set
55 # CONFIG_CLK_RHUMC is not set
56 # CONFIG_CLK_CLKDLL is not set
57 # CONFIG_CLK_DCM is not set
58 CONFIG_CLK_MUL=2
59 CONFIG_CLK_DIV=8
60 CONFIG_OCLK_DIV=2
61 # CONFIG_PCI_SYSCLK is not set
62 CONFIG_LEON3=y
63 CONFIG_PROC_NUM=1
64
65 #
66 # Processor
67 #
68
69 #
70 # Integer unit
71 #
72 CONFIG_IU_NWINDOWS=8
73 # CONFIG_IU_V8MULDIV is not set
74 # CONFIG_IU_SVT is not set
75 CONFIG_IU_LDELAY=1
76 CONFIG_IU_WATCHPOINTS=0
77 # CONFIG_PWD is not set
78 CONFIG_IU_RSTADDR=00000
79
80 #
81 # Floating-point unit
82 #
83 # CONFIG_FPU_ENABLE is not set
84
85 #
86 # Cache system
87 #
88 CONFIG_ICACHE_ENABLE=y
89 CONFIG_ICACHE_ASSO1=y
90 # CONFIG_ICACHE_ASSO2 is not set
91 # CONFIG_ICACHE_ASSO3 is not set
92 # CONFIG_ICACHE_ASSO4 is not set
93 # CONFIG_ICACHE_SZ1 is not set
94 # CONFIG_ICACHE_SZ2 is not set
95 CONFIG_ICACHE_SZ4=y
96 # CONFIG_ICACHE_SZ8 is not set
97 # CONFIG_ICACHE_SZ16 is not set
98 # CONFIG_ICACHE_SZ32 is not set
99 # CONFIG_ICACHE_SZ64 is not set
100 # CONFIG_ICACHE_SZ128 is not set
101 # CONFIG_ICACHE_SZ256 is not set
102 # CONFIG_ICACHE_LZ16 is not set
103 CONFIG_ICACHE_LZ32=y
104 CONFIG_DCACHE_ENABLE=y
105 CONFIG_DCACHE_ASSO1=y
106 # CONFIG_DCACHE_ASSO2 is not set
107 # CONFIG_DCACHE_ASSO3 is not set
108 # CONFIG_DCACHE_ASSO4 is not set
109 # CONFIG_DCACHE_SZ1 is not set
110 # CONFIG_DCACHE_SZ2 is not set
111 CONFIG_DCACHE_SZ4=y
112 # CONFIG_DCACHE_SZ8 is not set
113 # CONFIG_DCACHE_SZ16 is not set
114 # CONFIG_DCACHE_SZ32 is not set
115 # CONFIG_DCACHE_SZ64 is not set
116 # CONFIG_DCACHE_SZ128 is not set
117 # CONFIG_DCACHE_SZ256 is not set
118 # CONFIG_DCACHE_LZ16 is not set
119 CONFIG_DCACHE_LZ32=y
120 # CONFIG_DCACHE_SNOOP is not set
121 CONFIG_CACHE_FIXED=0
122
123 #
124 # MMU
125 #
126 CONFIG_MMU_ENABLE=y
127 # CONFIG_MMU_COMBINED is not set
128 CONFIG_MMU_SPLIT=y
129 # CONFIG_MMU_REPARRAY is not set
130 CONFIG_MMU_REPINCREMENT=y
131 # CONFIG_MMU_I2 is not set
132 # CONFIG_MMU_I4 is not set
133 CONFIG_MMU_I8=y
134 # CONFIG_MMU_I16 is not set
135 # CONFIG_MMU_I32 is not set
136 # CONFIG_MMU_D2 is not set
137 # CONFIG_MMU_D4 is not set
138 CONFIG_MMU_D8=y
139 # CONFIG_MMU_D16 is not set
140 # CONFIG_MMU_D32 is not set
141 CONFIG_MMU_FASTWB=y
142 CONFIG_MMU_PAGE_4K=y
143 # CONFIG_MMU_PAGE_8K is not set
144 # CONFIG_MMU_PAGE_16K is not set
145 # CONFIG_MMU_PAGE_32K is not set
146 # CONFIG_MMU_PAGE_PROG is not set
147
148 #
149 # Debug Support Unit
150 #
151 # CONFIG_DSU_ENABLE is not set
152
153 #
154 # Fault-tolerance
155 #
156
157 #
158 # VHDL debug settings
159 #
160 # CONFIG_IU_DISAS is not set
161 # CONFIG_DEBUG_PC32 is not set
162
163 #
164 # AMBA configuration
165 #
166 CONFIG_AHB_DEFMST=0
167 CONFIG_AHB_RROBIN=y
168 # CONFIG_AHB_SPLIT is not set
169 CONFIG_AHB_IOADDR=FFF
170 CONFIG_APB_HADDR=800
171 # CONFIG_AHB_MON is not set
172
173 #
174 # Debug Link
175 #
176 CONFIG_DSU_UART=y
177 # CONFIG_DSU_JTAG is not set
178
179 #
180 # Peripherals
181 #
182
183 #
184 # Memory controllers
185 #
186
187 #
188 # 8/32-bit PROM/SRAM controller
189 #
190 CONFIG_SRCTRL=y
191 # CONFIG_SRCTRL_8BIT is not set
192 CONFIG_SRCTRL_PROMWS=3
193 CONFIG_SRCTRL_RAMWS=0
194 CONFIG_SRCTRL_IOWS=0
195 # CONFIG_SRCTRL_RMW is not set
196 CONFIG_SRCTRL_SRBANKS1=y
197 # CONFIG_SRCTRL_SRBANKS2 is not set
198 # CONFIG_SRCTRL_SRBANKS3 is not set
199 # CONFIG_SRCTRL_SRBANKS4 is not set
200 # CONFIG_SRCTRL_SRBANKS5 is not set
201 # CONFIG_SRCTRL_BANKSZ0 is not set
202 # CONFIG_SRCTRL_BANKSZ1 is not set
203 # CONFIG_SRCTRL_BANKSZ2 is not set
204 # CONFIG_SRCTRL_BANKSZ3 is not set
205 # CONFIG_SRCTRL_BANKSZ4 is not set
206 # CONFIG_SRCTRL_BANKSZ5 is not set
207 # CONFIG_SRCTRL_BANKSZ6 is not set
208 # CONFIG_SRCTRL_BANKSZ7 is not set
209 # CONFIG_SRCTRL_BANKSZ8 is not set
210 # CONFIG_SRCTRL_BANKSZ9 is not set
211 # CONFIG_SRCTRL_BANKSZ10 is not set
212 # CONFIG_SRCTRL_BANKSZ11 is not set
213 # CONFIG_SRCTRL_BANKSZ12 is not set
214 # CONFIG_SRCTRL_BANKSZ13 is not set
215 CONFIG_SRCTRL_ROMASEL=19
216
217 #
218 # Leon2 memory controller
219 #
220 CONFIG_MCTRL_LEON2=y
221 # CONFIG_MCTRL_8BIT is not set
222 # CONFIG_MCTRL_16BIT is not set
223 # CONFIG_MCTRL_5CS is not set
224 # CONFIG_MCTRL_SDRAM is not set
225
226 #
227 # PC133 SDRAM controller
228 #
229 # CONFIG_SDCTRL is not set
230
231 #
232 # On-chip RAM/ROM
233 #
234 # CONFIG_AHBROM_ENABLE is not set
235 # CONFIG_AHBRAM_ENABLE is not set
236
237 #
238 # Ethernet
239 #
240 # CONFIG_GRETH_ENABLE is not set
241
242 #
243 # CAN
244 #
245 # CONFIG_CAN_ENABLE is not set
246
247 #
248 # PCI
249 #
250 # CONFIG_PCI_SIMPLE_TARGET is not set
251 # CONFIG_PCI_MASTER_TARGET is not set
252 # CONFIG_PCI_ARBITER is not set
253 # CONFIG_PCI_TRACE is not set
254
255 #
256 # Spacewire
257 #
258 # CONFIG_SPW_ENABLE is not set
259
260 #
261 # UARTs, timers and irq control
262 #
263 CONFIG_UART1_ENABLE=y
264 # CONFIG_UA1_FIFO1 is not set
265 # CONFIG_UA1_FIFO2 is not set
266 CONFIG_UA1_FIFO4=y
267 # CONFIG_UA1_FIFO8 is not set
268 # CONFIG_UA1_FIFO16 is not set
269 # CONFIG_UA1_FIFO32 is not set
270 # CONFIG_UART2_ENABLE is not set
271 CONFIG_IRQ3_ENABLE=y
272 # CONFIG_IRQ3_SEC is not set
273 CONFIG_GPT_ENABLE=y
274 CONFIG_GPT_NTIM=2
275 CONFIG_GPT_SW=8
276 CONFIG_GPT_TW=32
277 CONFIG_GPT_IRQ=8
278 CONFIG_GPT_SEPIRQ=y
279 CONFIG_GPT_WDOGEN=y
280 CONFIG_GPT_WDOG=FFFF
281 CONFIG_GRGPIO_ENABLE=y
282 CONFIG_GRGPIO_WIDTH=8
283 CONFIG_GRGPIO_IMASK=0000
284
285 #
286 # VHDL Debugging
287 #
288 # CONFIG_DEBUG_UART is not set
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1 GRLIB=../..
2 TOP=leon3mp
3 BOARD=em-LeonLPP-A3PE3kL-v3-core1
4 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
5 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
6 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
7 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
8 EFFORT=high
9 XSTOPT=
10 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
11 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
12 VHDLSYNFILES=config.vhd leon3mp.vhd
13 #VHDLSIMFILES=testbench.vhd
14 #SIMTOP=testbench
15 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
16 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
17 PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
18 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
19 CLEAN=soft-clean
20
21 TECHLIBS = proasic3e
22
23 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
24 tmtc openchip hynix ihp gleichmann micron usbhc
25
26 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
27 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
28 ./amba_lcd_16x2_ctrlr \
29 ./general_purpose/lpp_AMR \
30 ./general_purpose/lpp_balise \
31 ./general_purpose/lpp_delay \
32 ./dsp/lpp_fft \
33 ./lpp_bootloader \
34 ./lpp_cna \
35 ./lpp_demux \
36 ./lpp_matrix \
37 ./lpp_uart \
38 ./lpp_usb \
39 ./lpp_Header \
40
41 FILESKIP = i2cmst.vhd \
42 APB_MULTI_DIODE.vhd \
43 APB_SIMPLE_DIODE.vhd
44
45 include $(GRLIB)/bin/Makefile
46 include $(GRLIB)/software/leon3/Makefile
47
48 ################## project specific targets ##########################
49
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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design test bench configuration
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 ------------------------------------------------------------------------------
15
16
17 library techmap;
18 use techmap.gencomp.all;
19
20 package config is
21
22
23 -- Technology and synthesis options
24 constant CFG_FABTECH : integer := apa3e;
25 constant CFG_MEMTECH : integer := apa3e;
26 constant CFG_PADTECH : integer := inferred;
27 constant CFG_NOASYNC : integer := 0;
28 constant CFG_SCAN : integer := 0;
29
30 -- Clock generator
31 constant CFG_CLKTECH : integer := inferred;
32 constant CFG_CLKMUL : integer := (1);
33 constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
34 constant CFG_OCLKDIV : integer := (1);
35 constant CFG_PCIDLL : integer := 0;
36 constant CFG_PCISYSCLK: integer := 0;
37 constant CFG_CLK_NOFB : integer := 0;
38
39 -- LEON3 processor core
40 constant CFG_LEON3 : integer := 1;
41 constant CFG_NCPU : integer := (1);
42 --constant CFG_NWIN : integer := (7); -- PLE
43 constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
44 constant CFG_V8 : integer := 0;
45 constant CFG_MAC : integer := 0;
46 constant CFG_SVT : integer := 0;
47 constant CFG_RSTADDR : integer := 16#00000#;
48 constant CFG_LDDEL : integer := (1);
49 constant CFG_NWP : integer := (0);
50 constant CFG_PWD : integer := 1*2;
51 constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist
52 --constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE
53 constant CFG_GRFPUSH : integer := 0;
54 constant CFG_ICEN : integer := 1;
55 constant CFG_ISETS : integer := 1;
56 constant CFG_ISETSZ : integer := 4;
57 constant CFG_ILINE : integer := 4;
58 constant CFG_IREPL : integer := 0;
59 constant CFG_ILOCK : integer := 0;
60 constant CFG_ILRAMEN : integer := 0;
61 constant CFG_ILRAMADDR: integer := 16#8E#;
62 constant CFG_ILRAMSZ : integer := 1;
63 constant CFG_DCEN : integer := 1;
64 constant CFG_DSETS : integer := 1;
65 constant CFG_DSETSZ : integer := 4;
66 constant CFG_DLINE : integer := 4;
67 constant CFG_DREPL : integer := 0;
68 constant CFG_DLOCK : integer := 0;
69 constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
70 constant CFG_DFIXED : integer := 16#00F3#;
71 constant CFG_DLRAMEN : integer := 0;
72 constant CFG_DLRAMADDR: integer := 16#8F#;
73 constant CFG_DLRAMSZ : integer := 1;
74 constant CFG_MMUEN : integer := 0;
75 constant CFG_ITLBNUM : integer := 2;
76 constant CFG_DTLBNUM : integer := 2;
77 constant CFG_TLB_TYPE : integer := 1 + 0*2;
78 constant CFG_TLB_REP : integer := 1;
79 constant CFG_DSU : integer := 1;
80 constant CFG_ITBSZ : integer := 0;
81 constant CFG_ATBSZ : integer := 0;
82 constant CFG_LEON3FT_EN : integer := 0;
83 constant CFG_IUFT_EN : integer := 0;
84 constant CFG_FPUFT_EN : integer := 0;
85 constant CFG_RF_ERRINJ : integer := 0;
86 constant CFG_CACHE_FT_EN : integer := 0;
87 constant CFG_CACHE_ERRINJ : integer := 0;
88 constant CFG_LEON3_NETLIST: integer := 0;
89 constant CFG_DISAS : integer := 0 + 0;
90 constant CFG_PCLOW : integer := 2;
91
92 -- AMBA settings
93 constant CFG_DEFMST : integer := (0);
94 constant CFG_RROBIN : integer := 1;
95 constant CFG_SPLIT : integer := 0;
96 constant CFG_AHBIO : integer := 16#FFF#;
97 constant CFG_APBADDR : integer := 16#800#;
98 constant CFG_AHB_MON : integer := 0;
99 constant CFG_AHB_MONERR : integer := 0;
100 constant CFG_AHB_MONWAR : integer := 0;
101
102 -- DSU UART
103 constant CFG_AHB_UART : integer := 1;
104
105 -- JTAG based DSU interface
106 constant CFG_AHB_JTAG : integer := 0;
107
108 -- Ethernet DSU
109 constant CFG_DSU_ETH : integer := 0 + 0;
110 constant CFG_ETH_BUF : integer := 1;
111 constant CFG_ETH_IPM : integer := 16#C0A8#;
112 constant CFG_ETH_IPL : integer := 16#0033#;
113 constant CFG_ETH_ENM : integer := 16#00007A#;
114 constant CFG_ETH_ENL : integer := 16#CC0001#;
115
116 -- LEON2 memory controller
117 constant CFG_MCTRL_LEON2 : integer := 1;
118 constant CFG_MCTRL_RAM8BIT : integer := 0;
119 constant CFG_MCTRL_RAM16BIT : integer := 0;
120 constant CFG_MCTRL_5CS : integer := 0;
121 constant CFG_MCTRL_SDEN : integer := 0;
122 constant CFG_MCTRL_SEPBUS : integer := 0;
123 constant CFG_MCTRL_INVCLK : integer := 0;
124 constant CFG_MCTRL_SD64 : integer := 0;
125 constant CFG_MCTRL_PAGE : integer := 0 + 0;
126
127 -- SSRAM controller
128 constant CFG_SSCTRL : integer := 0;
129 constant CFG_SSCTRLP16 : integer := 0;
130
131 -- AHB ROM
132 constant CFG_AHBROMEN : integer := 0;
133 constant CFG_AHBROPIP : integer := 0;
134 constant CFG_AHBRODDR : integer := 16#000#;
135 constant CFG_ROMADDR : integer := 16#000#;
136 constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
137
138 -- AHB RAM
139 constant CFG_AHBRAMEN : integer := 0;
140 constant CFG_AHBRSZ : integer := 1;
141 constant CFG_AHBRADDR : integer := 16#A00#;
142
143 -- Gaisler Ethernet core
144 constant CFG_GRETH : integer := 0;
145 constant CFG_GRETH1G : integer := 0;
146 constant CFG_ETH_FIFO : integer := 8;
147
148 -- CAN 2.0 interface
149 constant CFG_CAN : integer := 0;
150 constant CFG_CANIO : integer := 16#0#;
151 constant CFG_CANIRQ : integer := 0;
152 constant CFG_CANLOOP : integer := 0;
153 constant CFG_CAN_SYNCRST : integer := 0;
154 constant CFG_CANFT : integer := 0;
155
156 -- UART 1
157 constant CFG_UART1_ENABLE : integer := 1;
158 constant CFG_UART1_FIFO : integer := 1;
159
160 -- LEON3 interrupt controller
161 constant CFG_IRQ3_ENABLE : integer := 1;
162
163 -- Modular timer
164 constant CFG_GPT_ENABLE : integer := 1;
165 constant CFG_GPT_NTIM : integer := (3);
166 constant CFG_GPT_SW : integer := (8);
167 constant CFG_GPT_TW : integer := (32);
168 constant CFG_GPT_IRQ : integer := (8);
169 constant CFG_GPT_SEPIRQ : integer := 1;
170 constant CFG_GPT_WDOGEN : integer := 0;
171 constant CFG_GPT_WDOG : integer := 16#0#;
172
173 -- GPIO port
174 constant CFG_GRGPIO_ENABLE : integer := 1;
175 constant CFG_GRGPIO_IMASK : integer := 16#0000#;
176 constant CFG_GRGPIO_WIDTH : integer := (7);
177
178 -- GRLIB debugging
179 constant CFG_DUART : integer := 0;
180
181
182 end;
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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19
20
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
36 USE work.config.ALL;
37 LIBRARY lpp;
38 --use lpp.lpp_amba.all;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_top_lfr_pkg.ALL;
42 --use lpp.lpp_uart.all;
43 --use lpp.lpp_matrix.all;
44 --use lpp.lpp_delay.all;
45 --use lpp.lpp_fft.all;
46 --use lpp.fft_components.all;
47 use lpp.iir_filter.all;
48 USE lpp.general_purpose.ALL;
49 --use lpp.Filtercfg.all;
50 USE lpp.lpp_lfr_time_management.ALL; -- PLE
51 --use lpp.lpp_lfr_spectral_matrices_DMA.all; -- PLE
52
53 ENTITY leon3mp IS
54 GENERIC (
55 fabtech : INTEGER := CFG_FABTECH;
56 memtech : INTEGER := CFG_MEMTECH;
57 padtech : INTEGER := CFG_PADTECH;
58 clktech : INTEGER := CFG_CLKTECH;
59 disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
60 dbguart : INTEGER := CFG_DUART; -- Print UART on console
61 pclow : INTEGER := CFG_PCLOW
62 );
63 PORT (
64 clk100MHz : IN STD_ULOGIC;
65 clk49_152MHz : IN STD_ULOGIC;
66 reset : IN STD_ULOGIC;
67
68 errorn : OUT STD_ULOGIC;
69
70 -- UART AHB ---------------------------------------------------------------
71 ahbrxd : IN STD_ULOGIC; -- DSU rx data
72 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
73
74 -- UART APB ---------------------------------------------------------------
75 urxd1 : IN STD_ULOGIC; -- UART1 rx data
76 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
77
78 -- RAM --------------------------------------------------------------------
79 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
80 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 nSRAM_BE0 : OUT STD_LOGIC;
82 nSRAM_BE1 : OUT STD_LOGIC;
83 nSRAM_BE2 : OUT STD_LOGIC;
84 nSRAM_BE3 : OUT STD_LOGIC;
85 nSRAM_WE : OUT STD_LOGIC;
86 nSRAM_CE : OUT STD_LOGIC;
87 nSRAM_OE : OUT STD_LOGIC;
88
89 -- SPW --------------------------------------------------------------------
90 spw1_din : IN STD_LOGIC; -- PLE
91 spw1_sin : IN STD_LOGIC; -- PLE
92 spw1_dout : OUT STD_LOGIC; -- PLE
93 spw1_sout : OUT STD_LOGIC; -- PLE
94
95 spw2_din : IN STD_LOGIC; -- JCPE --TODO
96 spw2_sin : IN STD_LOGIC; -- JCPE --TODO
97 spw2_dout : OUT STD_LOGIC; -- JCPE --TODO
98 spw2_sout : OUT STD_LOGIC; -- JCPE --TODO
99
100 -- ADC --------------------------------------------------------------------
101 bias_fail_sw : OUT STD_LOGIC;
102 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
103 ADC_smpclk : OUT STD_LOGIC;
104 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
105
106 ---------------------------------------------------------------------------
107 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
108 );
109 END;
110
111 ARCHITECTURE Behavioral OF leon3mp IS
112
113 --constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
114 -- CFG_GRETH+CFG_AHB_JTAG;
115 CONSTANT maxahbmsp : INTEGER := CFG_NCPU+
116 CFG_AHB_UART+
117 CFG_GRETH+
118 CFG_AHB_JTAG
119 +2; -- 1 is for the SpaceWire module grspw2, which is a master
120 CONSTANT maxahbm : INTEGER := maxahbmsp;
121
122 --Clk & Rst gοΏ½nοΏ½
123 SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0);
124 SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
125 SIGNAL resetnl : STD_ULOGIC;
126 SIGNAL clk2x : STD_ULOGIC;
127 SIGNAL lclk2x : STD_ULOGIC;
128 SIGNAL lclk25MHz : STD_ULOGIC;
129 SIGNAL lclk50MHz : STD_ULOGIC;
130 SIGNAL lclk100MHz : STD_ULOGIC;
131 SIGNAL clkm : STD_ULOGIC;
132 SIGNAL rstn : STD_ULOGIC;
133 SIGNAL rstraw : STD_ULOGIC;
134 SIGNAL pciclk : STD_ULOGIC;
135 SIGNAL sdclkl : STD_ULOGIC;
136 SIGNAL cgi : clkgen_in_type;
137 SIGNAL cgo : clkgen_out_type;
138 --- AHB / APB
139 SIGNAL apbi : apb_slv_in_type;
140 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
141 SIGNAL ahbsi : ahb_slv_in_type;
142 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
143 SIGNAL ahbmi : ahb_mst_in_type;
144 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
145 --UART
146 SIGNAL ahbuarti : uart_in_type;
147 SIGNAL ahbuarto : uart_out_type;
148 SIGNAL apbuarti : uart_in_type;
149 SIGNAL apbuarto : uart_out_type;
150 --MEM CTRLR
151 SIGNAL memi : memory_in_type;
152 SIGNAL memo : memory_out_type;
153 SIGNAL wpo : wprot_out_type;
154 SIGNAL sdo : sdram_out_type;
155 SIGNAL ramcs : STD_ULOGIC;
156 --IRQ
157 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
158 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
159 --Timer
160 SIGNAL gpti : gptimer_in_type;
161 SIGNAL gpto : gptimer_out_type;
162 --GPIO
163 SIGNAL gpioi : gpio_in_type;
164 SIGNAL gpioo : gpio_out_type;
165 --DSU
166 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
167 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
168 SIGNAL dsui : dsu_in_type;
169 SIGNAL dsuo : dsu_out_type;
170
171 ---------------------------------------------------------------------
172 --- AJOUT TEST ------------------------Signaux----------------------
173 ---------------------------------------------------------------------
174
175 ---------------------------------------------------------------------
176 CONSTANT IOAEN : INTEGER := CFG_CAN;
177 CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz
178
179 -- time management signal
180 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 SIGNAL fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
182
183 -- Spacewire signals
184 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
185 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
186 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
187 signal spw_rxtxclk : std_ulogic;
188 signal spw_rxclkn : std_ulogic;
189 SIGNAL spw_clk : std_logic;
190 SIGNAL swni : grspw_in_type; -- PLE
191 SIGNAL swno : grspw_out_type; -- PLE
192 SIGNAL clkmn : STD_ULOGIC; -- PLE
193 SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14
194
195 -- AD Converter RHF1401
196 SIGNAL sample : Samples14v(7 DOWNTO 0);
197 SIGNAL sample_val : STD_LOGIC;
198 -----------------------------------------------------------------------------
199 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
200
201 BEGIN
202
203
204 ----------------------------------------------------------------------
205 --- Reset and Clock generation -------------------------------------
206 ----------------------------------------------------------------------
207
208 vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0');
209 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
210
211 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
212
213
214 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz);
215
216 clkgen0 : clkgen -- clock generator
217 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
218 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
219 PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
220
221 PROCESS(lclk100MHz)
222 BEGIN
223 IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN
224 lclk50MHz <= NOT lclk50MHz;
225 END IF;
226 END PROCESS;
227
228 PROCESS(lclk50MHz)
229 BEGIN
230 IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN
231 lclk25MHz <= NOT lclk25MHz;
232 END IF;
233 END PROCESS;
234
235 lclk2x <= lclk50MHz;
236 spw_clk <= lclk50MHz;
237
238 ----------------------------------------------------------------------
239 --- LEON3 processor / DSU / IRQ ------------------------------------
240 ----------------------------------------------------------------------
241
242 l3 : IF CFG_LEON3 = 1 GENERATE
243 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
244 u0 : leon3s -- LEON3 processor
245 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
246 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
247 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
248 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
249 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
250 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
251 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
252 irqi(i), irqo(i), dbgi(i), dbgo(i));
253 END GENERATE;
254 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
255
256 dsugen : IF CFG_DSU = 1 GENERATE
257 dsu0 : dsu3 -- LEON3 Debug Support Unit
258 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
259 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
260 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
261 dsui.enable <= '1';
262 dsui.break <= '0';
263 led(2) <= dsuo.active;
264 END GENERATE;
265 END GENERATE;
266
267 nodsu : IF CFG_DSU = 0 GENERATE
268 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
269 END GENERATE;
270
271 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
272 irqctrl0 : irqmp -- interrupt controller
273 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
274 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
275 END GENERATE;
276 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
277 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
278 irqi(i).irl <= "0000";
279 END GENERATE;
280 apbo(2) <= apb_none;
281 END GENERATE;
282
283 ----------------------------------------------------------------------
284 --- Memory controllers ---------------------------------------------
285 ----------------------------------------------------------------------
286 memctrlr : mctrl GENERIC MAP (
287 hindex => 0,
288 pindex => 0,
289 paddr => 0,
290 srbanks => 1
291 )
292 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
293
294 memi.brdyn <= '1';
295 memi.bexcn <= '1';
296 memi.writen <= '1';
297 memi.wrn <= "1111";
298 memi.bwidth <= "10";
299
300 bdr : FOR i IN 0 TO 3 GENERATE
301 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
302 PORT MAP (
303 data(31-i*8 DOWNTO 24-i*8),
304 memo.data(31-i*8 DOWNTO 24-i*8),
305 memo.bdrive(i),
306 memi.data(31-i*8 DOWNTO 24-i*8));
307 END GENERATE;
308
309 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
310 PORT MAP (address, memo.address(21 DOWNTO 2));
311
312 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
313 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
314 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
315 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
316 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
317 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
318 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
319
320 ----------------------------------------------------------------------
321 --- AHB CONTROLLER -------------------------------------------------
322 ----------------------------------------------------------------------
323 ahb0 : ahbctrl -- AHB arbiter/multiplexer
324 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
325 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
326 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
327 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
328
329 ----------------------------------------------------------------------
330 --- AHB UART -------------------------------------------------------
331 ----------------------------------------------------------------------
332 dcomgen : IF CFG_AHB_UART = 1 GENERATE
333 dcom0 : ahbuart
334 GENERIC MAP ( hindex => 3, pindex => 4, paddr => 4)
335 PORT MAP ( rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3));
336 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
337 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
338 led(0) <= NOT ahbuarti.rxd;
339 led(1) <= NOT ahbuarto.txd;
340 END GENERATE;
341 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
342
343 ----------------------------------------------------------------------
344 --- APB Bridge -----------------------------------------------------
345 ----------------------------------------------------------------------
346 apb0 : apbctrl -- AHB/APB bridge
347 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
348 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
349
350 ----------------------------------------------------------------------
351 --- GPT Timer ------------------------------------------------------
352 ----------------------------------------------------------------------
353 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
354 timer0 : gptimer -- timer unit
355 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
356 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
357 nbits => CFG_GPT_TW)
358 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
359 gpti.dhalt <= dsuo.tstop;
360 gpti.extclk <= '0';
361 END GENERATE;
362 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
363
364
365 ----------------------------------------------------------------------
366 --- APB UART -------------------------------------------------------
367 ----------------------------------------------------------------------
368 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
369 uart1 : apbuart -- UART 1
370 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
371 fifosize => CFG_UART1_FIFO)
372 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
373 apbuarti.rxd <= urxd1;
374 apbuarti.extclk <= '0';
375 utxd1 <= apbuarto.txd;
376 apbuarti.ctsn <= '0';
377 END GENERATE;
378 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
379
380 -------------------------------------------------------------------------------
381 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
382 -------------------------------------------------------------------------------
383 lfrtimemanagement0 : apb_lfr_time_management
384 GENERIC MAP(pindex => 6, paddr => 6, pmask => 16#fff#,
385 masterclk => 25000000, timeclk => 49152000, finetimeclk => 65536,
386 pirq => 12)
387 PORT MAP(clkm, clk49_152MHz, rstn, swno.tickout, apbi, apbo(6),
388 coarse_time, fine_time);
389
390 -----------------------------------------------------------------------
391 --- SpaceWire --------------------------------------------------------
392 -----------------------------------------------------------------------
393
394 spw_rxtxclk <= spw_clk;
395 spw_rxclkn <= not spw_rxtxclk;
396
397 -- PADS for SPW1
398 spw1_rxd_pad : inpad generic map (tech => padtech)
399 port map (spw1_din, dtmp(0));
400 spw1_rxs_pad : inpad generic map (tech => padtech)
401 port map (spw1_sin, stmp(0));
402 spw1_txd_pad : outpad generic map (tech => padtech)
403 port map (spw1_dout, swno.d(0));
404 spw1_txs_pad : outpad generic map (tech => padtech)
405 port map (spw1_sout, swno.s(0));
406 -- PADS FOR SPW2
407 spw2_rxd_pad : inpad generic map (tech => padtech)
408 port map (spw2_din, dtmp(1));
409 spw2_rxs_pad : inpad generic map (tech => padtech)
410 port map (spw2_sin, stmp(1));
411 spw2_txd_pad : outpad generic map (tech => padtech)
412 port map (spw2_dout, swno.d(1));
413 spw2_txs_pad : outpad generic map (tech => padtech)
414 port map (spw2_sout, swno.s(1));
415
416 -- GRSPW PHY
417 --spw1_input: if CFG_SPW_GRSPW = 1 generate
418 spw_inputloop: for j in 0 to 1 generate
419 spw_phy0 : grspw_phy
420 generic map(
421 tech => fabtech,
422 rxclkbuftype => 1,
423 scantest => 0)
424 port map(
425 rxrst => swno.rxrst,
426 di => dtmp(j),
427 si => stmp(j),
428 rxclko => spw_rxclk(j),
429 do => swni.d(j),
430 ndo => swni.nd(j*5+4 downto j*5),
431 dconnect => swni.dconnect(j*2+1 downto j*2));
432 end generate spw_inputloop;
433
434 -- SPW core
435 sw0 : grspwm generic map(
436 tech => apa3e,
437 hindex => 1,
438 pindex => 5,
439 paddr => 5,
440 pirq => 11,
441 sysfreq => 25000, -- CPU_FREQ
442 rmap => 1,
443 rmapcrc => 1,
444 fifosize1 => 16,
445 fifosize2 => 16,
446 rxclkbuftype => 1,
447 rxunaligned => 0,
448 rmapbufs => 4,
449 ft => 0,
450 netlist => 0,
451 ports => 2,
452 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
453 memtech => apa3e,
454 destkey => 2,
455 spwcore => 1
456 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
457 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
458 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
459 )
460 port map(rstn, clkm, spw_rxclk(0),
461 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
462 ahbmi, ahbmo(1), apbi, apbo(5),
463 swni, swno);
464
465 swni.tickin <= '0';
466 swni.rmapen <= '1';
467 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
468 swni.tickinraw <= '0';
469 swni.timein <= (others => '0');
470 swni.dcrstval <= (others => '0');
471 swni.timerrstval <= (others => '0');
472
473 -------------------------------------------------------------------------------
474 -- WAVEFORM PICKER
475 -------------------------------------------------------------------------------
476 waveform_picker0 : top_wf_picker
477 GENERIC MAP(
478 hindex => 2,
479 pindex => 15,
480 paddr => 15,
481 pmask => 16#fff#,
482 pirq => 14,
483 tech => CFG_FABTECH,
484 nb_burst_available_size => 12, -- size of the register holding the nb of burst
485 nb_snapshot_param_size => 12, -- size of the register holding the snapshots size
486 delta_snapshot_size => 16, -- snapshots period
487 delta_f2_f0_size => 20, -- initialize the counter when the f2 snapshot starts
488 delta_f2_f1_size => 16, -- nb f0 ticks before starting the f1 snapshot
489 ENABLE_FILTER => '1'
490 )
491 PORT MAP(
492 sample_B => sample(2 DOWNTO 0),
493 sample_E => sample(7 DOWNTO 3),
494 sample_val => sample_val,
495 --
496 cnv_clk => clkm,
497 cnv_rstn => rstn,
498 -- AMBA AHB system signals
499 HCLK => clkm,
500 HRESETn => rstn,
501 -- AMBA APB Slave Interface
502 apbi => apbi,
503 apbo => apbo(15),
504 -- AMBA AHB Master Interface
505 AHB_Master_In => ahbmi,
506 AHB_Master_Out => ahbmo(2),
507 --
508 coarse_time_0 => coarse_time(0), -- bit 0 of the coarse time
509 --
510 data_shaping_BW => bias_fail_sw
511 );
512
513 top_ad_conv_RHF1401_1: top_ad_conv_RHF1401
514 GENERIC MAP (
515 ChanelCount => 8,
516 ncycle_cnv_high => 79,
517 ncycle_cnv => 500)
518 PORT MAP (
519 cnv_clk => clk49_152MHz,
520 cnv_rstn => rstn,
521
522 cnv => ADC_smpclk,
523
524 clk => clkm,
525 rstn => rstn,
526 ADC_data => ADC_data,
527 --ADC_smpclk => ,
528 ADC_nOE => ADC_OEB_bar_CH,
529 sample => sample,
530 sample_val => sample_val);
531
532 -- ADC_OEB_bar_CH(0) <= ADC_OEB_bar_CH_s(5); -- B1
533 -- ADC_OEB_bar_CH(1) <= ADC_OEB_bar_CH_s(6); -- B2
534 -- ADC_OEB_bar_CH(2) <= ADC_OEB_bar_CH_s(7); -- B3
535
536 -- ADC_OEB_bar_CH(3) <= ADC_OEB_bar_CH_s(0); -- V1
537 -- ADC_OEB_bar_CH(4) <= ADC_OEB_bar_CH_s(1); -- V2
538 -- ADC_OEB_bar_CH(5) <= ADC_OEB_bar_CH_s(2); -- V3
539 -- ADC_OEB_bar_CH(6) <= ADC_OEB_bar_CH_s(3); -- V4
540 -- ADC_OEB_bar_CH(7) <= ADC_OEB_bar_CH_s(4); -- V5
541
542 END Behavioral; No newline at end of file
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