HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/ProjetBlanc-LeonLPP-A3PE3kL/simulation/modelsim.ini

LPP's Code Repositories

- This repo
- ?
- Use '/' key to quickly access this field. - Enter a name of repository, or repository group for quick search. - Prefix query to allow special search: user:admin, to search for usernames, always global user_group:devops, to search for user groups, always global pr:303, to search for pull request number, title, or description, always global commit:efced4, to search for commits, scoped to repositories or groups file:models.py, to search for file paths, scoped to repositories or groups For advanced full text search visit: repository search
Home
Public journal
Gists
Sign in

HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib

RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Ajout design perso Projet-LeonLFR-A3PE3kL-Sheldon-DataFlux...

Ajout design perso Projet-LeonLFR-A3PE3kL-Sheldon-DataFlux Supression fichiers obsolete !

Alexis Jeandet - - Load All Authors

File last commit:

r181:2a5b3fda6e52 alexis


                r284:058199c2c092

martin

Download file

             modelsim.ini
        
                    13 lines
            
             | 268 B
            
                | text/x-ini
            
             |
                IniLexer
            
             / designs / ProjetBlanc-LeonLPP-A3PE3kL / simulation / modelsim.ini
          
                    History
                
                 |
                  Annotation
                 | Raw
                 |Copy content
                 |Copy permalink

      [Library]

      others = $MODEL_TECH/../modelsim.ini

      proasic3l = C:/Actel/Libero_v9.1/Designer/lib/modelsim/precompiled/vhdl/proasic3l

      syncad_vhdl_lib = C:\Actel\Libero_v9.1\Designer/lib/actel/syncad_vhdl_lib

      [vcom]

      VHDL93 = 1

      [vsim]

      IterationLimit = 5000

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages

				[Library]
				others = $MODEL_TECH/../modelsim.ini

				proasic3l = C:/Actel/Libero_v9.1/Designer/lib/modelsim/precompiled/vhdl/proasic3l


				syncad_vhdl_lib = C:\Actel\Libero_v9.1\Designer/lib/actel/syncad_vhdl_lib

				[vcom]
				VHDL93 = 1

				[vsim]
				IterationLimit = 5000