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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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library lpp;
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use lpp.lpp_ad_conv.all;
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use lpp.lpp_amba.all;
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use lpp.apb_devices_list.all;
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use lpp.general_purpose.all;
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use lpp.Rocket_PCM_Encoder.all;
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use work.config.all;
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entity DC_ACQ_TOP is
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generic(
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WordSize : integer := 8;
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WordCnt : integer := 144;
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MinFCount : integer := 64;
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EnableSR : integer := 1;
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CstDATA : integer := 0;
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FakeADC : integer := 0;
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CDS : integer := 0
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);
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port(
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reset : in std_logic;
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clk : in std_logic;
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SyncSig : in STD_LOGIC;
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minorF : in std_logic;
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majorF : in std_logic;
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sclk : in std_logic;
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WordClk : in std_logic;
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DC_ADC_Sclk : out std_logic;
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DC_ADC_IN : in std_logic_vector(1 downto 0);
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DC_ADC_ClkDiv : out std_logic;
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DC_ADC_FSynch : out std_logic;
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SET_RESET0 : out std_logic;
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SET_RESET1 : out std_logic;
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AMR1X : out std_logic_vector(23 downto 0);
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AMR1Y : out std_logic_vector(23 downto 0);
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AMR1Z : out std_logic_vector(23 downto 0);
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AMR2X : out std_logic_vector(23 downto 0);
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AMR2Y : out std_logic_vector(23 downto 0);
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AMR2Z : out std_logic_vector(23 downto 0);
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AMR3X : out std_logic_vector(23 downto 0);
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AMR3Y : out std_logic_vector(23 downto 0);
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AMR3Z : out std_logic_vector(23 downto 0);
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AMR4X : out std_logic_vector(23 downto 0);
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AMR4Y : out std_logic_vector(23 downto 0);
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AMR4Z : out std_logic_vector(23 downto 0);
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Temp1 : out std_logic_vector(23 downto 0);
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Temp2 : out std_logic_vector(23 downto 0);
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Temp3 : out std_logic_vector(23 downto 0);
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Temp4 : out std_logic_vector(23 downto 0)
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);
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end DC_ACQ_TOP;
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architecture Behavioral of DC_ACQ_TOP is
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signal DC_ADC_SmplClk : std_logic;
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signal LF_ADC_SmplClk : std_logic;
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signal SET_RESET0_sig : std_logic;
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signal SET_RESET1_sig : std_logic;
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signal SET_RESET_counter : integer range 0 to 31:=0;
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signal AMR1X_Sync : std_logic_vector(23 downto 0);
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signal AMR1Y_Sync : std_logic_vector(23 downto 0);
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signal AMR1Z_Sync : std_logic_vector(23 downto 0);
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signal AMR2X_Sync : std_logic_vector(23 downto 0);
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signal AMR2Y_Sync : std_logic_vector(23 downto 0);
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signal AMR2Z_Sync : std_logic_vector(23 downto 0);
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signal AMR3X_Sync : std_logic_vector(23 downto 0);
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signal AMR3Y_Sync : std_logic_vector(23 downto 0);
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signal AMR3Z_Sync : std_logic_vector(23 downto 0);
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signal AMR4X_Sync : std_logic_vector(23 downto 0);
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signal AMR4Y_Sync : std_logic_vector(23 downto 0);
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signal AMR4Z_Sync : std_logic_vector(23 downto 0);
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signal Temp1_Sync : std_logic_vector(23 downto 0);
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signal Temp2_Sync : std_logic_vector(23 downto 0);
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signal Temp3_Sync : std_logic_vector(23 downto 0);
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signal Temp4_Sync : std_logic_vector(23 downto 0);
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begin
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------------------------------------------------------------------
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--
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-- DC sampling clock generation
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--
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------------------------------------------------------------------
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DC_SMPL_CLK0 : entity work.LF_SMPL_CLK
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--generic map(36)
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generic map(288)
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port map(
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reset => reset,
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wclk => WordClk,
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SMPL_CLK => DC_ADC_SmplClk
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);
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------------------------------------------------------------------
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------------------------------------------------------------------
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--
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-- DC ADC
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--
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------------------------------------------------------------------
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ADC1: IF CstDATA /= 1 GENERATE
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ADC : IF FakeADC /=1 GENERATE
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DC_ADC0 : DUAL_ADS1278_DRIVER
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port map(
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Clk => clk,
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reset => reset,
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SpiClk => DC_ADC_Sclk,
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DIN => DC_ADC_IN,
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SmplClk => DC_ADC_SmplClk,
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OUT00 => AMR1X_Sync,
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OUT01 => AMR1Y_Sync,
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OUT02 => AMR1Z_Sync,
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OUT03 => AMR2X_Sync,
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OUT04 => AMR2Y_Sync,
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OUT05 => AMR2Z_Sync,
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OUT06 => Temp1_Sync,
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OUT07 => Temp2_Sync,
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OUT10 => AMR3X_Sync,
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OUT11 => AMR3Y_Sync,
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OUT12 => AMR3Z_Sync,
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OUT13 => AMR4X_Sync,
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OUT14 => AMR4Y_Sync,
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OUT15 => AMR4Z_Sync,
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OUT16 => Temp3_Sync,
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OUT17 => Temp4_Sync,
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FSynch => DC_ADC_FSynch
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);
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END GENERATE;
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NOADC: IF FakeADC=1 GENERATE
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DC_ADC0 : entity work.FAKE_DUAL_ADS1278_DRIVER
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port map(
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Clk => clk,
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reset => reset,
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SpiClk => DC_ADC_Sclk,
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DIN => DC_ADC_IN,
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SmplClk => DC_ADC_SmplClk,
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OUT00 => AMR1X_Sync,
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OUT01 => AMR1Y_Sync,
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OUT02 => AMR1Z_Sync,
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OUT03 => AMR2X_Sync,
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OUT04 => AMR2Y_Sync,
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OUT05 => AMR2Z_Sync,
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OUT06 => Temp1_Sync,
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OUT07 => Temp2_Sync,
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OUT10 => AMR3X_Sync,
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OUT11 => AMR3Y_Sync,
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OUT12 => AMR3Z_Sync,
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OUT13 => AMR4X_Sync,
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OUT14 => AMR4Y_Sync,
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OUT15 => AMR4Z_Sync,
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OUT16 => Temp3_Sync,
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OUT17 => Temp4_Sync,
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FSynch => DC_ADC_FSynch
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);
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END GENERATE;
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END GENERATE;
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------------------------------------------------------------------
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NOADC: IF CstDATA = 1 GENERATE
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AMR1X_Sync <= AMR1Xcst;
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AMR1Y_Sync <= AMR1Ycst;
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AMR1Z_Sync <= AMR1Zcst;
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AMR2X_Sync <= AMR2Xcst;
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AMR2Y_Sync <= AMR2Ycst;
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AMR2Z_Sync <= AMR2Zcst;
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Temp1_Sync <= Temp1cst;
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Temp2_Sync <= Temp2cst;
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AMR3X_Sync <= AMR3Xcst;
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AMR3Y_Sync <= AMR3Ycst;
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AMR3Z_Sync <= AMR3Zcst;
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AMR4X_Sync <= AMR4Xcst;
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AMR4Y_Sync <= AMR4Ycst;
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AMR4Z_Sync <= AMR4Zcst;
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Temp3_Sync <= Temp3cst;
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Temp4_Sync <= Temp4cst;
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END GENERATE;
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------------------------------------------------------------------
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--
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-- SET/RESET GEN
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--
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------------------------------------------------------------------
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SR: IF EnableSR /=0 GENERATE
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process(reset,DC_ADC_SmplClk)
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begin
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if reset = '0' then
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SET_RESET0_sig <= '0';
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elsif DC_ADC_SmplClk'event and DC_ADC_SmplClk = '0' then
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if(SET_RESET_counter = 31) then
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SET_RESET0_sig <= not SET_RESET0_sig;
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SET_RESET_counter <= 0;
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else
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SET_RESET_counter <= SET_RESET_counter +1;
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end if;
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end if;
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end process;
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END GENERATE;
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NOSR: IF EnableSR=0 GENERATE
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SET_RESET0_sig <= '0';
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END GENERATE;
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SET_RESET1_sig <= SET_RESET0_sig;
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SET_RESET0 <= SET_RESET0_sig;
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SET_RESET1 <= SET_RESET1_sig;
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------------------------------------------------------------------
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------------------------------------------------------------------
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------------------------------------------------------------------
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--
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-- Cross domain clock synchronisation
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--
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------------------------------------------------------------------
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IF CDS =1 GENERATE
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AMR1Xsync: entity work.Fast2SlowSync
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generic map(N => 24)
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port map( AMR1X_Sync,clk,sclk,SyncSig,AMR1X);
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AMR1Ysync: entity work.Fast2SlowSync
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generic map(N => 24)
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port map( AMR1Y_Sync,clk,sclk,SyncSig,AMR1Y);
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AMR1Zsync: entity work.Fast2SlowSync
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generic map(N => 24)
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port map( AMR1Z_Sync,clk,sclk,SyncSig,AMR1Z);
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AMR2Xsync: entity work.Fast2SlowSync
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generic map(N => 24)
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port map( AMR2X_Sync,clk,sclk,SyncSig,AMR2X);
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AMR2Ysync: entity work.Fast2SlowSync
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generic map(N => 24)
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port map( AMR2Y_Sync,clk,sclk,SyncSig,AMR2Y);
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AMR2Zsync: entity work.Fast2SlowSync
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generic map(N => 24)
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port map( AMR2Z_Sync,clk,sclk,SyncSig,AMR2Z);
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AMR3Xsync: entity work.Fast2SlowSync
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generic map(N => 24)
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port map( AMR3X_Sync,clk,sclk,SyncSig,AMR3X);
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AMR3Ysync: entity work.Fast2SlowSync
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generic map(N => 24)
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port map( AMR3Y_Sync,clk,sclk,SyncSig,AMR3Y);
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AMR3Zsync: entity work.Fast2SlowSync
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generic map(N => 24)
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port map( AMR3Z_Sync,clk,sclk,SyncSig,AMR3Z);
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AMR4Xsync: entity work.Fast2SlowSync
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generic map(N => 24)
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port map( AMR4X_Sync,clk,sclk,SyncSig,AMR4X);
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AMR4Ysync: entity work.Fast2SlowSync
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generic map(N => 24)
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port map( AMR4Y_Sync,clk,sclk,SyncSig,AMR4Y);
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AMR4Zsync: entity work.Fast2SlowSync
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generic map(N => 24)
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port map( AMR4Z_Sync,clk,sclk,SyncSig,AMR4Z);
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TEMP1sync: entity work.Fast2SlowSync
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generic map(N => 24)
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port map( TEMP1_Sync,clk,sclk,SyncSig,TEMP1);
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TEMP2sync: entity work.Fast2SlowSync
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generic map(N => 24)
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port map( TEMP2_Sync,clk,sclk,SyncSig,TEMP2);
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TEMP3sync: entity work.Fast2SlowSync
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generic map(N => 24)
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port map( TEMP3_Sync,clk,sclk,SyncSig,TEMP3);
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TEMP4sync: entity work.Fast2SlowSync
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generic map(N => 24)
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port map( TEMP4_Sync,clk,sclk,SyncSig,TEMP4);
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END GENERATE;
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IF CDS /= 1 GENERATE
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AMR1X_Sync <= AMR1X;
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AMR1Y_Sync <= AMR1Y;
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AMR1Z_Sync <= AMR1Z;
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AMR2X_Sync <= AMR2X;
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AMR2Y_Sync <= AMR2Y;
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AMR2Z_Sync <= AMR2Z;
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Temp1_Sync <= Temp1;
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Temp2_Sync <= Temp2;
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AMR3X_Sync <= AMR3X;
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AMR3Y_Sync <= AMR3Y;
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AMR3Z_Sync <= AMR3Z;
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AMR4X_Sync <= AMR4X;
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AMR4Y_Sync <= AMR4Y;
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AMR4Z_Sync <= AMR4Z;
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Temp3_Sync <= Temp3;
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Temp4_Sync <= Temp4;
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END GENERATE;
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------------------------------------------------------------------
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end Behavioral;
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