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--------------------------------------------------------------------------------
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-- File name: gen_utils.vhd
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--------------------------------------------------------------------------------
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-- Copyright (C) 1996, 1998, 2001 Free Model Foundry; http://eda.org/fmf/
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License version 2 as
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-- published by the Free Software Foundation.
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--
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-- MODIFICATION HISTORY:
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--
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-- version: | author: | mod date: | changes made:
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-- V1.0 R. Steele 96 SEP 26 Initial release
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-- V1.1 REV3 97 Feb 27 Added Xon and MsgOn generics
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-- V1.2 R. Steele 97 APR 16 Changed wired-or to wired-and
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-- V1.3 R. Steele 97 APR 16 Added diff. receiver table
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-- V1.4 R. Munden 98 APR 13 Added GenParity and CheckParity
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-- V1.5 R. Munden 01 NOV 24 Added UnitDelay01ZX
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--
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--------------------------------------------------------------------------------
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LIBRARY IEEE; USE IEEE.std_Logic_1164.ALL;
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USE IEEE.VITAL_primitives.ALL;
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USE IEEE.VITAL_timing.ALL;
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PACKAGE gen_utils IS
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----------------------------------------------------------------------------
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-- Result map for Wired-and output values (open collector)
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----------------------------------------------------------------------------
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CONSTANT STD_wired_and_rmap : VitalResultMapType := ('U','X','0','Z');
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----------------------------------------------------------------------------
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-- Table for computing a single signal from a differential receiver input
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-- pair.
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----------------------------------------------------------------------------
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CONSTANT diff_rec_tab : VitalStateTableType := (
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------INPUTS--|-PREV-|-OUTPUT----
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-- A ANeg | Aint | Aint' --
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--------------|------|-----------
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( 'X', '-', '-', 'X'), -- A unknown
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( '-', 'X', '-', 'X'), -- A unknown
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( '1', '-', 'X', '1'), -- Recover from 'X'
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( '0', '-', 'X', '0'), -- Recover from 'X'
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( '/', '0', '0', '1'), -- valid diff. rising edge
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( '1', '\', '0', '1'), -- valid diff. rising edge
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( '\', '1', '1', '0'), -- valid diff. falling edge
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( '0', '/', '1', '0'), -- valid diff. falling edge
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( '-', '-', '-', 'S') -- default
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); -- end of VitalStateTableType definition
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----------------------------------------------------------------------------
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-- Default Constants
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----------------------------------------------------------------------------
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CONSTANT UnitDelay : VitalDelayType := 1 ns;
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CONSTANT UnitDelay01 : VitalDelayType01 := (1 ns, 1 ns);
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CONSTANT UnitDelay01Z : VitalDelayType01Z := (others => 1 ns);
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CONSTANT UnitDelay01ZX : VitalDelayType01ZX := (others => 1 ns);
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CONSTANT DefaultInstancePath : STRING := "*";
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CONSTANT DefaultTimingChecks : BOOLEAN := FALSE;
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CONSTANT DefaultTimingModel : STRING := "UNIT";
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CONSTANT DefaultXon : BOOLEAN := TRUE;
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CONSTANT DefaultMsgOn : BOOLEAN := TRUE;
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-- Older VITAL generic being phased out
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CONSTANT DefaultXGeneration : BOOLEAN := TRUE;
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-------------------------------------------------------------------
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-- Generate Parity for each 8-bit in 9th bit
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-------------------------------------------------------------------
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FUNCTION GenParity
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(Data : in std_logic_vector; -- Data
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ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
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SIZE : in POSITIVE) -- Bit Size
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RETURN std_logic_vector;
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-------------------------------------------------------------------
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-- Check Parity for each 8-bit in 9th bit
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-------------------------------------------------------------------
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FUNCTION CheckParity
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(Data : in std_logic_vector; -- Data
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ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
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SIZE : in POSITIVE) -- Bit Size
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RETURN std_logic; -- '0' - Parity Error
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END gen_utils;
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PACKAGE BODY gen_utils IS
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function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
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-- pragma subpgm_id 403
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variable result: STD_LOGIC;
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begin
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result := '0';
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for i in ARG'range loop
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result := result xor ARG(i);
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end loop;
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return result;
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end;
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-------------------------------------------------------------------
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-- Generate Parity for each 8-bit in 9th bit
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-------------------------------------------------------------------
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FUNCTION GenParity
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(Data : in std_logic_vector; -- Data
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ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
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SIZE : in POSITIVE) -- Bit Size
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RETURN std_logic_vector
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IS
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VARIABLE I: NATURAL;
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VARIABLE Result: std_logic_vector (Data'Length - 1 DOWNTO 0);
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BEGIN
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I := 0;
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WHILE (I < SIZE) LOOP
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Result(I+7 DOWNTO I) := Data(I+7 downto I);
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Result(I+8) := XOR_REDUCE( Data(I+7 downto I) ) XOR ODDEVEN;
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I := I + 9;
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END LOOP;
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RETURN Result;
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END GenParity;
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-------------------------------------------------------------------
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-- Check Parity for each 8-bit in 9th bit
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-------------------------------------------------------------------
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FUNCTION CheckParity
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(Data : in std_logic_vector; -- Data
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ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
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SIZE : in POSITIVE) -- Bit Size
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RETURN std_logic -- '0' - Parity Error
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IS
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VARIABLE I: NATURAL;
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VARIABLE Result: std_logic;
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BEGIN
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I := 0; Result := '1';
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WHILE (I < SIZE) LOOP
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Result := Result AND
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NOT (XOR_REDUCE( Data(I+8 downto I) ) XOR ODDEVEN);
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I := I + 9;
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END LOOP;
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RETURN Result;
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END CheckParity;
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END gen_utils;
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