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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.vital_timing.ALL;
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USE ieee.vital_primitives.ALL;
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library fmf;
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use fmf.gen_utils.all;
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use fmf.conversions.all;
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package flash is
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component s25fl064a
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generic (
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tipd_SCK : VitalDelayType01 := VitalZeroDelay01;
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tipd_SI : VitalDelayType01 := VitalZeroDelay01;
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tipd_CSNeg : VitalDelayType01 := VitalZeroDelay01;
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tipd_HOLDNeg : VitalDelayType01 := VitalZeroDelay01;
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tipd_WNeg : VitalDelayType01 := VitalZeroDelay01;
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tpd_SCK_SO : VitalDelayType01Z := UnitDelay01Z;
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tpd_CSNeg_SO : VitalDelayType01Z := UnitDelay01Z;
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tpd_HOLDNeg_SO : VitalDelayType01Z := UnitDelay01Z;
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tsetup_SI_SCK : VitalDelayType := UnitDelay;
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tsetup_CSNeg_SCK : VitalDelayType := UnitDelay;
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tsetup_HOLDNeg_SCK : VitalDelayType := UnitDelay;
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tsetup_WNeg_CSNeg : VitalDelayType := UnitDelay;
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thold_SI_SCK : VitalDelayType := UnitDelay;
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thold_CSNeg_SCK : VitalDelayType := UnitDelay;
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thold_HOLDNeg_SCK : VitalDelayType := UnitDelay;
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thold_WNeg_CSNeg : VitalDelayType := UnitDelay;
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tpw_SCK_posedge : VitalDelayType := UnitDelay;
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tpw_SCK_negedge : VitalDelayType := UnitDelay;
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tpw_CSNeg_posedge : VitalDelayType := UnitDelay;
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tperiod_SCK_rd : VitalDelayType := UnitDelay;
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tperiod_SCK_fast_rd : VitalDelayType := UnitDelay;
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tdevice_PP : VitalDelayType := 3 ms;
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tdevice_SE : VitalDelayType := 3 sec;
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tdevice_BE : VitalDelayType := 384 sec;
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tdevice_WR : VitalDelayType := 60 ms;
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tdevice_DP : VitalDelayType := 3 us;
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tdevice_RES : VitalDelayType := 30 us;
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tdevice_PU : VitalDelayType := 10 ms;
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InstancePath : STRING := DefaultInstancePath;
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TimingChecksOn : BOOLEAN := DefaultTimingChecks;
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MsgOn : BOOLEAN := DefaultMsgOn;
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XOn : BOOLEAN := DefaultXon;
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mem_file_name : STRING := "s25fl064a.mem";
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UserPreload : BOOLEAN := FALSE;
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LongTimming : BOOLEAN := TRUE;
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TimingModel : STRING := DefaultTimingModel
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);
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port (
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SCK : IN std_ulogic := 'U';
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SI : IN std_ulogic := 'U';
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CSNeg : IN std_ulogic := 'U';
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HOLDNeg : IN std_ulogic := 'U';
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WNeg : IN std_ulogic := 'U';
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SO : OUT std_ulogic := 'U'
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);
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end component;
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component m25p80
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generic (
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tipd_C : VitalDelayType01 := VitalZeroDelay01;
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tipd_D : VitalDelayType01 := VitalZeroDelay01;
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tipd_SNeg : VitalDelayType01 := VitalZeroDelay01;
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tipd_HOLDNeg : VitalDelayType01 := VitalZeroDelay01;
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tipd_WNeg : VitalDelayType01 := VitalZeroDelay01;
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tpd_C_Q : VitalDelayType01 := UnitDelay01;
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tpd_SNeg_Q : VitalDelayType01Z := UnitDelay01Z;
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tpd_HOLDNeg_Q : VitalDelayType01Z := UnitDelay01Z;
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tsetup_D_C : VitalDelayType := UnitDelay;
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tsetup_SNeg_C : VitalDelayType := UnitDelay;
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tsetup_HOLDNeg_C : VitalDelayType := UnitDelay;
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tsetup_C_HOLDNeg : VitalDelayType := UnitDelay;
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tsetup_WNeg_SNeg : VitalDelayType := UnitDelay;
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thold_D_C : VitalDelayType := UnitDelay;
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thold_SNeg_C : VitalDelayType := UnitDelay;
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thold_HOLDNeg_C : VitalDelayType := UnitDelay;
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thold_C_HOLDNeg : VitalDelayType := UnitDelay;
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thold_WNeg_SNeg : VitalDelayType := UnitDelay;
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tpw_C_posedge : VitalDelayType := UnitDelay;
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tpw_C_negedge : VitalDelayType := UnitDelay;
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tpw_SNeg_posedge : VitalDelayType := UnitDelay;
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tperiod_C_rd : VitalDelayType := UnitDelay;
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tperiod_C_fast_rd : VitalDelayType := UnitDelay;
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tdevice_PP : VitalDelayType := 5 ms;
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tdevice_SE : VitalDelayType := 3 sec;
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tdevice_BE : VitalDelayType := 20 sec;
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tdevice_WR : VitalDelayType := 15 ms;
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tdevice_DP : VitalDelayType := 3 us;
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tdevice_RES1 : VitalDelayType := 3 us;
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tdevice_RES2 : VitalDelayType := 1.8 us;
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tdevice_VSL : VitalDelayType := 10 us;
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tdevice_PUW : VitalDelayType := 10 ms;
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InstancePath : STRING := DefaultInstancePath;
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TimingChecksOn : BOOLEAN := DefaultTimingChecks;
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MsgOn : BOOLEAN := DefaultMsgOn;
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XOn : BOOLEAN := DefaultXon;
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mem_file_name : STRING := "m25p80.mem";
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UserPreload : BOOLEAN := FALSE;
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DebugInfo : BOOLEAN := FALSE;
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LongTimming : BOOLEAN := TRUE;
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TimingModel : STRING := DefaultTimingModel
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);
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port (
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C : IN std_ulogic := 'U';
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D : IN std_ulogic := 'U';
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SNeg : IN std_ulogic := 'U';
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HOLDNeg : IN std_ulogic := 'U';
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WNeg : IN std_ulogic := 'U';
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Q : OUT std_ulogic := 'U'
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);
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end component;
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end flash;
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