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Update and debug UART
Update and debug UART

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modelsim.ini.sav
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[Library]
others = $MODEL_TECH/../modelsim.ini
proasic3 = C:/Actel/Libero_v9.1/Designer/lib/modelsim/precompiled/vhdl/proasic3
syncad_vhdl_lib = C:\Actel\Libero_v9.1\Designer/lib/actel/syncad_vhdl_lib
[vcom]
VHDL93 = 1
[vsim]
IterationLimit = 5000