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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: net
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-- File: net.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: Package with component and type declarations for network cores
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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package net is
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type eth_in_type is record
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gtx_clk : std_ulogic;
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rmii_clk : std_ulogic;
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tx_clk : std_ulogic;
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rx_clk : std_ulogic;
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rxd : std_logic_vector(7 downto 0);
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rx_dv : std_ulogic;
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rx_er : std_ulogic;
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rx_col : std_ulogic;
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rx_crs : std_ulogic;
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mdio_i : std_ulogic;
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mdint : std_ulogic;
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phyrstaddr : std_logic_vector(4 downto 0);
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edcladdr : std_logic_vector(3 downto 0);
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edclsepahb : std_ulogic;
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edcldisable: std_ulogic;
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end record;
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constant eth_in_none : eth_in_type :=
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('0', '0', '0', '0', (others => '0'), '0', '0', '0', '0',
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'0', '0', (others => '0'), (others => '0'), '0', '0');
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type eth_out_type is record
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reset : std_ulogic;
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txd : std_logic_vector(7 downto 0);
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tx_en : std_ulogic;
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tx_er : std_ulogic;
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mdc : std_ulogic;
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mdio_o : std_ulogic;
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mdio_oe : std_ulogic;
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end record;
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constant eth_out_none : eth_out_type :=
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('0', (others => '0'), '0', '0', '0', '0', '1');
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component eth_arb
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generic(
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fullduplex : integer := 0;
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mdiomaster : integer := 0);
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port(
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rst : in std_logic;
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clk : in std_logic;
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ethi : in eth_in_type;
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etho : out eth_out_type;
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methi : in eth_out_type;
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metho : out eth_in_type;
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dethi : in eth_out_type;
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detho : out eth_in_type
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);
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end component;
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component greth is
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generic(
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hindex : integer := 0;
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#FFF#;
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pirq : integer := 0;
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memtech : integer := 0;
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ifg_gap : integer := 24;
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attempt_limit : integer := 16;
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backoff_limit : integer := 10;
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slot_time : integer := 128;
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mdcscaler : integer range 0 to 255 := 25;
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enable_mdio : integer range 0 to 1 := 0;
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fifosize : integer range 4 to 512 := 8;
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nsync : integer range 1 to 2 := 2;
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edcl : integer range 0 to 3 := 0;
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edclbufsz : integer range 1 to 64 := 1;
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macaddrh : integer := 16#00005E#;
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macaddrl : integer := 16#000000#;
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ipaddrh : integer := 16#c0a8#;
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ipaddrl : integer := 16#0035#;
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phyrstadr : integer range 0 to 32 := 0;
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rmii : integer range 0 to 1 := 0;
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oepol : integer range 0 to 1 := 0;
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scanen : integer range 0 to 1 := 0;
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ft : integer range 0 to 2 := 0;
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edclft : integer range 0 to 2 := 0;
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mdint_pol : integer range 0 to 1 := 0;
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enable_mdint : integer range 0 to 1 := 0;
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multicast : integer range 0 to 1 := 0;
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ramdebug : integer range 0 to 2 := 0);
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbmi : in ahb_mst_in_type;
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ahbmo : out ahb_mst_out_type;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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ethi : in eth_in_type;
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etho : out eth_out_type
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);
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end component;
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component greth_mb is
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generic(
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hindex : integer := 0;
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ehindex : integer := 0;
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#FFF#;
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pirq : integer := 0;
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memtech : integer := 0;
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ifg_gap : integer := 24;
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attempt_limit : integer := 16;
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backoff_limit : integer := 10;
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slot_time : integer := 128;
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mdcscaler : integer range 0 to 255 := 25;
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enable_mdio : integer range 0 to 1 := 0;
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fifosize : integer range 4 to 512 := 8;
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nsync : integer range 1 to 2 := 2;
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edcl : integer range 0 to 3 := 0;
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edclbufsz : integer range 1 to 64 := 1;
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macaddrh : integer := 16#00005E#;
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macaddrl : integer := 16#000000#;
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ipaddrh : integer := 16#c0a8#;
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ipaddrl : integer := 16#0035#;
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phyrstadr : integer range 0 to 32 := 0;
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rmii : integer range 0 to 1 := 0;
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oepol : integer range 0 to 1 := 0;
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scanen : integer range 0 to 1 := 0;
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ft : integer range 0 to 2 := 0;
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edclft : integer range 0 to 2 := 0;
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mdint_pol : integer range 0 to 1 := 0;
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enable_mdint : integer range 0 to 1 := 0;
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multicast : integer range 0 to 1 := 0;
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edclsepahb : integer range 0 to 1 := 0;
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ramdebug : integer range 0 to 2 := 0);
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbmi : in ahb_mst_in_type;
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ahbmo : out ahb_mst_out_type;
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ahbmi2 : in ahb_mst_in_type;
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ahbmo2 : out ahb_mst_out_type;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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ethi : in eth_in_type;
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etho : out eth_out_type
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);
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end component;
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component greth_gbit_mb is
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generic(
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hindex : integer := 0;
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ehindex : integer := 0;
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#FFF#;
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pirq : integer := 0;
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memtech : integer := 0;
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ifg_gap : integer := 24;
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attempt_limit : integer := 16;
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backoff_limit : integer := 10;
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slot_time : integer := 128;
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mdcscaler : integer range 0 to 255 := 25;
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nsync : integer range 1 to 2 := 2;
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edcl : integer range 0 to 3 := 0;
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edclbufsz : integer range 1 to 64 := 1;
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burstlength : integer range 4 to 128 := 32;
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macaddrh : integer := 16#00005E#;
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macaddrl : integer := 16#000000#;
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ipaddrh : integer := 16#c0a8#;
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ipaddrl : integer := 16#0035#;
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phyrstadr : integer range 0 to 32 := 0;
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sim : integer range 0 to 1 := 0;
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oepol : integer range 0 to 1 := 0;
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scanen : integer range 0 to 1 := 0;
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ft : integer range 0 to 2 := 0;
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edclft : integer range 0 to 2 := 0;
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mdint_pol : integer range 0 to 1 := 0;
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enable_mdint : integer range 0 to 1 := 0;
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multicast : integer range 0 to 1 := 0;
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edclsepahb : integer range 0 to 1 := 0;
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ramdebug : integer range 0 to 2 := 0);
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbmi : in ahb_mst_in_type;
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ahbmo : out ahb_mst_out_type;
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ahbmi2 : in ahb_mst_in_type;
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ahbmo2 : out ahb_mst_out_type;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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ethi : in eth_in_type;
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etho : out eth_out_type
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);
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end component;
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component greth_gbit is
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generic(
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hindex : integer := 0;
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#FFF#;
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pirq : integer := 0;
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memtech : integer := 0;
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ifg_gap : integer := 24;
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attempt_limit : integer := 16;
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backoff_limit : integer := 10;
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slot_time : integer := 128;
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mdcscaler : integer range 0 to 255 := 25;
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nsync : integer range 1 to 2 := 2;
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edcl : integer range 0 to 3 := 0;
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edclbufsz : integer range 1 to 64 := 1;
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burstlength : integer range 4 to 128 := 32;
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macaddrh : integer := 16#00005E#;
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macaddrl : integer := 16#000000#;
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ipaddrh : integer := 16#c0a8#;
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ipaddrl : integer := 16#0035#;
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phyrstadr : integer range 0 to 32 := 0;
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sim : integer range 0 to 1 := 0;
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oepol : integer range 0 to 1 := 0;
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scanen : integer range 0 to 1 := 0;
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ft : integer range 0 to 2 := 0;
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edclft : integer range 0 to 2 := 0;
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mdint_pol : integer range 0 to 1 := 0;
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enable_mdint : integer range 0 to 1 := 0;
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multicast : integer range 0 to 1 := 0;
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ramdebug : integer range 0 to 2 := 0);
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbmi : in ahb_mst_in_type;
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ahbmo : out ahb_mst_out_type;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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ethi : in eth_in_type;
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etho : out eth_out_type
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);
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end component;
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component grethm
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generic(
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hindex : integer := 0;
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#FFF#;
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pirq : integer := 0;
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memtech : integer := 0;
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ifg_gap : integer := 24;
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attempt_limit : integer := 16;
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backoff_limit : integer := 10;
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slot_time : integer := 128;
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mdcscaler : integer range 0 to 255 := 25;
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enable_mdio : integer range 0 to 1 := 0;
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fifosize : integer range 4 to 64 := 8;
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nsync : integer range 1 to 2 := 2;
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edcl : integer range 0 to 3 := 0;
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edclbufsz : integer range 1 to 64 := 1;
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burstlength : integer range 4 to 128 := 32;
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macaddrh : integer := 16#00005E#;
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macaddrl : integer := 16#000000#;
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ipaddrh : integer := 16#c0a8#;
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ipaddrl : integer := 16#0035#;
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phyrstadr : integer range 0 to 32 := 0;
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rmii : integer range 0 to 1 := 0;
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sim : integer range 0 to 1 := 0;
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giga : integer range 0 to 1 := 0;
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oepol : integer range 0 to 1 := 0;
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scanen : integer range 0 to 1 := 0;
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ft : integer range 0 to 2 := 0;
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edclft : integer range 0 to 1 := 0;
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mdint_pol : integer range 0 to 1 := 0;
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enable_mdint : integer range 0 to 1 := 0;
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multicast : integer range 0 to 1 := 0;
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ramdebug : integer range 0 to 2 := 0);
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbmi : in ahb_mst_in_type;
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ahbmo : out ahb_mst_out_type;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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ethi : in eth_in_type;
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etho : out eth_out_type
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);
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end component;
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end;
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