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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library gaisler;
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use gaisler.net.all;
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library grlib;
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use grlib.amba.all;
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library techmap;
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use techmap.gencomp.all;
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package ethernet_mac is
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type eth_tx_in_type is record
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start : std_ulogic;
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valid : std_ulogic;
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data : std_logic_vector(31 downto 0);
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full_duplex : std_ulogic;
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length : std_logic_vector(10 downto 0);
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col : std_ulogic;
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crs : std_ulogic;
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read_ack : std_ulogic;
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end record;
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type eth_tx_out_type is record
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status : std_logic_vector(1 downto 0);
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done : std_ulogic;
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restart : std_ulogic;
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read : std_ulogic;
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tx_er : std_ulogic;
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tx_en : std_ulogic;
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txd : std_logic_vector(3 downto 0);
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end record;
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type eth_rx_in_type is record
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writeok : std_ulogic;
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rxen : std_ulogic;
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rx_dv : std_ulogic;
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rx_er : std_ulogic;
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rxd : std_logic_vector(3 downto 0);
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done_ack : std_ulogic;
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write_ack : std_ulogic;
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end record;
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type eth_rx_out_type is record
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write : std_ulogic;
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data : std_logic_vector(31 downto 0);
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done : std_ulogic;
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length : std_logic_vector(10 downto 0);
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status : std_logic_vector(2 downto 0);
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start : std_ulogic;
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end record;
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type eth_mdio_in_type is record
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mdioi : std_ulogic;
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write : std_ulogic;
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read : std_ulogic;
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mdiostart : std_ulogic;
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regadr : std_logic_vector(4 downto 0);
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phyadr : std_logic_vector(4 downto 0);
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data : std_logic_vector(15 downto 0);
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end record;
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type eth_mdio_out_type is record
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mdc : std_ulogic;
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mdioo : std_ulogic;
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mdioen : std_ulogic;
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data : std_logic_vector(15 downto 0);
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done : std_ulogic;
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error : std_ulogic;
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end record;
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type eth_tx_ahb_in_type is record
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req : std_ulogic;
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write : std_ulogic;
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addr : std_logic_vector(31 downto 0);
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data : std_logic_vector(31 downto 0);
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end record;
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type eth_tx_ahb_out_type is record
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grant : std_ulogic;
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data : std_logic_vector(31 downto 0);
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ready : std_ulogic;
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error : std_ulogic;
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retry : std_ulogic;
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end record;
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type eth_rx_ahb_in_type is record
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req : std_ulogic;
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write : std_ulogic;
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addr : std_logic_vector(31 downto 0);
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data : std_logic_vector(31 downto 0);
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end record;
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type eth_rx_ahb_out_type is record
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grant : std_ulogic;
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ready : std_ulogic;
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error : std_ulogic;
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retry : std_ulogic;
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data : std_logic_vector(31 downto 0);
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end record;
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type eth_rx_gbit_ahb_in_type is record
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req : std_ulogic;
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write : std_ulogic;
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addr : std_logic_vector(31 downto 0);
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data : std_logic_vector(31 downto 0);
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size : std_logic_vector(1 downto 0);
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end record;
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component eth_ahb_mst is
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generic(
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hindex : integer := 0;
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revision : integer := 0;
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irq : integer := 0);
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbmi : in ahb_mst_in_type;
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ahbmo : out ahb_mst_out_type;
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tmsti : in eth_tx_ahb_in_type;
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tmsto : out eth_tx_ahb_out_type;
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rmsti : in eth_rx_ahb_in_type;
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rmsto : out eth_rx_ahb_out_type
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);
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end component;
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component eth_ahb_mst_gbit is
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generic(
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hindex : integer := 0;
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revision : integer := 0;
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irq : integer := 0);
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbmi : in ahb_mst_in_type;
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ahbmo : out ahb_mst_out_type;
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tmsti : in eth_tx_ahb_in_type;
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tmsto : out eth_tx_ahb_out_type;
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rmsti : in eth_rx_gbit_ahb_in_type;
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rmsto : out eth_rx_ahb_out_type
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);
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end component;
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end package;
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