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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library lpp;
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use lpp.lpp_ad_conv.all;
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use lpp.lpp_amba.all;
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use lpp.apb_devices_list.all;
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use lpp.general_purpose.all;
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use lpp.Rocket_PCM_Encoder.all;
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use lpp.iir_filter.all;
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use work.config.all;
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entity IIR_FILTER_TOP is
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generic
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(
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V2 : integer :=0 -- IF 1 uses V2 else use V1
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);
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port
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(
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rstn : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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SMPclk : IN STD_LOGIC;
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LF1_IN : IN std_logic_vector(15 downto 0);
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LF2_IN : IN std_logic_vector(15 downto 0);
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LF3_IN : IN std_logic_vector(15 downto 0);
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SMPCLKOut : OUT STD_LOGIC;
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LF1_OUT : OUT std_logic_vector(15 downto 0);
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LF2_OUT : OUT std_logic_vector(15 downto 0);
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LF3_OUT : OUT std_logic_vector(15 downto 0)
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);
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end IIR_FILTER_TOP;
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architecture AR_IIR_FILTER_TOP of IIR_FILTER_TOP is
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signal sps : Samples(2 DOWNTO 0);
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signal LFX : Samples(2 DOWNTO 0);
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signal Filter_sp_in : samplT(2 DOWNTO 0, 15 DOWNTO 0);
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signal Filter_sp_out : samplT(2 DOWNTO 0, 15 DOWNTO 0);
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signal sample_out_val : std_logic;
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signal LF_ADC_SpPulse : std_logic;
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begin
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sps(0) <= LF1_IN;
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sps(1) <= LF2_IN;
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sps(2) <= LF3_IN;
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LF1_OUT <= LFX(0);
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LF2_OUT <= LFX(1);
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LF3_OUT <= LFX(2);
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SMPCLKOut <= sample_out_val;
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loop_all_sample : FOR J IN 15 DOWNTO 0 GENERATE
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loop_all_chanel : FOR I IN 2 DOWNTO 0 GENERATE
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process(rstn,clk)
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begin
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if rstn ='0' then
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Filter_sp_in(I,J) <= '0';
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-- LFX(I) <= (others => '0');
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elsif clk'event and clk ='1' then
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if sample_out_val = '1' then
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LFX(I)(J) <= Filter_sp_out(I,J);
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Filter_sp_in(I,J) <= sps(I)(J);
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end if;
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end if;
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end process;
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END GENERATE;
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END GENERATE;
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V2FILTER: IF V2 = 1 GENERATE
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smpPulse: entity work.OneShot
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Port map(
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reset => rstn,
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clk => clk,
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input => SMPclk,
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output => LF_ADC_SpPulse
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);
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FilterV2: IIR_CEL_CTRLR_v2
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GENERIC map(
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tech => CFG_MEMTECH,
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Mem_use => use_RAM,
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Sample_SZ => Sample_SZ,
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Coef_SZ => Coef_SZ,
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Coef_Nb => 25,
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Coef_sel_SZ => 5,
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Cels_count => 5,
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ChanelsCount => ChanelsCount
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)
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PORT map(
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rstn => rstn,
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clk => clk,
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virg_pos => virgPos,
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coefs => CoefsInitValCst_v2,
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sample_in_val => LF_ADC_SpPulse,
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sample_in => Filter_sp_in,
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sample_out_val => sample_out_val,
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sample_out => Filter_sp_out
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);
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END GENERATE;
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V1FILTER: IF V2 /= 1 GENERATE
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sample_out_val <= SMPclk;
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FilterV1: IIR_CEL_CTRLR
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generic map(
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tech => CFG_MEMTECH,
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Sample_SZ => Sample_SZ,
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ChanelsCount => 3,
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Coef_SZ => Coef_SZ,
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CoefCntPerCel=> CoefCntPerCel,
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Cels_count => Cels_count,
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Mem_use => use_RAM
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)
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port map(
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reset => rstn,
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clk => clk,
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sample_clk => SMPclk,
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sample_in => Filter_sp_in,
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sample_out => Filter_sp_out,
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virg_pos => virgPos,
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GOtest => open,
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coefs => CoefsInitValCst
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);
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END GENERATE;
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end AR_IIR_FILTER_TOP;
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