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################################################################################
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# SDC WRITER VERSION "3.1";
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# DESIGN "LFR_EQM";
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# Timing constraints scenario: "Primary";
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# DATE "Fri Jul 24 14:50:40 2015";
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# VENDOR "Actel";
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# PROGRAM "Actel Designer Software Release v9.1 SP5";
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# VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
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################################################################################
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set sdc_version 1.7
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######## Clock Constraints ########
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create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
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create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
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create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_pad_25/U0:Y }
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create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
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create_clock -name { spw_inputloop.1.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_1:Y }
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create_clock -name { spw_inputloop.0.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_1:Y }
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######## Generated Clock Constraints ########
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######## Clock Source Latency Constraints #########
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######## Input Delay Constraints ########
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######## Output Delay Constraints ########
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set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address }]
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set_min_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 }]
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######## Delay Constraints ########
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######## Delay Constraints ########
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######## Multicycle Constraints ########
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######## False Path Constraints ########
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######## Output load Constraints ########
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######## Disable Timing Constraints #########
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######## Clock Uncertainty Constraints #########
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