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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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----------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE IEEE.std_logic_arith.ALL;
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USE IEEE.std_logic_signed.ALL;
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USE IEEE.MATH_real.ALL;
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ENTITY chirp IS
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GENERIC (
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LOW_FREQUENCY_LIMIT : INTEGER := 0;
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HIGH_FREQUENCY_LIMIT : INTEGER := 2000;
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NB_POINT_TO_GEN : INTEGER := 10000;
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AMPLITUDE : INTEGER := 100;
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NB_BITS : INTEGER := 16);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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data_ack : IN STD_LOGIC;
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data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
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);
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END chirp;
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ARCHITECTURE beh OF chirp IS
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SIGNAL reg : STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
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SIGNAL n : INTEGER;
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SIGNAL current_time : REAL := REAL(0);
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SIGNAL freq_chirp : REAL := REAL(0);
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BEGIN -- beh
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current_time <= REAL(n) / REAL(NB_POINT_TO_GEN);
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freq_chirp <= REAL(LOW_FREQUENCY_LIMIT) + (REAL(HIGH_FREQUENCY_LIMIT) - REAL(LOW_FREQUENCY_LIMIT))*current_time;
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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reg <= (OTHERS => '0');
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n <= 0;
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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IF run = '0' THEN
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reg <= (OTHERS => '0');
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n <= 0;
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ELSE
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IF data_ack = '1' THEN
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IF n < NB_POINT_TO_GEN THEN
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n <= n+1;
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reg <= conv_std_logic_vector(INTEGER(REAL(AMPLITUDE) * SIN(MATH_2_PI*current_time*freq_chirp)),NB_BITS);
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ELSE
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reg <= (OTHERS => '0');
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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data <= reg;
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END beh;
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