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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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-- pragma translate_off
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use std.textio.all;
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-- pragma translate_on
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library lpp;
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use lpp.lpp_amba.all;
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package lpp_uart is
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component UART is
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generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee
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port(
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clk : in std_logic; --! Horloge a 25Mhz du systeme
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reset : in std_logic; --! Reset du systeme
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TXD : out std_logic; --! Transmission, cote PC
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RXD : in std_logic; --! Reception, cote PC
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Capture : in std_logic; --! "Reset" cible pour le generateur de bauds, ici indissocie du reset global
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NwDat : out std_logic; --! Flag, Nouvelle donnee presente
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ACK : in std_logic; --! Flag, Reponse au flag precedent
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Send : in std_logic; --! Flag, Demande d'envoi sur le bus
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Sended : out std_logic; --! Flag, Envoi termine
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BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission
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RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Mot de donnee en provenance de l'utilisateur
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WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur
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);
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end component;
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component Shift_REG is
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generic(Data_sz : integer := 10);
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port(
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clk : in std_logic;
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Sclk : in std_logic;
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reset : in std_logic;
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SIN : in std_logic;
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SOUT : out std_logic;
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Serialize : in std_logic;
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Serialized : out std_logic;
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D : in std_logic_vector(Data_sz-1 downto 0);
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Q : out std_logic_vector(Data_sz-1 downto 0)
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);
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end component;
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component BaudGen is
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port(
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clk : in std_logic;
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reset : in std_logic;
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Capture : in std_logic;
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Bclk : out std_logic;
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RXD : in std_logic;
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BTrigger : out std_logic_vector(11 downto 0)
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);
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end component;
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component APB_UART is
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generic (
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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pirq : integer := 0;
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abits : integer := 8;
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Data_sz : integer := 8);
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port (
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clk : in std_logic;
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rst : in std_logic;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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TXD : out std_logic;
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RXD : in std_logic
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);
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end component;
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end lpp_uart;
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