##// END OF EJS Templates
Renamed em-LeonLPP-A3PE3kL-v3-core1 boards in LFR-EM boards...
Renamed em-LeonLPP-A3PE3kL-v3-core1 boards in LFR-EM boards Renamed LFR-em-WFP_MS designs in SOLO_LFR_LFR-EM designs Updated LFR-EM boards constraints => PDC file => SDC file for the place and route Updated SOLO_LFR_LFR-EM designs => added DATA_SHAPING_SATURATION in LPP_FILTER => changed boards number : LPP_LFR_BOARD_LFR_EM & X"015B"

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r639:5ffe6bd0368c default
r662:f19abbf47ea7 SOLO_LFR_01-5B (LFR-EM) default
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Makefile_RTAX.inc
41 lines | 733 B | text/x-povray | PovrayLexer
PACKAGE=CQFP352
SPEED=Std
SYNFREQ=50
TECHNOLOGY=Axcelerator
DESIGNER_PACKAGE=CQFP
DESIGNER_PINS=352
DESIGNER_VOLTAGE=COM
DESIGNER_TEMP=COM
#ifeq ("$(FPGA_RTAX4000)","S")
# LIBERO_DIE=70800rts
# PART=RTAX4000S
# LIBERO_PACKAGE=cqfp$(DESIGNER_PINS)r
#endif
#ifeq ("$(FPGA_RTAX4000)","D")
LIBERO_DIE=70800d
PART=RTAX4000D
LIBERO_PACKAGE=cq$(DESIGNER_PINS)
#endif
MANUFACTURER=Actel
MGCPART=$(PART)
MGCTECHNOLOGY=Axcelerator
MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
## RTAX4000S OPTIONS
#LIBERO_DIE=70800rts
#PART=RTAX4000S
## RTAX4000D OPTIONS
#LIBERO_DIE=70800d
#PART=RTAX4000D
# RTAX4000D
#LIBERO_PACKAGE=cq$(DESIGNER_PINS)
# RTAX4000S
#LIBERO_PACKAGE=cqfp$(DESIGNER_PINS)r