HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/ProjetBlanc-LeonLPP-M7A3P1k/top_synplify.qsf

LPP DMA v1.0.1...

LPP DMA v1.0.1 - Correction of bugs due to "AHB bursts and 1kB address boundary" - Add TB for DMA with a RTL model of the external RAM CYC1360C in designs/Projet-LeonLFR-AP3K-Sheldon_sim-all

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				# Project-Wide Assignments
				# ========================
				#set_global_assignment -name ORIGINAL_QUARTUS_VERSION "4.1 SP2"
				#set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:13:08 DECEMBER 01, 2004"

				# Explicitly disable TimeQuest since the GRLIB flow invokes the classical
				# timing analyzer and USE_TIMEQUEST_TIMING_ANALYZER defaults to "ON"
				# set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER "OFF"

				set_global_assignment -name VQM_FILE synplify/top.edf

				set_global_assignment -name TOP_LEVEL_ENTITY "top"

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