HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/ProjetBlanc-LeonLPP-M7A3P1k/top_synplify.npl

LPP DMA v1.0.1...

LPP DMA v1.0.1 - Correction of bugs due to "AHB bursts and 1kB address boundary" - Add TB for DMA with a RTL model of the external RAM CYC1360C in designs/Projet-LeonLFR-AP3K-Sheldon_sim-all

martin - - Load All Authors

File last commit:

r100:fc97c34d69e3 martin


                r102:ecadbe9f5050

Download file

             top_synplify.npl
        
                    20 lines
            
             | 694 B
            
                | text/plain
            
             |
                TextLexer

/ designs / ProjetBlanc-LeonLPP-M7A3P1k / top_synplify.npl

History | Annotation | Raw |Copy content |Copy permalink

				JDF G
				PROJECT top
				DESIGN top
				DEVFAM PROASIC3
				DEVICE PROASIC3
				DEVSPEED Std
				DEVPKG ""
				DEVTOPLEVELMODULETYPE EDIF
				DEVSIMULATOR Modelsim
				DEVGENERATEDSIMULATIONMODEL VHDL
				SOURCE synplify\top.edf
				DEPASSOC top ..\..\boards\Projet-Blanc-M7A3P1K\top.ucf
				[Normal]
				xilxMapAllowLogicOpt=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, True
				xilxMapCoverMode=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, Speed
				xilxNgdbld_AUL=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, True
				xilxPAReffortLevel=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, Medium
				xilxNgdbldMacro=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1105378344, ..\..\netlists\xilinx\PROASIC3
				[STRATEGY-LIST]
				Normal=True

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages