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library ieee;
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use ieee.std_logic_1164.all;
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USE IEEE.NUMERIC_STD.ALL;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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library techmap;
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use techmap.gencomp.all;
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use techmap.allclkgen.all;
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library gaisler;
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use gaisler.memctrl.all;
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use gaisler.leon3.all;
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use gaisler.uart.all;
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use gaisler.misc.all;
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--pragma translate_off
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use gaisler.sim.all;
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--pragma translate_on
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library opencores;
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use opencores.spwpkg.all;
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use opencores.spwambapkg.all;
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LIBRARY lpp;
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USE lpp.general_purpose.ALL;
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use lpp.lpp_amba.all;
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USE lpp.lpp_lfr_management.ALL;
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use work.config.all;
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library unisim;
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use unisim.vcomponents.all;
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entity leon3mp is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW
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);
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port (
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CLK50 : in std_logic;
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LEDS : inout std_logic_vector(7 downto 0);
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SW : in std_logic_vector(4 downto 1);
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dram_addr : out std_logic_vector(12 downto 0);
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dram_ba_0 : out std_logic;
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dram_ba_1 : out std_logic;
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dram_dq : inout std_logic_vector(15 downto 0);
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dram_clk : out std_logic;
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dram_cke : out std_logic;
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dram_cs_n : out std_logic;
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dram_we_n : out std_logic; -- sdram write enable
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dram_ras_n : out std_logic; -- sdram ras
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dram_cas_n : out std_logic; -- sdram cas
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dram_ldqm : out std_logic; -- sdram ldqm
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dram_udqm : out std_logic; -- sdram udqm
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uart_txd : out std_logic; -- DSU tx data
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uart_rxd : in std_logic; -- DSU rx data
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spw_rxdp : in std_logic;
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spw_rxdn : in std_logic;
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spw_rxsp : in std_logic;
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spw_rxsn : in std_logic;
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spw_txdp : out std_logic;
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spw_txdn : out std_logic;
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spw_txsp : out std_logic;
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spw_txsn : out std_logic
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);
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end;
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architecture rtl of leon3mp is
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signal resetn : std_logic;
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signal clkm, rstn, rstraw, rst : std_logic;
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signal clk_50 : std_logic := '0';
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signal clkm_inv : std_logic := '0';
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signal cptr : std_logic_vector(29 downto 0);
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constant BOARD_FREQ : integer := 25000; -- CLK input frequency in KHz
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constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
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signal sdi : sdctrl_in_type;
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signal sdo : sdctrl_out_type;
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--AMBA bus standard interface signals--
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signal apbi : apb_slv_in_type;
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signal apbo : apb_slv_out_vector := (others => apb_none);
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signal ahbsi : ahb_slv_in_type;
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signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
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signal ahbmi : ahb_mst_in_type;
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signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
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signal cgi : clkgen_in_type;
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signal cgo : clkgen_out_type;
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signal dui : uart_in_type;
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signal duo : uart_out_type;
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signal irqi : irq_in_vector(0 to CFG_NCPU-1);
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signal irqo : irq_out_vector(0 to CFG_NCPU-1);
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signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
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signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
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signal dsui : dsu_in_type;
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signal dsuo : dsu_out_type;
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signal gpti : gptimer_in_type;
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signal gpto : gptimer_out_type;
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signal gpioi_0 : gpio_in_type;
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signal gpioo_0 : gpio_out_type;
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signal dsubren : std_logic :='0';
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signal spw_di: std_logic;
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signal spw_si: std_logic;
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signal spw_do: std_logic;
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signal spw_so: std_logic;
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signal spw_tick_in: std_logic;
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signal spw_tick_out: std_logic;
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-- AdvancedTrigger
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SIGNAL Trigger : STD_LOGIC;
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SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
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component sdctrl16
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generic (
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hindex : integer := 0;
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haddr : integer := 0;
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hmask : integer := 16#f00#;
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ioaddr : integer := 16#000#;
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iomask : integer := 16#fff#;
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wprot : integer := 0;
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invclk : integer := 0;
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fast : integer := 0;
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pwron : integer := 0;
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sdbits : integer := 16;
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oepol : integer := 0;
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pageburst : integer := 0;
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mobile : integer := 0
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);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type;
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sdi : in sdctrl_in_type;
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sdo : out sdctrl_out_type
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);
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end component;
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begin
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resetn <= SW(1);
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clk_pad : clkpad generic map (tech => padtech) port map (CLK50, clk_50);
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process(clk_50)
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begin
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if clk_50'event and clk_50='1' then
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clkm <= not clkm;
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end if;
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end process;
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clkm_inv <= not clkm;
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resetn_pad : inpad generic map (tech => padtech) port map (resetn, rst);
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rst0 : rstgen -- reset generator (reset is active LOW)
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port map (rst, clkm, '1', rstn, rstraw);
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----------------------------------------------------------------------
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--- AHB CONTROLLER --------------------------------------------------
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----------------------------------------------------------------------
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ahb0 : ahbctrl -- AHB arbiter/multiplexer
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generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
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rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
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nahbm => CFG_NCPU+CFG_AHB_UART+1, nahbs => 8)
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port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
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----------------------------------------------------------------------
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----- LEON3 processor and DSU ---------------------------------------
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----------------------------------------------------------------------
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cpu : for i in 0 to CFG_NCPU-1 generate
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nosh : if CFG_GRFPUSH = 0 generate
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u0 : leon3s -- LEON3 processor
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generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
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0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
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CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
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CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
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CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
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CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
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0, 0, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
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port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
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irqi(i), irqo(i), dbgi(i), dbgo(i));
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end generate;
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end generate;
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--ledr[0] lit when leon 3 debugvector signals error
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dsugen : if CFG_DSU = 1 generate
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dsu0 : dsu3 -- LEON3 Debug Support Unit (slave)
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generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
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ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
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port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
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dsui.enable <= '1';
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end generate;
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nodsu : if CFG_DSU = 0 generate
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ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; --no timer freeze, no light.
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end generate;
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dcomgen : if CFG_AHB_UART = 1 generate
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dcom0: ahbuart -- Debug UART
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generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
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port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
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end generate;
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uart_txd <= duo.txd;
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dui.rxd <= uart_rxd;
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----------------------------------------------------------------------
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--- Memory controllers ----------------------------------------------
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----------------------------------------------------------------------
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sdc : sdctrl16 generic map (hindex => 3, haddr => 16#400#, hmask => 16#FE0#, -- hmask => 16#C00#,
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ioaddr => 1, fast => 0, pwron => 0, invclk => 0,
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sdbits => 16, pageburst => 2)
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port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo);
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sa_pad : outpadv generic map (width => 13, tech => padtech)
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port map (dram_addr, sdo.address(14 downto 2));
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ba0_pad : outpad generic map (tech => padtech)
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port map (dram_ba_0, sdo.address(15));
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ba1_pad : outpad generic map (tech => padtech)
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port map (dram_ba_1, sdo.address(16));
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sd_pad : iopadvv generic map (width => 16, tech => padtech)
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port map (dram_dq(15 downto 0), sdo.data(15 downto 0), sdo.vbdrive(15 downto 0), sdi.data(15 downto 0));
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sdcke_pad : outpad generic map (tech => padtech)
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port map (dram_cke, sdo.sdcke(0));
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sdwen_pad : outpad generic map (tech => padtech)
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port map (dram_we_n, sdo.sdwen);
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sdcsn_pad : outpad generic map (tech => padtech)
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port map (dram_cs_n, sdo.sdcsn(0));
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sdras_pad : outpad generic map (tech => padtech)
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port map (dram_ras_n, sdo.rasn);
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sdcas_pad : outpad generic map (tech => padtech)
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port map (dram_cas_n, sdo.casn);
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sdldqm_pad : outpad generic map (tech => padtech)
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port map (dram_ldqm, sdo.dqm(0) );
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sdudqm_pad : outpad generic map (tech => padtech)
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port map (dram_udqm, sdo.dqm(1));
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dram_clk_pad : outpad generic map (tech => padtech)
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port map (dram_clk, clkm_inv);
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----------------------------------------------------------------------
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--- APB Bridge and various periherals -------------------------------
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----------------------------------------------------------------------
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apb0 : apbctrl -- AHB/APB bridge
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generic map (hindex => 1, haddr => CFG_APBADDR)
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port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
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----------------------------------------------------------------------------------------
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irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
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irqctrl0 : irqmp -- interrupt controller
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generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
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port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
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end generate;
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irq3 : if CFG_IRQ3_ENABLE = 0 generate
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x : for i in 0 to CFG_NCPU-1 generate irqi(i).irl <= "0000"; end generate;
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apbo(2) <= apb_none;
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end generate;
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--Timer unit, generates interrupts when a timer underflow.
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gpt : if CFG_GPT_ENABLE /= 0 generate
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timer0 : gptimer -- timer unit
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generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
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sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
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nbits => CFG_GPT_TW)
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port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
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gpti <= gpti_dhalt_drive(dsuo.tstop);
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end generate;
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notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
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gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO0 unit
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grgpio0: grgpio
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generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK, nbits => 4)
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port map( rstn, clkm, apbi, apbo(9), gpioi_0, gpioo_0);
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pio_pads : for i in 0 to 3 generate
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pio_pad : iopad generic map (tech => padtech)
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port map (LEDS(i), gpioo_0.dout(i), gpioo_0.oen(i), gpioi_0.din(i));
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end generate;
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end generate;
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nogpio0: if CFG_GRGPIO_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
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-------------------------------------------------------------------------------
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-- APB_LFR_MANAGEMENT ---------------------------------------------------------
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-------------------------------------------------------------------------------
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apb_lfr_management_1 : apb_lfr_management
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GENERIC MAP (
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tech => fabtech,
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pindex => 6,
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paddr => 6,
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pmask => 16#fff#,
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NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
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PORT MAP (
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clk25MHz => clkm,
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resetn_25MHz => rstn,
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grspw_tick => spw_tick_out,
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apbi => apbi,
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apbo => apbo(6),
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HK_sample => X"0000",
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HK_val => '0',
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HK_sel => OPEN,
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DAC_SDO => OPEN,
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DAC_SCK => OPEN,
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DAC_SYNC => OPEN,
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DAC_CAL_EN => OPEN,
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coarse_time => coarse_time,
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fine_time => fine_time,
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LFR_soft_rstn => OPEN
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);
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----------------------------------------------------------------------
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--- APB_ADVANCED_TRIGGER -----------------------------------------------------------
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----------------------------------------------------------------------
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advtrig0: APB_ADVANCED_TRIGGER
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generic map(
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pindex => 5,
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paddr => 5)
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port map(
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rstn => rstn,
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clk => clkm,
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apbi => apbi,
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apbo => apbo(5),
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SPW_Tickout => spw_tick_out,
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CoarseTime => coarse_time,
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FineTime => fine_time,
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Trigger => Trigger
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);
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DISCO1_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
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PORT MAP (LEDS(4), Trigger);
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DISCO2_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
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PORT MAP (LEDS(5), Trigger);
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DISCO3_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
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PORT MAP (LEDS(6), Trigger);
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DISCO4_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
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PORT MAP (LEDS(7), Trigger);
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-----------------------------------------------------------------------
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--- SpaceWire Light --------------------------------------------------
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-----------------------------------------------------------------------
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spw0: spwamba
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generic map (
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tech => memtech,
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hindex => 2,
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pindex => 10,
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paddr => 10,
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pirq => 10,
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sysfreq => 25.0e6,
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txclkfreq => 50.0e6,
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rximpl => impl_fast,
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rxchunk => 1,
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tximpl => impl_fast,
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timecodegen => true,
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rxfifosize => 11,
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txfifosize => 11,
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desctablesize => 10,
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maxburst => 3 )
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port map (
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clk => clkm,
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rxclk => clk_50,
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txclk => clk_50,
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rstn => rstn,
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apbi => apbi,
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apbo => apbo(10),
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ahbi => ahbmi,
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ahbo => ahbmo(2),
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|
tick_in => spw_tick_in,
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tick_out => spw_tick_out,
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|
spw_di => spw_di,
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|
spw_si => spw_si,
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|
spw_do => spw_do,
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|
spw_so => spw_so );
|
|
|
|
|
|
spw_tick_in <= gpto.tick(2) when CFG_GPT_ENABLE /= 0 else '0';
|
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|
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spw_rxd_pad: inpad_ds
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generic map (padtech, lvds, x33v)
|
|
|
port map (spw_rxdp, spw_rxdn, spw_di);
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|
|
spw_rxs_pad: inpad_ds
|
|
|
generic map (padtech, lvds, x33v)
|
|
|
port map (spw_rxsp, spw_rxsn, spw_si);
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|
|
-- spw_txd_pad: outpad_ds
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|
|
-- generic map (padtech, lvds, x33v)
|
|
|
-- port map (spw_txdp, spw_txdn, spw_do, '0');
|
|
|
-- spw_txs_pad: outpad_ds
|
|
|
-- generic map (padtech, lvds, x33v)
|
|
|
-- port map (spw_txsp, spw_txsn, spw_so, '0');
|
|
|
|
|
|
|
|
|
spw_txdp_pad : outpad generic map (tech => padtech)
|
|
|
port map (spw_txdp, spw_do);
|
|
|
spw_txdn_pad : outpad generic map (tech => padtech)
|
|
|
port map (spw_txdn, not spw_do);
|
|
|
|
|
|
spw_txsp_pad : outpad generic map (tech => padtech)
|
|
|
port map (spw_txsp, spw_so);
|
|
|
spw_txsn_pad : outpad generic map (tech => padtech)
|
|
|
port map (spw_txsn, not spw_so);
|
|
|
|
|
|
end rtl;
|
|
|
|
|
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|
