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diff -Naur mig.org/mig_38/user_design/rtl/memc3_infrastructure.vhd mig/mig_38/user_design/rtl/memc3_infrastructure.vhd
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--- mig.org/mig_38/user_design/rtl/memc3_infrastructure.vhd 2011-12-30 20:07:53.000000000 +0100
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+++ mig/mig_38/user_design/rtl/memc3_infrastructure.vhd 2012-01-02 14:05:44.000000000 +0100
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@@ -95,7 +95,9 @@
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mcb_drp_clk : out std_logic;
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pll_ce_0 : out std_logic;
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pll_ce_90 : out std_logic;
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- pll_lock : out std_logic
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+ pll_lock : out std_logic;
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+ clk_125 : out std_logic;
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+ clk_50 : out std_logic
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);
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end entity;
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@@ -121,6 +123,8 @@
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signal clk0_bufg_in : std_logic;
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signal mcb_drp_clk_bufg_in : std_logic;
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signal clkfbout_clkfbin : std_logic;
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+ signal clkfbout_clkfbin2 : std_logic;
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+ signal clk_50i, clk_125i : std_logic;
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signal rst_tmp : std_logic;
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signal sys_clk_ibufg : std_logic;
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signal sys_rst : std_logic;
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@@ -330,5 +334,73 @@
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LOCK => bufpll_mcb_locked
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);
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+
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+ -- second PLL to generate 125 MHz for giga-bit MAC and 50 MHz for VGA
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+ u_pll_adv2 : PLL_ADV
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+ generic map
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+ (
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+ BANDWIDTH => "OPTIMIZED",
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+ CLKIN1_PERIOD => CLK_PERIOD_NS,
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+ CLKIN2_PERIOD => CLK_PERIOD_NS,
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+ CLKOUT0_DIVIDE => 8, -- 125 MHz
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+ CLKOUT1_DIVIDE => 20, -- 50 MHz
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+ CLKOUT2_DIVIDE => C_CLKOUT2_DIVIDE,
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+ CLKOUT3_DIVIDE => C_CLKOUT3_DIVIDE,
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+ CLKOUT4_DIVIDE => 1,
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+ CLKOUT5_DIVIDE => 1,
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+ CLKOUT0_PHASE => 0.000,
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+ CLKOUT1_PHASE => 0.000,
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+ CLKOUT2_PHASE => 0.000,
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+ CLKOUT3_PHASE => 0.000,
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+ CLKOUT4_PHASE => 0.000,
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+ CLKOUT5_PHASE => 0.000,
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+ CLKOUT0_DUTY_CYCLE => 0.500,
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+ CLKOUT1_DUTY_CYCLE => 0.500,
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+ CLKOUT2_DUTY_CYCLE => 0.500,
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+ CLKOUT3_DUTY_CYCLE => 0.500,
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+ CLKOUT4_DUTY_CYCLE => 0.500,
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+ CLKOUT5_DUTY_CYCLE => 0.500,
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+ SIM_DEVICE => "SPARTAN6",
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+ COMPENSATION => "INTERNAL",
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+ DIVCLK_DIVIDE => 1,
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+ CLKFBOUT_MULT => 5, -- 1000 MHz
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+ CLKFBOUT_PHASE => 0.0,
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+ REF_JITTER => 0.005000
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+ )
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+ port map
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+ (
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+ CLKFBIN => clkfbout_clkfbin2,
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+ CLKINSEL => '1',
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+ CLKIN1 => sys_clk_ibufg,
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+ CLKIN2 => '0',
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+ DADDR => (others => '0'),
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+ DCLK => '0',
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+ DEN => '0',
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+ DI => (others => '0'),
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+ DWE => '0',
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+ REL => '0',
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+ RST => sys_rst,
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+ CLKFBDCM => open,
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+ CLKFBOUT => clkfbout_clkfbin2,
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+ CLKOUTDCM0 => open,
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+ CLKOUTDCM1 => open,
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+ CLKOUTDCM2 => open,
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+ CLKOUTDCM3 => open,
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+ CLKOUTDCM4 => open,
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+ CLKOUTDCM5 => open,
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+ CLKOUT0 => clk_125i,
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+ CLKOUT1 => clk_50i,
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+ CLKOUT2 => open,
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+ CLKOUT3 => open,
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+ CLKOUT4 => open,
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+ CLKOUT5 => open,
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+ DO => open,
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+ DRDY => open,
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+ LOCKED => open
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+ );
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+
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+ U_BUFG_125 : BUFG port map ( O => clk_125, I => clk_125i);
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+ U_BUFG_50 : BUFG port map ( O => clk_50, I => clk_50i);
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+
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end architecture syn;
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diff -Naur mig.org/mig_38/user_design/rtl/mig_38.vhd mig/mig_38/user_design/rtl/mig_38.vhd
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--- mig.org/mig_38/user_design/rtl/mig_38.vhd 2011-12-30 20:07:53.000000000 +0100
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+++ mig/mig_38/user_design/rtl/mig_38.vhd 2012-01-02 12:42:40.000000000 +0100
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@@ -165,7 +165,9 @@
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c3_p2_rd_empty : out std_logic;
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c3_p2_rd_count : out std_logic_vector(6 downto 0);
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c3_p2_rd_overflow : out std_logic;
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- c3_p2_rd_error : out std_logic
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+ c3_p2_rd_error : out std_logic;
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+ clk_125 : out std_logic;
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+ clk_50 : out std_logic
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);
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end mig_38;
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@@ -198,8 +200,9 @@
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pll_ce_0 : out std_logic;
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pll_ce_90 : out std_logic;
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pll_lock : out std_logic;
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- mcb_drp_clk : out std_logic
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-
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+ mcb_drp_clk : out std_logic;
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+ clk_125 : out std_logic;
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+ clk_50 : out std_logic
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);
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end component;
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@@ -363,8 +366,8 @@
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constant C3_CLKOUT1_DIVIDE : integer := 1;
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constant C3_CLKOUT2_DIVIDE : integer := 16;
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constant C3_CLKOUT3_DIVIDE : integer := 8;
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- constant C3_CLKFBOUT_MULT : integer := 2;
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- constant C3_DIVCLK_DIVIDE : integer := 1;
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+ constant C3_CLKFBOUT_MULT : integer := 2*5;
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+ constant C3_DIVCLK_DIVIDE : integer := 1*3;
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constant C3_INCLK_PERIOD : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2));
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constant C3_ARB_NUM_TIME_SLOTS : integer := 12;
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constant C3_ARB_TIME_SLOT_0 : bit_vector(5 downto 0) := o"02";
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@@ -485,7 +488,9 @@
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pll_ce_0 => c3_pll_ce_0,
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pll_ce_90 => c3_pll_ce_90,
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pll_lock => c3_pll_lock,
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- mcb_drp_clk => c3_mcb_drp_clk
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+ mcb_drp_clk => c3_mcb_drp_clk,
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+ clk_125 => clk_125,
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+ clk_50 => clk_50
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);
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