HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/ProjetBlanc-LeonLPP-M7A3P1k/top_synplify.npl

Débug de la FIFO...

Débug de la FIFO /!\ syncram_2p, signaux d'écritue/lecture actif a l'état haut Différent de RAM_CEL actif a l'état bas .

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/ designs / ProjetBlanc-LeonLPP-M7A3P1k / top_synplify.npl

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				JDF G
				PROJECT top
				DESIGN top
				DEVFAM PROASIC3
				DEVICE PROASIC3
				DEVSPEED Std
				DEVPKG ""
				DEVTOPLEVELMODULETYPE EDIF
				DEVSIMULATOR Modelsim
				DEVGENERATEDSIMULATIONMODEL VHDL
				SOURCE synplify\top.edf
				DEPASSOC top ..\..\boards\Projet-Blanc-M7A3P1K\top.ucf
				[Normal]
				xilxMapAllowLogicOpt=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, True
				xilxMapCoverMode=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, Speed
				xilxNgdbld_AUL=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, True
				xilxPAReffortLevel=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, Medium
				xilxNgdbldMacro=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1105378344, ..\..\netlists\xilinx\PROASIC3
				[STRATEGY-LIST]
				Normal=True

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