HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/ProjetBlanc-LeonLPP-M7A3P1k/top_designer_act.tcl

Débug de la FIFO...

Débug de la FIFO /!\ syncram_2p, signaux d'écritue/lecture actif a l'état haut Différent de RAM_CEL actif a l'état bas .

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             top_designer_act.tcl
        
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                | application/x-tcl
            
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      new_design -name "top" -family "PROASIC3" 

      set_device -die "PROASIC3" -package "484 FBGA" -speed "Std" -voltage "1.5" -iostd "LVTTL" -jtag "yes" -probe "yes" -trst "yes" -temprange "COM" -voltrange "COM" 

      if {[file exist top.pdc]} {

      import_source -format "edif" -edif_flavor "GENERIC"  -merge_physical "no" -merge_timing "no" {synplify/top.edf} -format "pdc" -abort_on_error "no" {top.pdc}

      } else {

      import_source -format "edif" -edif_flavor "GENERIC"  -merge_physical "no" -merge_timing "no" {synplify/top.edf}

      }

      save_design {top.adb}

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				new_design -name "top" -family "PROASIC3"
				set_device -die "PROASIC3" -package "484 FBGA" -speed "Std" -voltage "1.5" -iostd "LVTTL" -jtag "yes" -probe "yes" -trst "yes" -temprange "COM" -voltrange "COM"
				if {[file exist top.pdc]} {
				import_source -format "edif" -edif_flavor "GENERIC" -merge_physical "no" -merge_timing "no" {synplify/top.edf} -format "pdc" -abort_on_error "no" {top.pdc}
				} else {
				import_source -format "edif" -edif_flavor "GENERIC" -merge_physical "no" -merge_timing "no" {synplify/top.edf}
				}
				save_design {top.adb}