HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/ProjetBlanc-LeonLPP-M7A3P1k/package/memoryctrl.vhd

Débug de la FIFO...

Débug de la FIFO /!\ syncram_2p, signaux d'écritue/lecture actif a l'état haut Différent de RAM_CEL actif a l'état bas .

martin - - Load All Authors

File last commit:

r100:fc97c34d69e3 martin


                r103:e52d1f932b5e

martin

Download file

             memoryctrl.vhd
        
                    73 lines
            
             | 2.2 KiB
            
                | text/x-vhdl
            
             |
                VhdlLexer
            
             / designs / ProjetBlanc-LeonLPP-M7A3P1k / package / memoryctrl.vhd
          
                    History
                
                 |
                  Annotation
                 | Raw
                 |Copy content
                 |Copy permalink

      ----------------------------------------------------------------------------

      --  This file is a part of the GRLIB VHDL IP LIBRARY

      --  Copyright (C) 2004 GAISLER RESEARCH

      --

      --  This program is free software; you can redistribute it and/or modify

      --  it under the terms of the GNU General Public License as published by

      --  the Free Software Foundation; either version 2 of the License, or

      --  (at your option) any later version.

      --

      --  See the file COPYING for the full details of the license.

      --

      ------------------------------------------------------------------------------

      -- Entity: 	memctrl

      -- File:	memctrl.vhd

      -- Author:	Jiri Gaisler - Gaisler Research

      -- Description:	Memory controller package

      ------------------------------------------------------------------------------

      library ieee;

      use ieee.std_logic_1164.all;

      library grlib;

      use grlib.amba.all;

      library gaisler;

      use gaisler.memctrl.all;

      package memoryctrl is

      component mctrl

        generic (

          hindex    : integer := 0;

          pindex    : integer := 0;

          romaddr   : integer := 16#000#;

          rommask   : integer := 16#E00#;

          ioaddr    : integer := 16#200#;

          iomask    : integer := 16#E00#;

          ramaddr   : integer := 16#400#;

          rammask   : integer := 16#C00#;

          paddr     : integer := 0;

          pmask     : integer := 16#fff#;

          wprot     : integer := 0;

          invclk    : integer := 0; 

          fast      : integer := 0; 

          romasel   : integer := 28;

          sdrasel   : integer := 29;

          srbanks   : integer := 4;

          ram8      : integer := 0;

          ram16     : integer := 0;

          sden      : integer := 0;

          sepbus    : integer := 0;

          sdbits    : integer := 32;

          sdlsb     : integer := 2;

          oepol     : integer := 0;

          syncrst   : integer := 0;

          pageburst : integer := 0;

          scantest  : integer := 0;

          mobile    : integer := 0

        );

        port (

          rst       : in  std_ulogic;

          clk       : in  std_ulogic;

          memi      : in  memory_in_type;

          memo      : out memory_out_type;

          ahbsi     : in  ahb_slv_in_type;

          ahbso     : out ahb_slv_out_type;

          apbi      : in  apb_slv_in_type;

          apbo      : out apb_slv_out_type;

          wpo       : in  wprot_out_type;

          sdo       : out sdram_out_type

        );

      end component; 

      end;

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages

				----------------------------------------------------------------------------
				-- This file is a part of the GRLIB VHDL IP LIBRARY
				-- Copyright (C) 2004 GAISLER RESEARCH
				--
				-- This program is free software; you can redistribute it and/or modify
				-- it under the terms of the GNU General Public License as published by
				-- the Free Software Foundation; either version 2 of the License, or
				-- (at your option) any later version.
				--
				-- See the file COPYING for the full details of the license.
				--
				------------------------------------------------------------------------------
				-- Entity: memctrl
				-- File: memctrl.vhd
				-- Author: Jiri Gaisler - Gaisler Research
				-- Description: Memory controller package
				------------------------------------------------------------------------------

				library ieee;
				use ieee.std_logic_1164.all;
				library grlib;
				use grlib.amba.all;
				library gaisler;
				use gaisler.memctrl.all;

				package memoryctrl is

				component mctrl
				generic (
				hindex : integer := 0;
				pindex : integer := 0;
				romaddr : integer := 16#000#;
				rommask : integer := 16#E00#;
				ioaddr : integer := 16#200#;
				iomask : integer := 16#E00#;
				ramaddr : integer := 16#400#;
				rammask : integer := 16#C00#;
				paddr : integer := 0;
				pmask : integer := 16#fff#;
				wprot : integer := 0;
				invclk : integer := 0;
				fast : integer := 0;
				romasel : integer := 28;
				sdrasel : integer := 29;
				srbanks : integer := 4;
				ram8 : integer := 0;
				ram16 : integer := 0;
				sden : integer := 0;
				sepbus : integer := 0;
				sdbits : integer := 32;
				sdlsb : integer := 2;
				oepol : integer := 0;
				syncrst : integer := 0;
				pageburst : integer := 0;
				scantest : integer := 0;
				mobile : integer := 0
				);
				port (
				rst : in std_ulogic;
				clk : in std_ulogic;
				memi : in memory_in_type;
				memo : out memory_out_type;
				ahbsi : in ahb_slv_in_type;
				ahbso : out ahb_slv_out_type;
				apbi : in apb_slv_in_type;
				apbo : out apb_slv_out_type;
				wpo : in wprot_out_type;
				sdo : out sdram_out_type
				);

				end component;

				end;