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-- Company:
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-- Engineer:
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--
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-- Create Date: 11:14:05 07/02/2012
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-- Design Name:
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-- Module Name: lfr_time_management - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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library lpp;
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use lpp.general_purpose.Clk_divider;
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entity lfr_time_management is
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generic (
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masterclk : integer := 25000000; -- master clock in Hz
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timeclk : integer := 49152000; -- 2nd clock in Hz
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finetimeclk : integer := 65536; -- divided clock used for the fine time counter
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nb_clk_div_ticks : integer := 1 -- nb ticks before commutation to AUTO state
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);
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Port (
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master_clock : in std_logic; --! Clock
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time_clock : in std_logic; --! 2nd Clock
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resetn : in std_logic; --! Reset
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grspw_tick : in std_logic;
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soft_tick : in std_logic; --! soft tick, load the coarse_time value
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coarse_time_load : in std_logic_vector(31 downto 0);
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coarse_time : out std_logic_vector(31 downto 0);
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fine_time : out std_logic_vector(31 downto 0);
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next_commutation : in std_logic_vector(31 downto 0);
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reset_next_commutation: out std_logic;
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irq1 : out std_logic;
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irq2 : out std_logic
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);
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end lfr_time_management;
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architecture Behavioral of lfr_time_management is
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signal resetn_clk_div : std_logic;
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signal clk_div : std_logic;
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--
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signal flag : std_logic;
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signal s_coarse_time : std_logic_vector(31 downto 0);
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signal previous_coarse_time_load : std_logic_vector(31 downto 0);
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signal cpt : integer range 0 to 100000;
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signal secondary_cpt : integer range 0 to 72000;
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--
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signal sirq1 : std_logic;
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signal sirq2 : std_logic;
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signal cpt_next_commutation : integer range 0 to 100000;
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signal p_next_commutation : std_logic_vector(31 downto 0);
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signal latched_next_commutation : std_logic_vector(31 downto 0);
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signal p_clk_div : std_logic;
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--
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type state_type is (auto, slave);
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signal state : state_type;
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type timer_type is (idle, engaged);
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signal commutation_timer : timer_type;
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begin
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--*******************************************
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-- COMMUTATION TIMER AND INTERRUPT GENERATION
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process(master_clock, resetn)
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begin
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if resetn = '0' then
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commutation_timer <= idle;
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cpt_next_commutation <= 0;
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sirq1 <= '0';
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sirq2 <= '0';
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latched_next_commutation <= x"ffffffff";
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elsif master_clock'event and master_clock = '1' then
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case commutation_timer is
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when idle =>
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sirq1 <= '0';
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sirq2 <= '0';
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if s_coarse_time = latched_next_commutation then
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commutation_timer <= engaged; -- transition to state "engaged"
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sirq1 <= '1'; -- start the pulse on sirq1
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latched_next_commutation <= x"ffffffff";
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elsif not(p_next_commutation = next_commutation) then -- next_commutation has changed
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latched_next_commutation <= next_commutation; -- latch the value
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else
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commutation_timer <= idle;
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end if;
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when engaged =>
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sirq1 <= '0'; -- stop the pulse on sirq1
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if not(p_clk_div = clk_div) and clk_div = '1' then -- detect a clk_div raising edge
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if cpt_next_commutation = 65536 then
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cpt_next_commutation <= 0;
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commutation_timer <= idle;
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sirq2 <= '1'; -- start the pulse on sirq2
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else
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cpt_next_commutation <= cpt_next_commutation + 1;
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end if;
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end if;
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when others =>
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commutation_timer <= idle;
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end case;
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p_next_commutation <= next_commutation;
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p_clk_div <= clk_div;
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end if;
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end process;
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irq1 <= sirq1;
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irq2 <= sirq2;
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reset_next_commutation <= '0';
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--
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--*******************************************
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--**********************
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-- synchronization stage
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process(master_clock, resetn) -- resynchronisation with clk
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begin
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if resetn = '0' then
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coarse_time(31 downto 0) <= x"80000000"; -- set the most significant bit of the coarse time to 1 on reset
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elsif master_clock'event and master_clock = '1' then
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coarse_time(31 downto 0) <= s_coarse_time(31 downto 0); -- coarse_time is changed synchronously with clk
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end if;
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end process;
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--
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--**********************
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process(clk_div, resetn, grspw_tick, soft_tick, flag, coarse_time_load) --
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begin
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if resetn = '0' then
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flag <= '0';
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cpt <= 0;
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secondary_cpt <= 0;
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s_coarse_time <= x"80000000"; -- set the most significant bit of the coarse time to 1 on reset
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previous_coarse_time_load <= x"80000000";
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state <= auto;
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elsif grspw_tick = '1' or soft_tick = '1' then
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if flag = '1' then -- coarse_time_load shall change at least 1/65536 s before the timecode
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s_coarse_time <= coarse_time_load;
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flag <= '0';
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else -- if coarse_time_load has not changed, increment the value autonomously
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s_coarse_time <= std_logic_vector(unsigned(s_coarse_time) + 1);
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end if;
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cpt <= 0;
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secondary_cpt <= 0;
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state <= slave;
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elsif clk_div'event and clk_div = '1' then
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case state is
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when auto =>
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if cpt = 65535 then
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if flag = '1' then
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s_coarse_time <= coarse_time_load;
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flag <= '0';
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else
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s_coarse_time <= std_logic_vector(unsigned(s_coarse_time) + 1);
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end if;
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cpt <= 0;
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secondary_cpt <= secondary_cpt + 1;
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else
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cpt <= cpt + 1 ;
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end if;
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when slave =>
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if cpt = 65536 + nb_clk_div_ticks then -- 1 / 65536 = 15.259 us
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state <= auto; -- commutation to AUTO state
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if flag = '1' then
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s_coarse_time <= coarse_time_load;
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flag <= '0';
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else
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s_coarse_time <= std_logic_vector(unsigned(s_coarse_time) + 1);
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end if;
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cpt <= nb_clk_div_ticks; -- reset cpt at nb_clk_div_ticks
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secondary_cpt <= secondary_cpt + 1;
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else
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cpt <= cpt + 1;
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end if;
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when others =>
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state <= auto;
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end case;
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if secondary_cpt > 60 then
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s_coarse_time(31) <= '1';
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end if;
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if not(previous_coarse_time_load = coarse_time_load) then
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flag <= '1';
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end if;
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previous_coarse_time_load <= coarse_time_load;
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end if;
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end process;
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fine_time <= std_logic_vector(to_unsigned(cpt, 32));
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-- resetn grspw_tick soft_tick resetn_clk_div
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-- 0 0 0 0
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-- 0 0 1 0
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-- 0 1 0 0
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-- 0 1 1 0
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-- 1 0 0 1
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-- 1 0 1 0
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-- 1 1 0 0
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-- 1 1 1 0
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resetn_clk_div <= '1' when ( (resetn='1') and (grspw_tick='0') and (soft_tick='0') ) else '0';
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Clk_divider0 : Clk_divider -- the target frequency is 65536 Hz
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generic map (timeclk,finetimeclk) port map ( time_clock, resetn_clk_div, clk_div);
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end Behavioral;
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