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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by GRLIB script generator -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
</header>
<version xil_pn:ise_version="11.1" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="../../boards/Projet-Blanc-M7A3P1K/top.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../lib/grlib/stdlib/version.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="grlib"/>
</file>
<file xil_pn:name="../../lib/grlib/stdlib/config.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="grlib"/>
</file>
<file xil_pn:name="../../lib/grlib/stdlib/stdlib.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="grlib"/>
</file>
<file xil_pn:name="../../lib/grlib/stdlib/stdio.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="grlib"/>
</file>
<file xil_pn:name="../../lib/grlib/stdlib/testlib.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="grlib"/>
</file>
<file xil_pn:name="../../lib/grlib/util/util.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="grlib"/>
</file>
<file xil_pn:name="../../lib/grlib/sparc/sparc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="grlib"/>
</file>
<file xil_pn:name="../../lib/grlib/sparc/sparc_disas.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="grlib"/>
</file>
<file xil_pn:name="../../lib/grlib/sparc/cpu_disas.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="grlib"/>
</file>
<file xil_pn:name="../../lib/grlib/modgen/multlib.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="grlib"/>
</file>
<file xil_pn:name="../../lib/grlib/modgen/leaves.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="grlib"/>
</file>
<file xil_pn:name="../../lib/grlib/amba/amba.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="grlib"/>
</file>
<file xil_pn:name="../../lib/grlib/amba/devices.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="grlib"/>
</file>
<file xil_pn:name="../../lib/grlib/amba/defmst.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="grlib"/>
</file>
<file xil_pn:name="../../lib/grlib/amba/apbctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="grlib"/>
</file>
<file xil_pn:name="../../lib/grlib/amba/ahbctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="grlib"/>
</file>
<file xil_pn:name="../../lib/grlib/amba/dma2ahb_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="grlib"/>
</file>
<file xil_pn:name="../../lib/grlib/amba/dma2ahb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="grlib"/>
</file>
<file xil_pn:name="../../lib/grlib/amba/dma2ahb_tp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="grlib"/>
</file>
<file xil_pn:name="../../lib/grlib/amba/amba_tp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="grlib"/>
</file>
<file xil_pn:name="../../lib/tech/proasic3/components/proasic3.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="proasic3"/>
</file>
<file xil_pn:name="../../lib/synplify/sim/synplify.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="synplify"/>
</file>
<file xil_pn:name="../../lib/synplify/sim/synattr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="synplify"/>
</file>
<file xil_pn:name="../../lib/techmap/gencomp/gencomp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/gencomp/netcomp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/inferred/memory_inferred.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/inferred/ddr_inferred.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/inferred/mul_inferred.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/inferred/ddr_phy_inferred.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/allclkgen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/allddr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/allmem.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/allmul.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/allpads.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/alltap.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/clkgen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/clkmux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/clkand.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/ddr_ireg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/ddr_oreg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/ddrphy.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/syncram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/syncram64.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/syncram_2p.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/syncram_dp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/syncfifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/regfile_3p.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/tap.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/techbuf.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/nandtree.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/clkpad.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/clkpad_ds.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/inpad.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/inpad_ds.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/iodpad.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/iopad.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/iopad_ds.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/lvds_combo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/odpad.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/outpad.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/outpad_ds.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/toutpad.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/skew_outpad.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/grspwc_net.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/grspwc2_net.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/grlfpw_net.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/grfpw_net.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/leon4_net.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/mul_61x61.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/cpu_disas_net.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/grusbhc_net.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/ringosc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/ssrctrl_net.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/system_monitor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/grgates.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/inpad_ddr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/outpad_ddr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/iopad_ddr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/syncram128bw.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/syncram128.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/syncram156bw.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/techmult.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/spictrl_net.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/techmap/maps/scanreg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="techmap"/>
</file>
<file xil_pn:name="../../lib/spw/comp/spwcomp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="spw"/>
</file>
<file xil_pn:name="../../lib/spw/wrapper/grspw_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="spw"/>
</file>
<file xil_pn:name="../../lib/spw/wrapper/grspw2_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="spw"/>
</file>
<file xil_pn:name="../../lib/eth/comp/ethcomp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="eth"/>
</file>
<file xil_pn:name="../../lib/eth/core/greth_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="eth"/>
</file>
<file xil_pn:name="../../lib/eth/core/eth_rstgen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="eth"/>
</file>
<file xil_pn:name="../../lib/eth/core/eth_edcl_ahb_mst.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="eth"/>
</file>
<file xil_pn:name="../../lib/eth/core/eth_ahb_mst.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="eth"/>
</file>
<file xil_pn:name="../../lib/eth/core/greth_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="eth"/>
</file>
<file xil_pn:name="../../lib/eth/core/greth_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="eth"/>
</file>
<file xil_pn:name="../../lib/eth/core/grethc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="eth"/>
</file>
<file xil_pn:name="../../lib/eth/wrapper/greth_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="eth"/>
</file>
<file xil_pn:name="../../lib/eth/wrapper/greth_gbit_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="eth"/>
</file>
<file xil_pn:name="../../lib/opencores/occomp/occomp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="opencores"/>
</file>
<file xil_pn:name="../../lib/opencores/can/cancomp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="opencores"/>
</file>
<file xil_pn:name="../../lib/opencores/can/can_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="opencores"/>
</file>
<file xil_pn:name="../../lib/gaisler/arith/arith.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/arith/mul32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/arith/div32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/memctrl/memctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/memctrl/sdctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/memctrl/sdctrl64.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/memctrl/sdmctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/memctrl/srctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/memctrl/spimctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/leon3.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/mmuconfig.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/mmuiface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/libmmu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/libiu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/libcache.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/libproc3.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/cachemem.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/mmu_icache.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/mmu_dcache.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/mmu_acache.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/mmutlbcam.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/mmulrue.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/mmulru.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/mmutlb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/mmutw.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/mmu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/mmu_cache.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/cpu_disasx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/iu3.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/grfpwx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/mfpwx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/grlfpwx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/tbufmem.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/dsu3x.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/dsu3.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/proc3.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/leon3s.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/leon3cg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/irqmp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/grfpwxsh.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/grfpushwx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3/leon3sh.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/leon3ft/leon3ft.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/can/can.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/can/can_mod.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/can/can_oc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/can/can_mc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/can/canmux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/can/can_rd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/misc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/rstgen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/gptimer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/ahbram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/ahbdpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/ahbtrace.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/ahbtrace_mb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/ahbtrace_mmb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/ahbmst.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/grgpio.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/ahbstat.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/logan.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/apbps2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/charrom_package.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/charrom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/apbvga.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/svgactrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/i2cmst_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/spictrlx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/spictrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/i2cslv.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/wild.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/wild2ahb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/grsysmon.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/gracectrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/grgpreg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/ahbmst2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/misc/ahb_mst_iface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/ambatest/ahbtbp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/ambatest/ahbtbm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/net/net.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/uart/uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/uart/libdcom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/uart/apbuart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/uart/dcom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/uart/dcom_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/uart/ahbuart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/sim/sim.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/sim/sram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/sim/ata_device.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/sim/sram16.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/sim/phy.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/sim/ahbrep.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/sim/delay_wire.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/sim/spi_flash.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/sim/pwm_check.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/sim/usbsim.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/sim/grusbdcsim.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/sim/grusb_dclsim.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/jtag/jtag.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/jtag/libjtagcom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/jtag/jtagcom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/jtag/ahbjtag.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/jtag/ahbjtag_bsd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/jtag/bscanregs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/jtag/bscanregsbd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/jtag/jtagtst.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/greth/ethernet_mac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/greth/greth.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/greth/greth_mb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/greth/greth_gbit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/greth/greth_gbit_mb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/greth/grethm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/spacewire/spacewire.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/spacewire/grspw.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/spacewire/grspw2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/spacewire/grspwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/gaisler/gr1553b/gr1553b_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="gaisler"/>
</file>
<file xil_pn:name="../../lib/esa/memoryctrl/memoryctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="esa"/>
</file>
<file xil_pn:name="../../lib/esa/memoryctrl/mctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="esa"/>
</file>
<file xil_pn:name="../../lib/fmf/utilities/conversions.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="fmf"/>
</file>
<file xil_pn:name="../../lib/fmf/utilities/gen_utils.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="fmf"/>
</file>
<file xil_pn:name="../../lib/fmf/flash/flash.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="fmf"/>
</file>
<file xil_pn:name="../../lib/fmf/flash/s25fl064a.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="fmf"/>
</file>
<file xil_pn:name="../../lib/fmf/flash/m25p80.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="fmf"/>
</file>
<file xil_pn:name="../../lib/fmf/fifo/idt7202.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="fmf"/>
</file>
<file xil_pn:name="../../lib/gsi/ssram/functions.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="gsi"/>
</file>
<file xil_pn:name="../../lib/gsi/ssram/core_burst.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="gsi"/>
</file>
<file xil_pn:name="../../lib/gsi/ssram/g880e18bt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="gsi"/>
</file>
<file xil_pn:name="../../lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/iir_filter/FILTER.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/iir_filter/FILTERcfg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/iir_filter/RAM.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/iir_filter/RAM_CEL.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/iir_filter/iir_filter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/lpp_fft/APB_FFT.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/lpp_fft/APB_FFT_half.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/lpp_fft/CoreFFT.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/lpp_fft/Driver_FFT.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/lpp_fft/actar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/lpp_fft/actram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/lpp_fft/fftDp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/lpp_fft/fftSm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/lpp_fft/fft_components.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/lpp_fft/lpp_fft.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/lpp_fft/primitives.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./dsp/lpp_fft/twiddle.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/ADDRcntr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/ALU.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/Adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/Clk_divider.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/MAC.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/MAC_CONTROLER.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/MAC_MUX.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/MAC_MUX2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/MAC_REG.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/MUX2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/Multiplier.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/REG.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/Shifter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/general_purpose.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/lpp_AMR/APB_AMR.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/lpp_AMR/Clock_multi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/lpp_AMR/Dephaseur.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/lpp_AMR/Gene_Rz.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/lpp_AMR/bclk_reg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/lpp_AMR/lpp_AMR.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/lpp_balise/APB_Balise.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/lpp_balise/lpp_balise.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/lpp_delay/APB_Delay.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/lpp_delay/TimerDelay.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./general_purpose/lpp_delay/lpp_delay.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_ad_Conv/WriteGen_ADC.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_amba/apb_devices_list.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_amba/lpp_amba.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_cna/APB_CNA.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_cna/CNA_TabloC.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_cna/Convertisseur_config.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_cna/Gene_SYNC.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_cna/Serialize.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_cna/Systeme_Clock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_cna/lpp_cna.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_matrix/ALU_Driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_matrix/ALU_v2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_matrix/APB_Matrix.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_matrix/DriveInputs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_matrix/GetResult.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_matrix/MAC_v2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_matrix/Matrix.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_matrix/SpectralMatrix.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_matrix/Starter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_matrix/TopMatrix_PDR.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_matrix/Top_MatrixSpec.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_matrix/TwoComplementer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_matrix/lpp_matrix.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_memory/APB_FIFO.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_memory/SSRAM_plugin.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_memory/lppFIFOx5.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_memory/lpp_FIFO.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_memory/lpp_memory.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_uart/APB_UART.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_uart/BaudGen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_uart/Shift_REG.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_uart/UART.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_uart/lpp_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_usb/APB_USB.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_usb/RWbuf.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/lpp/./lpp_usb/lpp_usb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/cypress/ssram/components.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="cypress"/>
</file>
<file xil_pn:name="../../lib/cypress/ssram/package_utility.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="cypress"/>
</file>
<file xil_pn:name="../../lib/cypress/ssram/cy7c1354b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="cypress"/>
</file>
<file xil_pn:name="../../lib/cypress/ssram/cy7c1380d.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="cypress"/>
</file>
<file xil_pn:name="../../lib/work/debug/debug.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="work"/>
</file>
<file xil_pn:name="../../lib/work/debug/grtestmod.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="work"/>
</file>
<file xil_pn:name="../../lib/work/debug/cpu_disas.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="work"/>
</file>
<file xil_pn:name="config.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="ahbrom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="leon3mp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="testbench.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
</file>
</files>
<properties>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="true"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="()"/>
<property xil_pn:name="Constraints Entry" xil_pn:value="Constraints Editor"/>
<property xil_pn:name="Create Mask File" xil_pn:value="true"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="true"/>
<property xil_pn:name="Device" xil_pn:value="PROASIC3"/>
<property xil_pn:name="Device Family" xil_pn:value="PROASIC3"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="true"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="None"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|top|rtl"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/top"/>
<property xil_pn:name="Macro Search Path" xil_pn:value="../../netlists/xilinx/PROASIC3"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value=""/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value=""/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="high"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="top"/>
<property xil_pn:name="PROP_xilxBitgCfg_GenOpt_MaskFile_virtex2" xil_pn:value="true"/>
<property xil_pn:name="PROP_xilxBitgCfg_GenOpt_ReadBack_virtex2" xil_pn:value="true"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Yes"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs"/>
<property xil_pn:name="Package" xil_pn:value=""""/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="false"/>
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE Mixed"/>
<property xil_pn:name="Speed Grade" xil_pn:value="Std"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
<property xil_pn:name="Verbose Property Persistence" xil_pn:value="false"/>
</properties>
<bindings/>
<libraries>
<library xil_pn:name="grlib"/>
<library xil_pn:name="proasic3"/>
<library xil_pn:name="synplify"/>
<library xil_pn:name="techmap"/>
<library xil_pn:name="spw"/>
<library xil_pn:name="eth"/>
<library xil_pn:name="opencores"/>
<library xil_pn:name="gaisler"/>
<library xil_pn:name="esa"/>
<library xil_pn:name="fmf"/>
<library xil_pn:name="spansion"/>
<library xil_pn:name="gsi"/>
<library xil_pn:name="lpp"/>
<library xil_pn:name="cypress"/>
<library xil_pn:name="work"/>
</libraries>
<partitions>
<partition xil_pn:name="/top"/>
</partitions>
</project>