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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE IEEE.std_logic_signed.ALL;
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USE IEEE.MATH_real.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY std;
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USE std.textio.ALL;
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library opencores;
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use opencores.spwpkg.all;
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use opencores.spwambapkg.all;
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LIBRARY lpp;
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USE lpp.iir_filter.ALL;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.FILTERcfg.ALL;
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USE lpp.lpp_lfr_filter_coeff.ALL;
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USE lpp.general_purpose.ALL;
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USE lpp.data_type_pkg.ALL;
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USE lpp.lpp_lfr_pkg.ALL;
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USE lpp.general_purpose.ALL;
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USE lpp.lpp_sim_pkg.ALL;
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USE lpp.CY7C1061DV33_pkg.ALL;
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ENTITY testbench IS
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GENERIC(
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tech : INTEGER := 0; --axcel,0
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Mem_use : INTEGER := use_CEL --use_RAM,use_CEL
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);
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END;
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ARCHITECTURE behav OF testbench IS
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SIGNAL TSTAMP : INTEGER := 0;
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL clk49_152MHz : STD_LOGIC := '0';
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SIGNAL rstn,rst : STD_LOGIC;
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SIGNAL end_of_simu : STD_LOGIC := '0';
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-----------------------------------------------------------------------------
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-- LFR TOP WRAPPER SIGNALS
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-----------------------------------------------------------------------------
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SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0);
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SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL nSRAM_MBE : STD_LOGIC; -- new
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SIGNAL nSRAM_E1 : STD_LOGIC; -- new
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SIGNAL nSRAM_E2 : STD_LOGIC; -- new
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-- nSRAM_SCRUB : OUT STD_LOGIC; -- new
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SIGNAL nSRAM_W : STD_LOGIC; -- new
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SIGNAL nSRAM_G : STD_LOGIC; -- new
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SIGNAL nSRAM_BUSY : STD_LOGIC; -- new
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-- SPW --------------------------------------------------------------------
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SIGNAL spw1_en : STD_LOGIC; -- new
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SIGNAL spw1_din : STD_LOGIC;
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SIGNAL spw1_sin : STD_LOGIC;
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SIGNAL spw1_dout : STD_LOGIC;
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SIGNAL spw1_sout : STD_LOGIC;
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SIGNAL spw2_en : STD_LOGIC; -- new
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SIGNAL spw2_din : STD_LOGIC;
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SIGNAL spw2_sin : STD_LOGIC;
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SIGNAL spw2_dout : STD_LOGIC;
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SIGNAL spw2_sout : STD_LOGIC;
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-- ADC --------------------------------------------------------------------
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SIGNAL bias_fail_sw : STD_LOGIC;
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SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL ADC_smpclk : STD_LOGIC;
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SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0);
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-- DAC --------------------------------------------------------------------
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SIGNAL DAC_SDO : STD_LOGIC;
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SIGNAL DAC_SCK : STD_LOGIC;
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SIGNAL DAC_SYNC : STD_LOGIC;
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SIGNAL DAC_CAL_EN : STD_LOGIC;
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-- HK ---------------------------------------------------------------------
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SIGNAL HK_smpclk : STD_LOGIC;
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SIGNAL ADC_OEB_bar_HK : STD_LOGIC;
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SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL nSRAM_CE : STD_LOGIC;
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SIGNAL autostart: std_logic := '1';
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-- Enables link start once the Ready state is reached.
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-- Without autostart or linkstart, the link remains in state Ready.
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SIGNAL linkstart: std_logic :='1';
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-- Do not start link (overrides linkstart and autostart) and/or
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-- disconnect a running link.
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SIGNAL linkdis: std_logic := '0';
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-- Control bits of the TimeCode to be sent. Must be valid while tick_in is high.
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SIGNAL ctrl_in: std_logic_vector(1 downto 0) :=(others => '0');
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-- Counter value of the TimeCode to be sent. Must be valid while tick_in is high.
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SIGNAL time_in: std_logic_vector(5 downto 0):=(others => '0');
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-- Pulled high by the application to write an N-Char to the transmit
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-- queue. If "txwrite" and "txrdy" are both high on the rising edge
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-- of "clk", a character is added to the transmit queue.
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-- This signal has no effect if "txrdy" is low.
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SIGNAL txwrite: std_logic := '0';
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-- Control flag to be sent with the next N_Char.
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-- Must be valid while txwrite is high.
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SIGNAL txflag: std_logic :='0';
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-- Byte to be sent, or "00000000" for EOP or "00000001" for EEP.
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-- Must be valid while txwrite is high.
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SIGNAL txdata: std_logic_vector(7 downto 0):=(others => '0');
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-- High if the entity is ready to accept an N-Char for transmission.
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SIGNAL txrdy: std_logic;
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-- High if the transmission queue is at least half full.
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SIGNAL txhalff: std_logic;
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-- High for one clock cycle if a TimeCode was just received.
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SIGNAL tick_out: std_logic;
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-- Control bits of the last received TimeCode.
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SIGNAL ctrl_out: std_logic_vector(1 downto 0);
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-- Counter value of the last received TimeCode.
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SIGNAL time_out: std_logic_vector(5 downto 0);
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-- High if "rxflag" and "rxdata" contain valid data.
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-- This signal is high unless the receive FIFO is empty.
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SIGNAL rxvalid: std_logic;
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-- High if the receive FIFO is at least half full.
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SIGNAL rxhalff: std_logic;
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-- High if the received character is EOP or EEP; low if the received
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-- character is a data byte. Valid if "rxvalid" is high.
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SIGNAL rxflag: std_logic;
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-- Received byte, or "00000000" for EOP or "00000001" for EEP.
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-- Valid if "rxvalid" is high.
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SIGNAL rxdata: std_logic_vector(7 downto 0);
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-- Pulled high by the application to accept a received character.
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-- If "rxvalid" and "rxread" are both high on the rising edge of "clk",
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-- a character is removed from the receive FIFO and "rxvalid", "rxflag"
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-- and "rxdata" are updated.
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-- This signal has no effect if "rxvalid" is low.
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SIGNAL rxread: std_logic:='0';
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-- High if the link state machine is currently in the Started state.
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SIGNAL started: std_logic;
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-- High if the link state machine is currently in the Connecting state.
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SIGNAL connecting: std_logic;
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-- High if the link state machine is currently in the Run state, indicating
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-- that the link is fully operational. If none of started, connecting or running
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-- is high, the link is in an initial state and the transmitter is not yet enabled.
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SIGNAL running: std_logic;
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-- Disconnect detected in state Run. Triggers a reset and reconnect of the link.
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-- This indication is auto-clearing.
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SIGNAL errdisc: std_logic;
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-- Parity error detected in state Run. Triggers a reset and reconnect of the link.
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-- This indication is auto-clearing.
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SIGNAL errpar: std_logic;
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-- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of
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-- the link. This indication is auto-clearing.
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SIGNAL erresc: std_logic;
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-- Credit error detected. Triggers a reset and reconnect of the link.
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-- This indication is auto-clearing.
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SIGNAL errcred: std_logic;
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BEGIN
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-----------------------------------------------------------------------------
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-- CLOCK and RESET
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-----------------------------------------------------------------------------
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PROCESS
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BEGIN -- PROCESS
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WAIT UNTIL clk = '1';
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rstn <= '0';
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rst <= '1';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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rstn <= '1';
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rst <= '0';
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WAIT UNTIL end_of_simu = '1';
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WAIT FOR 10 ps;
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assert false report "end of test" severity note;
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-- Wait forever; this will finish the simulation.
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wait;
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END PROCESS;
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-----------------------------------------------------------------------------
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clk49_152MHz_gen:PROCESS
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BEGIN
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IF end_of_simu /= '1' THEN
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clk49_152MHz <= NOT clk49_152MHz;
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WAIT FOR 10173 ps;
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ELSE
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WAIT FOR 10 ps;
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assert false report "end of test" severity note;
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WAIT;
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END IF;
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END PROCESS;
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clk_50M_gen:PROCESS
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BEGIN
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IF end_of_simu /= '1' THEN
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clk <= NOT clk;
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TSTAMP <= TSTAMP+20;
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WAIT FOR 10 ns;
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ELSE
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WAIT FOR 10 ps;
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assert false report "end of test" severity note;
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WAIT;
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END IF;
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END PROCESS;
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LFR: ENTITY work.LFR_FM
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GENERIC MAP(
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Mem_use => use_RAM,
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USE_BOOTLOADER => 0,
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USE_ADCDRIVER => 1,
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tech => inferred,
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tech_leon => inferred,
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DEBUG_FORCE_DATA_DMA => 0,
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USE_DEBUG_VECTOR => 0
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)
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PORT MAP(
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clk50MHz => clk,
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clk49_152MHz => clk49_152MHz,
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reset => rstn,
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TAG => OPEN,
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address => address,
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data => data,
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nSRAM_MBE => nSRAM_MBE,
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nSRAM_E1 => nSRAM_E1,
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nSRAM_E2 => nSRAM_E2,
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-- nSRAM_SCRUB : OUT STD_LOGIC; -- new
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nSRAM_W => nSRAM_W,
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nSRAM_G => nSRAM_G,
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nSRAM_BUSY => nSRAM_BUSY,
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-- SPW --------------------------------------------------------------------
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spw1_en => spw1_en,
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spw1_din => spw1_din,
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spw1_sin => spw1_sin,
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spw1_dout => spw1_dout,
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spw1_sout => spw1_sout,
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spw2_en => spw2_en,
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spw2_din => spw2_din,
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spw2_sin => spw2_sin,
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spw2_dout => spw2_dout,
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spw2_sout => spw2_sout,
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-- ADC --------------------------------------------------------------------
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bias_fail_sw => bias_fail_sw,
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ADC_OEB_bar_CH => ADC_OEB_bar_CH,
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ADC_smpclk => ADC_smpclk,
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ADC_data => ADC_data,
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-- DAC --------------------------------------------------------------------
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DAC_SDO => DAC_SDO,
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DAC_SCK => DAC_SCK,
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DAC_SYNC => DAC_SYNC,
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DAC_CAL_EN => DAC_CAL_EN,
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-- HK ---------------------------------------------------------------------
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HK_smpclk => HK_smpclk,
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ADC_OEB_bar_HK => ADC_OEB_bar_HK,
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HK_SEL => HK_SEL
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);
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spw2_din <= '1';
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spw2_sin <= '1';
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-----------------------------------------------------------------------------
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-- SRAMS Same as EM, we don't have UT8ER1M32 models
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-----------------------------------------------------------------------------
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nSRAM_BUSY <= '1'; -- TODO emulate scrubbing
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nSRAM_CE <= not nSRAM_E1;
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async_1Mx16_0: CY7C1061DV33
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GENERIC MAP (
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ADDR_BITS => 19,
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DATA_BITS => 16,
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depth => 1048576,
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MEM_ARRAY_DEBUG => 32,
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TimingInfo => TRUE,
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TimingChecks => '1')
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PORT MAP (
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CE1_b => '0',
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CE2 => nSRAM_CE,
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WE_b => nSRAM_W,
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OE_b => nSRAM_G,
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BHE_b => '0',
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BLE_b => '0',
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A => address,
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DQ => data(15 DOWNTO 0));
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async_1Mx16_1: CY7C1061DV33
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GENERIC MAP (
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ADDR_BITS => 19,
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DATA_BITS => 16,
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depth => 1048576,
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MEM_ARRAY_DEBUG => 32,
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TimingInfo => TRUE,
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TimingChecks => '1')
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PORT MAP (
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CE1_b => '0',
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CE2 => nSRAM_CE,
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WE_b => nSRAM_W,
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OE_b => nSRAM_G,
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BHE_b => '0',
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BLE_b => '0',
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A => address,
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DQ => data(31 DOWNTO 16));
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SPW: spwstream
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generic map(
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sysfreq => 50.0e6,
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txclkfreq => 50.0e6,
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rximpl => impl_generic,
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rxchunk => 1,
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tximpl => impl_generic,
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rxfifosize_bits => 11,
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txfifosize_bits => 11
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)
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port map(
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-- System clock.
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clk => clk,
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rxclk => clk,
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txclk => clk,
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rst => rst,
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autostart => autostart,
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linkstart => linkstart,
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linkdis => linkdis,
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txdivcnt => X"00",
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tick_in => '0',
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-- Control bits of the TimeCode to be sent. Must be valid while tick_in is high.
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ctrl_in => ctrl_in,
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-- Counter value of the TimeCode to be sent. Must be valid while tick_in is high.
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time_in => time_in,
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-- Pulled high by the application to write an N-Char to the transmit
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-- queue. If "txwrite" and "txrdy" are both high on the rising edge
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-- of "clk", a character is added to the transmit queue.
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-- This signal has no effect if "txrdy" is low.
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txwrite => txwrite,
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-- Control flag to be sent with the next N_Char.
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-- Must be valid while txwrite is high.
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txflag => txflag,
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-- Byte to be sent, or "00000000" for EOP or "00000001" for EEP.
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-- Must be valid while txwrite is high.
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txdata => txdata,
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-- High if the entity is ready to accept an N-Char for transmission.
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txrdy => txrdy,
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-- High if the transmission queue is at least half full.
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txhalff => txhalff,
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-- High for one clock cycle if a TimeCode was just received.
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tick_out => tick_out,
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-- Control bits of the last received TimeCode.
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ctrl_out => ctrl_out,
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-- Counter value of the last received TimeCode.
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time_out => time_out,
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-- High if "rxflag" and "rxdata" contain valid data.
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-- This signal is high unless the receive FIFO is empty.
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rxvalid => rxvalid,
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-- High if the receive FIFO is at least half full.
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rxhalff => rxhalff,
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-- High if the received character is EOP or EEP; low if the received
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-- character is a data byte. Valid if "rxvalid" is high.
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rxflag => rxflag,
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-- Received byte, or "00000000" for EOP or "00000001" for EEP.
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-- Valid if "rxvalid" is high.
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rxdata => rxdata,
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-- Pulled high by the application to accept a received character.
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-- If "rxvalid" and "rxread" are both high on the rising edge of "clk",
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-- a character is removed from the receive FIFO and "rxvalid", "rxflag"
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-- and "rxdata" are updated.
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-- This signal has no effect if "rxvalid" is low.
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rxread => rxread,
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-- High if the link state machine is currently in the Started state.
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started => started,
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-- High if the link state machine is currently in the Connecting state.
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connecting => connecting,
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-- High if the link state machine is currently in the Run state, indicating
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-- that the link is fully operational. If none of started, connecting or running
|
|
|
-- is high, the link is in an initial state and the transmitter is not yet enabled.
|
|
|
running => running,
|
|
|
|
|
|
-- Disconnect detected in state Run. Triggers a reset and reconnect of the link.
|
|
|
-- This indication is auto-clearing.
|
|
|
errdisc => errdisc,
|
|
|
|
|
|
-- Parity error detected in state Run. Triggers a reset and reconnect of the link.
|
|
|
-- This indication is auto-clearing.
|
|
|
errpar => errpar,
|
|
|
|
|
|
-- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of
|
|
|
-- the link. This indication is auto-clearing.
|
|
|
erresc => erresc,
|
|
|
|
|
|
-- Credit error detected. Triggers a reset and reconnect of the link.
|
|
|
-- This indication is auto-clearing.
|
|
|
errcred => errcred,
|
|
|
|
|
|
-- Data In signal from SpaceWire bus.
|
|
|
spw_di => spw1_dout,
|
|
|
|
|
|
-- Strobe In signal from SpaceWire bus.
|
|
|
spw_si => spw1_sout,
|
|
|
|
|
|
-- Data Out signal to SpaceWire bus.
|
|
|
spw_do => spw1_din,
|
|
|
|
|
|
-- Strobe Out signal to SpaceWire bus.
|
|
|
spw_so => spw1_sin
|
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- RECORD OUTPUT SIGNALS
|
|
|
-----------------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
|
|
END;
|
|
|
|