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-- FIFO_pipeline.vhd
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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@member.fsf.org
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library lpp;
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use lpp.lpp_memory.all;
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use lpp.iir_filter.all;
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library techmap;
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use techmap.gencomp.all;
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entity FIFO_pipeline is
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generic(
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tech : integer := 0;
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Mem_use : integer := use_RAM;
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fifoCount : integer range 2 to 32 := 8;
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DataSz : integer range 1 to 32 := 8;
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abits : integer range 2 to 12 := 8
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);
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port(
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rstn : in std_logic;
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ReUse : in std_logic;
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rclk : in std_logic;
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ren : in std_logic;
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rdata : out std_logic_vector(DataSz-1 downto 0);
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empty : out std_logic;
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raddr : out std_logic_vector(abits-1 downto 0);
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wclk : in std_logic;
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wen : in std_logic;
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wdata : in std_logic_vector(DataSz-1 downto 0);
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full : out std_logic;
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waddr : out std_logic_vector(abits-1 downto 0)
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);
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end entity;
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architecture Ar_FIFO_pipeline of FIFO_pipeline is
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type FX2State is (idle);
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Signal DATA0 : std_logic_vector(DataSz-1 downto 0);
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Signal FULL_REN0,WEN_EMPTY0 : std_logic;
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begin
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FIFO0: lpp_fifo
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generic map(
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tech => tech,
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Mem_use => Mem_use,
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Enable_ReUse => '0',
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DataSz => DataSz,
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abits => abits
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)
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port map(
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rstn => rstn,
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ReUse => '0',
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rclk => rclk,
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ren => FULL_REN0,
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rdata => DATA0,
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empty => WEN_EMPTY0,
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raddr => open,
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wclk => wclk,
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wen => wen,
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wdata => wdata,
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full => full,
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waddr => open
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);
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FIFO1: lpp_fifo
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generic map(
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tech => tech,
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Mem_use => Mem_use,
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Enable_ReUse => '0',
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DataSz => DataSz,
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abits => abits
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)
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port map(
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rstn => rstn,
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ReUse => '0',
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rclk => rclk,
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ren => ren,
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rdata => rdata,
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empty => empty,
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raddr => open,
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wclk => wclk,
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wen => WEN_EMPTY0,
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wdata => DATA0,
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full => FULL_REN0,
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waddr => open
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);
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end ar_FIFO_pipeline;
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