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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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----------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.FILTERcfg.ALL;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_waveform_pkg.ALL;
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USE lpp.cic_pkg.ALL;
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USE lpp.data_type_pkg.ALL;
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USE lpp.lpp_lfr_filter_coeff.ALL;
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use lpp.general_purpose.all;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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ENTITY lpp_lfr_filter IS
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GENERIC(
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tech : INTEGER := 0;
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Mem_use : INTEGER := use_RAM;
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RTL_DESIGN_LIGHT : INTEGER := 0;
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DATA_SHAPING_SATURATION : INTEGER := 1
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);
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PORT (
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sample : IN Samples(7 DOWNTO 0);
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sample_val : IN STD_LOGIC;
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sample_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
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--
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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--
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data_shaping_SP0 : IN STD_LOGIC;
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data_shaping_SP1 : IN STD_LOGIC;
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data_shaping_R0 : IN STD_LOGIC;
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data_shaping_R1 : IN STD_LOGIC;
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data_shaping_R2 : IN STD_LOGIC;
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--
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sample_f0_val : OUT STD_LOGIC;
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sample_f1_val : OUT STD_LOGIC;
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sample_f2_val : OUT STD_LOGIC;
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sample_f3_val : OUT STD_LOGIC;
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--
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sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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--
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sample_f0_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
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sample_f1_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
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sample_f2_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
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sample_f3_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
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);
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END lpp_lfr_filter;
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ARCHITECTURE tb OF lpp_lfr_filter IS
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COMPONENT Downsampling
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GENERIC (
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ChanelCount : INTEGER;
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SampleSize : INTEGER;
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DivideParam : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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sample_in_val : IN STD_LOGIC;
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sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
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sample_out_val : OUT STD_LOGIC;
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sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
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END COMPONENT;
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-----------------------------------------------------------------------------
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CONSTANT ChanelCount : INTEGER := 8;
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-----------------------------------------------------------------------------
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SIGNAL sample_val_delay : STD_LOGIC;
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-----------------------------------------------------------------------------
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CONSTANT Coef_SZ : INTEGER := 9;
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CONSTANT CoefCntPerCel : INTEGER := 6;
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CONSTANT CoefPerCel : INTEGER := 5;
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CONSTANT Cels_count : INTEGER := 5;
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SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
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SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
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--
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SIGNAL sample_filter_v2_out_sim : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
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SIGNAL sample_filter_v2_out_val : STD_LOGIC;
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SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL sample_data_shaping_out_val : STD_LOGIC;
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SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
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SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
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SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
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SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
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SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(18 DOWNTO 0);
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SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(18 DOWNTO 0);
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SIGNAL sample_data_shaping_f1_f0_saturated_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL sample_data_shaping_f2_f1_saturated_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
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SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
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SIGNAL sample_f0_s : sample_vector(7 DOWNTO 0, 15 DOWNTO 0);
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SIGNAL sample_f0_f1_s : samplT(5 DOWNTO 0, 17 DOWNTO 0);
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SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 17 DOWNTO 0);
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SIGNAL sample_f1 : samplT(5 DOWNTO 0, 17 DOWNTO 0);
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SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
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SIGNAL sample_f2_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
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SIGNAL sample_f2_cic_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0);
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SIGNAL sample_f2_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0);
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SIGNAL sample_f2_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
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SIGNAL sample_f2_cic_val : STD_LOGIC;
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SIGNAL sample_f2_filter_val : STD_LOGIC;
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SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
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SIGNAL sample_f3_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
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SIGNAL sample_f3_cic_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0);
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SIGNAL sample_f3_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0);
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SIGNAL sample_f3_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
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SIGNAL sample_f3_cic_val : STD_LOGIC;
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SIGNAL sample_f3_filter_val : STD_LOGIC;
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SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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SIGNAL sample_f0_val_s : STD_LOGIC;
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SIGNAL sample_f1_val_s : STD_LOGIC;
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SIGNAL sample_f1_val_ss : STD_LOGIC;
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SIGNAL sample_f2_val_s : STD_LOGIC;
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SIGNAL sample_f3_val_s : STD_LOGIC;
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-----------------------------------------------------------------------------
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-- CONFIG FILTER IIR f0 to f1
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-----------------------------------------------------------------------------
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CONSTANT f0_to_f1_CEL_NUMBER : INTEGER := 5;
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CONSTANT f0_to_f1_COEFFICIENT_SIZE : INTEGER := 10;
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CONSTANT f0_to_f1_POINT_POSITION : INTEGER := 8;
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CONSTANT f0_to_f1_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) :=
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(
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(1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583),
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(1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351),
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(1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102),
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(1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464),
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(1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691)
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);
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CONSTANT f0_to_f1_gain : COEFF_CEL_REAL :=
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( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0);
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CONSTANT coefs_iir_cel_f0_to_f1 : STD_LOGIC_VECTOR((f0_to_f1_CEL_NUMBER*f0_to_f1_COEFFICIENT_SIZE*5)-1 DOWNTO 0)
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:= get_IIR_CEL_FILTER_CONFIG(
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f0_to_f1_COEFFICIENT_SIZE,
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f0_to_f1_POINT_POSITION,
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f0_to_f1_CEL_NUMBER,
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f0_to_f1_sos,
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f0_to_f1_gain);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- CONFIG FILTER IIR f2 and f3
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-----------------------------------------------------------------------------
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CONSTANT f2_f3_CEL_NUMBER : INTEGER := 5;
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CONSTANT f2_f3_COEFFICIENT_SIZE : INTEGER := 10;
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CONSTANT f2_f3_POINT_POSITION : INTEGER := 8;
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CONSTANT f2_f3_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) :=
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(
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(1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583),
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(1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351),
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(1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102),
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(1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464),
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(1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691)
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);
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CONSTANT f2_f3_gain : COEFF_CEL_REAL :=
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( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0);
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CONSTANT coefs_iir_cel_f2_f3 : STD_LOGIC_VECTOR((f2_f3_CEL_NUMBER*f2_f3_COEFFICIENT_SIZE*5)-1 DOWNTO 0)
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:= get_IIR_CEL_FILTER_CONFIG(
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f2_f3_COEFFICIENT_SIZE,
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f2_f3_POINT_POSITION,
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f2_f3_CEL_NUMBER,
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f2_f3_sos,
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f2_f3_gain);
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-----------------------------------------------------------------------------
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SIGNAL sample_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL sample_f0_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL sample_f1_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL sample_f2_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL sample_f3_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL sample_f0_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL sample_f1_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL sample_filter_v2_out_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
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BEGIN
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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sample_val_delay <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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sample_val_delay <= sample_val;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
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SampleLoop : FOR j IN 0 TO 15 GENERATE
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sample_filter_in(i, j) <= sample(i)(j);
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END GENERATE;
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sample_filter_in(i, 16) <= sample(i)(15);
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sample_filter_in(i, 17) <= sample(i)(15);
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END GENERATE;
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coefs_v2 <= CoefsInitValCst_v2;
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IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
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GENERIC MAP (
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tech => tech,
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Mem_use => Mem_use, -- use_RAM
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Sample_SZ => 18,
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Coef_SZ => Coef_SZ,
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Coef_Nb => 25,
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Coef_sel_SZ => 5,
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Cels_count => Cels_count,
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ChanelsCount => ChanelCount)
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PORT MAP (
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rstn => rstn,
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clk => clk,
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virg_pos => 7,
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coefs => coefs_v2,
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sample_in_val => sample_val_delay,
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sample_in => sample_filter_in,
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sample_out_val => sample_filter_v2_out_val,
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sample_out => sample_filter_v2_out);
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-- TIME --
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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sample_time_reg <= (OTHERS => '0');
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sample_filter_v2_out_time <= (OTHERS => '0');
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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IF sample_val = '1' THEN
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sample_time_reg <= sample_time;
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END IF;
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IF sample_filter_v2_out_val = '1' THEN
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sample_filter_v2_out_time <= sample_time_reg;
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END IF;
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END IF;
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END PROCESS;
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----------
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--for simulation/observation-------------------------------------------------
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ALL_channel_f0_sim: FOR I IN 0 TO ChanelCount-1 GENERATE
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all_bit: FOR J IN 0 TO 17 GENERATE
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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sample_filter_v2_out_sim(I,J) <= '0';
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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IF sample_filter_v2_out_val = '1' THEN
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sample_filter_v2_out_sim(I,J) <= sample_filter_v2_out(I,J);
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END IF;
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END IF;
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END PROCESS;
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END GENERATE all_bit;
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END GENERATE ALL_channel_f0_sim;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- DATA_SHAPING
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-----------------------------------------------------------------------------
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all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
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sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
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sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
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sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
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END GENERATE all_data_shaping_in_loop;
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sample_data_shaping_f1_f0_s <= STD_LOGIC_VECTOR(resize( SIGNED(sample_data_shaping_f1_s) - SIGNED(sample_data_shaping_f0_s),19));
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sample_data_shaping_f2_f1_s <= STD_LOGIC_VECTOR(resize( SIGNED(sample_data_shaping_f2_s) - SIGNED(sample_data_shaping_f1_s),19));
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|
|
|
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|
DATA_SHAPING_SATURATION_ENABLED: if DATA_SHAPING_SATURATION = 1 generate
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|
|
saturation_SP0 : saturation
|
|
|
generic map (
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|
SIZE_INPUT => 19,
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|
SIZE_OUTPUT => 16)
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|
|
port map (
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s_in => sample_data_shaping_f1_f0_s,
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|
|
s_out => sample_data_shaping_f1_f0_saturated_s );
|
|
|
|
|
|
saturation_SP1 : saturation
|
|
|
generic map (
|
|
|
SIZE_INPUT => 19,
|
|
|
SIZE_OUTPUT => 16)
|
|
|
port map (
|
|
|
s_in => sample_data_shaping_f2_f1_s,
|
|
|
s_out => sample_data_shaping_f2_f1_saturated_s );
|
|
|
end generate DATA_SHAPING_SATURATION_ENABLED;
|
|
|
|
|
|
DATA_SHAPING_SATURATION_DISABLED: if DATA_SHAPING_SATURATION = 0 generate
|
|
|
sample_data_shaping_f1_f0_saturated_s <= sample_data_shaping_f1_f0_s(16 downto 1);
|
|
|
sample_data_shaping_f2_f1_saturated_s <= sample_data_shaping_f2_f1_s(16 downto 1);
|
|
|
end generate DATA_SHAPING_SATURATION_DISABLED;
|
|
|
|
|
|
PROCESS (clk, rstn)
|
|
|
BEGIN -- PROCESS
|
|
|
IF rstn = '0' THEN -- asynchronous reset (active low)
|
|
|
sample_data_shaping_out_val <= '0';
|
|
|
ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
|
|
|
sample_data_shaping_out_val <= sample_filter_v2_out_val;
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
|
|
|
SampleLoop_data_shaping : FOR j IN 0 TO 15 GENERATE
|
|
|
PROCESS (clk, rstn)
|
|
|
BEGIN
|
|
|
IF rstn = '0' THEN
|
|
|
sample_data_shaping_out(0, j) <= '0';
|
|
|
sample_data_shaping_out(1, j) <= '0';
|
|
|
sample_data_shaping_out(2, j) <= '0';
|
|
|
sample_data_shaping_out(3, j) <= '0';
|
|
|
sample_data_shaping_out(4, j) <= '0';
|
|
|
sample_data_shaping_out(5, j) <= '0';
|
|
|
sample_data_shaping_out(6, j) <= '0';
|
|
|
sample_data_shaping_out(7, j) <= '0';
|
|
|
ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
|
|
|
sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
|
|
|
IF data_shaping_SP0 = '1' THEN
|
|
|
sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_saturated_s(j);
|
|
|
ELSE
|
|
|
sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
|
|
|
END IF;
|
|
|
IF data_shaping_SP1 = '1' THEN
|
|
|
sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_saturated_s(j);
|
|
|
ELSE
|
|
|
sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
|
|
|
END IF;
|
|
|
sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
|
|
|
sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
|
|
|
sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
|
|
|
sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
|
|
|
sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
END GENERATE;
|
|
|
|
|
|
sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
|
|
|
ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
|
|
|
SampleLoopOut : FOR j IN 0 TO 15 GENERATE
|
|
|
sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j);
|
|
|
END GENERATE;
|
|
|
END GENERATE;
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- F0 -- @24.576 kHz
|
|
|
-----------------------------------------------------------------------------
|
|
|
|
|
|
Downsampling_f0 : Downsampling
|
|
|
GENERIC MAP (
|
|
|
ChanelCount => 8,
|
|
|
SampleSize => 16,
|
|
|
DivideParam => 4)
|
|
|
PORT MAP (
|
|
|
clk => clk,
|
|
|
rstn => rstn,
|
|
|
sample_in_val => sample_filter_v2_out_val_s,
|
|
|
sample_in => sample_filter_v2_out_s,
|
|
|
sample_out_val => sample_f0_val_s,
|
|
|
sample_out => sample_f0);
|
|
|
|
|
|
-- TIME --
|
|
|
PROCESS (clk, rstn)
|
|
|
BEGIN
|
|
|
IF rstn = '0' THEN
|
|
|
sample_f0_time_reg <= (OTHERS => '0');
|
|
|
ELSIF clk'event AND clk = '1' THEN
|
|
|
IF sample_f0_val_s = '1' THEN
|
|
|
sample_f0_time_reg <= sample_filter_v2_out_time;
|
|
|
END IF;
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
sample_f0_time_s <= sample_filter_v2_out_time WHEN sample_f0_val_s = '1' ELSE sample_f0_time_reg;
|
|
|
sample_f0_time <= sample_f0_time_s;
|
|
|
----------
|
|
|
|
|
|
sample_f0_val <= sample_f0_val_s;
|
|
|
|
|
|
all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
|
|
|
sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
|
|
|
sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
|
|
|
sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2
|
|
|
sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1
|
|
|
sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2
|
|
|
sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3
|
|
|
END GENERATE all_bit_sample_f0;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- F1 -- @4096 Hz
|
|
|
-----------------------------------------------------------------------------
|
|
|
|
|
|
all_bit_sample_f0_f1 : FOR I IN 15 DOWNTO 0 GENERATE
|
|
|
sample_f0_f1_s(0,I) <= sample_f0(0,I); --V
|
|
|
sample_f0_f1_s(1,I) <= sample_f0(1,I) WHEN data_shaping_R1 = '1' ELSE sample_f0(3,I); --E1
|
|
|
sample_f0_f1_s(2,I) <= sample_f0(2,I) WHEN data_shaping_R1 = '1' ELSE sample_f0(4,I); --E2
|
|
|
sample_f0_f1_s(3,I) <= sample_f0(5,I); --B1
|
|
|
sample_f0_f1_s(4,I) <= sample_f0(6,I); --B2
|
|
|
sample_f0_f1_s(5,I) <= sample_f0(7,I); --B3
|
|
|
END GENERATE all_bit_sample_f0_f1;
|
|
|
all_bit_sample_f0_f1_extended : FOR I IN 17 DOWNTO 16 GENERATE
|
|
|
sample_f0_f1_s(0,I) <= sample_f0(0,15);
|
|
|
sample_f0_f1_s(1,I) <= sample_f0(1,15) WHEN data_shaping_R1 = '1' ELSE sample_f0(3,15); --E1
|
|
|
sample_f0_f1_s(2,I) <= sample_f0(2,15) WHEN data_shaping_R1 = '1' ELSE sample_f0(4,15); --E2
|
|
|
sample_f0_f1_s(3,I) <= sample_f0(5,15); --B1
|
|
|
sample_f0_f1_s(4,I) <= sample_f0(6,15); --B2
|
|
|
sample_f0_f1_s(5,I) <= sample_f0(7,15); --B3
|
|
|
END GENERATE all_bit_sample_f0_f1_extended;
|
|
|
|
|
|
|
|
|
IIR_CEL_f0_to_f1 : IIR_CEL_CTRLR_v2
|
|
|
GENERIC MAP (
|
|
|
tech => tech,
|
|
|
Mem_use => Mem_use, -- use_RAM
|
|
|
Sample_SZ => 18,
|
|
|
Coef_SZ => f0_to_f1_COEFFICIENT_SIZE,
|
|
|
Coef_Nb => f0_to_f1_CEL_NUMBER*5,
|
|
|
Coef_sel_SZ => 5,
|
|
|
Cels_count => f0_to_f1_CEL_NUMBER,
|
|
|
ChanelsCount => 6)
|
|
|
PORT MAP (
|
|
|
rstn => rstn,
|
|
|
clk => clk,
|
|
|
virg_pos => f0_to_f1_POINT_POSITION,
|
|
|
coefs => coefs_iir_cel_f0_to_f1,
|
|
|
|
|
|
sample_in_val => sample_f0_val_s,
|
|
|
sample_in => sample_f0_f1_s,
|
|
|
|
|
|
sample_out_val => sample_f1_val_s,
|
|
|
sample_out => sample_f1_s);
|
|
|
|
|
|
Downsampling_f1 : Downsampling
|
|
|
GENERIC MAP (
|
|
|
ChanelCount => 6,
|
|
|
SampleSize => 18,
|
|
|
DivideParam => 6)
|
|
|
PORT MAP (
|
|
|
clk => clk,
|
|
|
rstn => rstn,
|
|
|
sample_in_val => sample_f1_val_s,
|
|
|
sample_in => sample_f1_s,
|
|
|
sample_out_val => sample_f1_val_ss,
|
|
|
sample_out => sample_f1);
|
|
|
|
|
|
sample_f1_val <= sample_f1_val_ss;
|
|
|
|
|
|
-- TIME --
|
|
|
PROCESS (clk, rstn)
|
|
|
BEGIN
|
|
|
IF rstn = '0' THEN
|
|
|
sample_f1_time_reg <= (OTHERS => '0');
|
|
|
ELSIF clk'event AND clk = '1' THEN
|
|
|
IF sample_f1_val_ss = '1' THEN
|
|
|
sample_f1_time_reg <= sample_f0_time_s;
|
|
|
END IF;
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
sample_f1_time_s <= sample_f0_time_s WHEN sample_f1_val_ss = '1' ELSE sample_f1_time_reg;
|
|
|
sample_f1_time <= sample_f1_time_s;
|
|
|
----------
|
|
|
|
|
|
|
|
|
all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
|
|
|
all_channel_sample_f1: FOR J IN 5 DOWNTO 0 GENERATE
|
|
|
sample_f1_wdata_s(16*J+I) <= sample_f1(J, I);
|
|
|
END GENERATE all_channel_sample_f1;
|
|
|
END GENERATE all_bit_sample_f1;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- F2 -- @256 Hz
|
|
|
-- F3 -- @16 Hz
|
|
|
-----------------------------------------------------------------------------
|
|
|
all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
|
|
|
sample_f0_s(0, I) <= sample_f0(0, I); -- V
|
|
|
sample_f0_s(1, I) <= sample_f0(1, I); -- E1
|
|
|
sample_f0_s(2, I) <= sample_f0(2, I); -- E2
|
|
|
sample_f0_s(3, I) <= sample_f0(5, I); -- B1
|
|
|
sample_f0_s(4, I) <= sample_f0(6, I); -- B2
|
|
|
sample_f0_s(5, I) <= sample_f0(7, I); -- B3
|
|
|
sample_f0_s(6, I) <= sample_f0(3, I); --
|
|
|
sample_f0_s(7, I) <= sample_f0(4, I); --
|
|
|
END GENERATE all_bit_sample_f0_s;
|
|
|
|
|
|
|
|
|
cic_lfr_1: cic_lfr_r2
|
|
|
GENERIC MAP (
|
|
|
tech => tech,
|
|
|
use_RAM_nCEL => Mem_use)
|
|
|
PORT MAP (
|
|
|
clk => clk,
|
|
|
rstn => rstn,
|
|
|
run => '1',
|
|
|
|
|
|
param_r2 => data_shaping_R2,
|
|
|
|
|
|
data_in => sample_f0_s,
|
|
|
data_in_valid => sample_f0_val_s,
|
|
|
|
|
|
data_out_16 => sample_f2_cic,
|
|
|
data_out_16_valid => sample_f2_cic_val,
|
|
|
|
|
|
data_out_256 => sample_f3_cic,
|
|
|
data_out_256_valid => sample_f3_cic_val);
|
|
|
|
|
|
|
|
|
|
|
|
all_channel_sample_f_cic : FOR J IN 5 DOWNTO 0 GENERATE
|
|
|
all_bit_sample_f_cic : FOR I IN 15 DOWNTO 0 GENERATE
|
|
|
sample_f2_cic_filter(J,I) <= sample_f2_cic(J,I);
|
|
|
sample_f3_cic_filter(J,I) <= sample_f3_cic(J,I);
|
|
|
END GENERATE all_bit_sample_f_cic;
|
|
|
sample_f2_cic_filter(J,16) <= sample_f2_cic(J,15);
|
|
|
sample_f2_cic_filter(J,17) <= sample_f2_cic(J,15);
|
|
|
|
|
|
sample_f3_cic_filter(J,16) <= sample_f3_cic(J,15);
|
|
|
sample_f3_cic_filter(J,17) <= sample_f3_cic(J,15);
|
|
|
END GENERATE all_channel_sample_f_cic;
|
|
|
|
|
|
NO_IIR_FILTER_f2_f3: IF RTL_DESIGN_LIGHT = 1 GENERATE
|
|
|
sample_f2_filter_val <= sample_f2_cic_val;
|
|
|
sample_f2_filter <= sample_f2_cic_filter;
|
|
|
sample_f3_filter_val <= sample_f3_cic_val;
|
|
|
sample_f3_filter <= sample_f3_cic_filter;
|
|
|
END GENERATE NO_IIR_FILTER_f2_f3;
|
|
|
|
|
|
YES_IIR_FILTER_f2_f3: IF RTL_DESIGN_LIGHT = 0 GENERATE
|
|
|
IIR_CEL_CTRLR_v3_1:IIR_CEL_CTRLR_v3
|
|
|
GENERIC MAP (
|
|
|
tech => tech,
|
|
|
Mem_use => Mem_use,
|
|
|
Sample_SZ => 18,
|
|
|
Coef_SZ => f2_f3_COEFFICIENT_SIZE,
|
|
|
Coef_Nb => f2_f3_CEL_NUMBER*5,
|
|
|
Coef_sel_SZ => 5,
|
|
|
Cels_count => f2_f3_CEL_NUMBER,
|
|
|
ChanelsCount => 6)
|
|
|
PORT MAP (
|
|
|
rstn => rstn,
|
|
|
clk => clk,
|
|
|
virg_pos => f2_f3_POINT_POSITION,
|
|
|
coefs => coefs_iir_cel_f2_f3,
|
|
|
|
|
|
sample_in1_val => sample_f2_cic_val,
|
|
|
sample_in1 => sample_f2_cic_filter,
|
|
|
|
|
|
sample_in2_val => sample_f3_cic_val,
|
|
|
sample_in2 => sample_f3_cic_filter,
|
|
|
|
|
|
sample_out1_val => sample_f2_filter_val,
|
|
|
sample_out1 => sample_f2_filter,
|
|
|
sample_out2_val => sample_f3_filter_val,
|
|
|
sample_out2 => sample_f3_filter);
|
|
|
END GENERATE YES_IIR_FILTER_f2_f3;
|
|
|
|
|
|
all_channel_sample_f_filter : FOR J IN 5 DOWNTO 0 GENERATE
|
|
|
all_bit_sample_f_filter : FOR I IN 15 DOWNTO 0 GENERATE
|
|
|
sample_f2_cic_s(J,I) <= sample_f2_filter(J,I);
|
|
|
sample_f3_cic_s(J,I) <= sample_f3_filter(J,I);
|
|
|
END GENERATE all_bit_sample_f_filter;
|
|
|
END GENERATE all_channel_sample_f_filter;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
|
|
|
Downsampling_f2 : Downsampling
|
|
|
GENERIC MAP (
|
|
|
ChanelCount => 6,
|
|
|
SampleSize => 16,
|
|
|
DivideParam => 6)
|
|
|
PORT MAP (
|
|
|
clk => clk,
|
|
|
rstn => rstn,
|
|
|
sample_in_val => sample_f2_filter_val ,
|
|
|
sample_in => sample_f2_cic_s,
|
|
|
sample_out_val => sample_f2_val_s,
|
|
|
sample_out => sample_f2);
|
|
|
|
|
|
sample_f2_val <= sample_f2_val_s;
|
|
|
|
|
|
all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
|
|
|
all_channel_sample_f2 : FOR J IN 5 DOWNTO 0 GENERATE
|
|
|
sample_f2_wdata_s(16*J+I) <= sample_f2(J,I);
|
|
|
END GENERATE all_channel_sample_f2;
|
|
|
END GENERATE all_bit_sample_f2;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
|
|
|
Downsampling_f3 : Downsampling
|
|
|
GENERIC MAP (
|
|
|
ChanelCount => 6,
|
|
|
SampleSize => 16,
|
|
|
DivideParam => 6)
|
|
|
PORT MAP (
|
|
|
clk => clk,
|
|
|
rstn => rstn,
|
|
|
sample_in_val => sample_f3_filter_val ,
|
|
|
sample_in => sample_f3_cic_s,
|
|
|
sample_out_val => sample_f3_val_s,
|
|
|
sample_out => sample_f3);
|
|
|
sample_f3_val <= sample_f3_val_s;
|
|
|
|
|
|
all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
|
|
|
all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE
|
|
|
sample_f3_wdata_s(16*J+I) <= sample_f3(J,I);
|
|
|
END GENERATE all_channel_sample_f3;
|
|
|
END GENERATE all_bit_sample_f3;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
|
|
|
-- TIME --
|
|
|
PROCESS (clk, rstn)
|
|
|
BEGIN
|
|
|
IF rstn = '0' THEN
|
|
|
sample_f2_time_reg <= (OTHERS => '0');
|
|
|
sample_f3_time_reg <= (OTHERS => '0');
|
|
|
ELSIF clk'event AND clk = '1' THEN
|
|
|
IF sample_f2_val_s = '1' THEN sample_f2_time_reg <= sample_f0_time_s; END IF;
|
|
|
IF sample_f3_val_s = '1' THEN sample_f3_time_reg <= sample_f0_time_s; END IF;
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
sample_f2_time <= sample_f0_time_s WHEN sample_f2_val_s = '1' ELSE sample_f2_time_reg;
|
|
|
sample_f3_time <= sample_f0_time_s WHEN sample_f3_val_s = '1' ELSE sample_f3_time_reg;
|
|
|
----------
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
--
|
|
|
-----------------------------------------------------------------------------
|
|
|
sample_f0_wdata <= sample_f0_wdata_s;
|
|
|
sample_f1_wdata <= sample_f1_wdata_s;
|
|
|
sample_f2_wdata <= sample_f2_wdata_s;
|
|
|
sample_f3_wdata <= sample_f3_wdata_s;
|
|
|
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END tb;
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