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--************************************************************************
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--** MODEL : package_timing.vhd **
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--** COMPANY : Cypress Semiconductor **
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--** REVISION: 1.0 (Created new timing package model) **
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--************************************************************************
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library IEEE,std;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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use ieee.std_logic_textio.all ;
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use std.textio.all ;
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--****************************************************************
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package package_timing is
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------------------------------------------------------------------------------------------------
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-- Read Cycle timing
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------------------------------------------------------------------------------------------------
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constant tRC : TIME := 10 ns; -- Read Cycle Time
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constant tAA : TIME := 10 ns; -- Address to Data Valid
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constant tOHA : TIME := 3 ns; -- Data Hold from Address Change
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constant tACE : TIME := 10 ns; -- Random access CEb Low to Data Valid
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constant tDOE : TIME := 5 ns; -- OE Low to Data Valid
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constant tLZOE : TIME := 1 ns; -- OE Low to LOW Z
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constant tHZOE : TIME := 5 ns; -- OE High to HIGH Z
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constant tLZCE : TIME := 3 ns; -- CEb LOW to LOW Z
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constant tHZCE : TIME := 5 ns; -- CEb HIGH to HIGH Z
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constant tDBE : TIME := 5 ns; -- BHE/BLE LOW to Data Valid
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constant tLZBE : TIME := 1 ns; -- BHE/BLE LOW to LOW Z
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constant tHZBE : TIME := 5 ns; -- BHE/BLE HIGH to HIGH Z
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------------------------------------------------------------------------------------------------
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-- Write Cycle timing
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------------------------------------------------------------------------------------------------
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constant tWC : TIME := 10 ns; -- Write Cycle Time
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constant tSCE : TIME := 7 ns; -- CEb LOW to Write End
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constant tAW : TIME := 7 ns; -- Address Setup to Write End
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constant tSA : TIME := 0 ns; -- Address Setup to Write Start
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constant tHA : TIME := 0 ns; -- Address Hold from Write End
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constant tPWE : TIME := 7 ns; -- WEb pulse width
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constant tSD : TIME := 5.5 ns; -- Data Setup to Write End
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constant tHD : TIME := 0 ns; -- Data Hold from Write End
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constant tBW : TIME := 7 ns; -- BHE BLE Setup to Write End
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constant tLZWE : TIME := 3 ns; -- WEb Low to High Z
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constant tHZWE : TIME := 5 ns; -- WEb High to Low Z
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end package_timing;
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package body package_timing is
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end package_timing;
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