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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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library lpp;
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use lpp.FILTERcfg.all;
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package iir_filter is
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component APB_IIR_CEL is
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generic (
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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pirq : integer := 0;
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abits : integer := 8;
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Sample_SZ : integer := Smpl_SZ
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);
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port (
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rst : in std_logic;
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clk : in std_logic;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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sample_clk : in std_logic;
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sample_clk_out : out std_logic;
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sample_in : in samplT;
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sample_out : out samplT
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);
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end component;
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component FILTER is
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port(
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reset : in std_logic;
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clk : in std_logic;
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sample_clk : in std_logic;
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Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0);
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Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0)
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);
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end component;
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component FilterCTRLR is
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port(
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reset : in std_logic;
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clk : in std_logic;
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sample_clk : in std_logic;
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ALU_Ctrl : out std_logic_vector(3 downto 0);
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sample_in : in samplT;
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coef : out std_logic_vector(Coef_SZ-1 downto 0);
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sample : out std_logic_vector(Smpl_SZ-1 downto 0)
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);
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end component;
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component FILTER_RAM_CTRLR is
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port(
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reset : in std_logic;
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clk : in std_logic;
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run : in std_logic;
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GO_0 : in std_logic;
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B_A : in std_logic;
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writeForce : in std_logic;
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next_blk : in std_logic;
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sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
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sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
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);
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end component;
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component IIR_CEL_CTRLR is
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generic(Sample_SZ : integer := 16);
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port(
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reset : in std_logic;
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clk : in std_logic;
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sample_clk : in std_logic;
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sample_in : in samplT;
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sample_out : out samplT;
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virg_pos : in integer;
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coefs : in coefs_celsT
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);
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end component;
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component RAM is
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port( WD : in std_logic_vector(35 downto 0); RD : out
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std_logic_vector(35 downto 0);WEN, REN : in std_logic;
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WADDR : in std_logic_vector(7 downto 0); RADDR : in
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std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
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) ;
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end component;
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component RAM_CEL is
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port( WD : in std_logic_vector(35 downto 0); RD : out
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std_logic_vector(35 downto 0);WEN, REN : in std_logic;
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WADDR : in std_logic_vector(7 downto 0); RADDR : in
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std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
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) ;
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end component;
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component IIR_CEL_FILTER is
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generic(Sample_SZ : integer := 16);
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port(
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reset : in std_logic;
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clk : in std_logic;
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sample_clk : in std_logic;
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regs_in : in in_IIR_CEL_reg;
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regs_out : in out_IIR_CEL_reg;
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sample_in : in samplT;
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sample_out : out samplT
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);
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end component;
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component RAM_CTRLR2 is
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generic(
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Input_SZ_1 : integer := 16
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);
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port(
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reset : in std_logic;
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clk : in std_logic;
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WD_sel : in std_logic;
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Read : in std_logic;
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WADDR_sel : in std_logic;
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count : in std_logic;
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SVG_ADDR : in std_logic;
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Write : in std_logic;
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GO_0 : in std_logic;
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sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
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sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
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);
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end component;
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end;
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