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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- RAM_CTRLR2.vhd
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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library lpp;
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use lpp.iir_filter.all;
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use lpp.FILTERcfg.all;
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use lpp.general_purpose.all;
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--TODO am�liorer la flexibilit� de la config de la RAM.
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entity RAM_CTRLR2 is
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generic(
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Input_SZ_1 : integer := 16
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);
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port(
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reset : in std_logic;
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clk : in std_logic;
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WD_sel : in std_logic;
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Read : in std_logic;
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WADDR_sel : in std_logic;
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count : in std_logic;
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SVG_ADDR : in std_logic;
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Write : in std_logic;
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GO_0 : in std_logic;
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sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
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sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
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);
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end RAM_CTRLR2;
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architecture ar_RAM_CTRLR2 of RAM_CTRLR2 is
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signal WD : std_logic_vector(35 downto 0);
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signal WD_D : std_logic_vector(35 downto 0);
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signal RD : std_logic_vector(35 downto 0);
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signal WEN, REN : std_logic;
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signal WADDR_back : std_logic_vector(7 downto 0);
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signal WADDR_back_D: std_logic_vector(7 downto 0);
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signal RADDR : std_logic_vector(7 downto 0);
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signal WADDR : std_logic_vector(7 downto 0);
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signal WADDR_D : std_logic_vector(7 downto 0);
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begin
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sample_out <= RD(Smpl_SZ-1 downto 0);
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WEN <= not Write;
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REN <= not read;
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--==============================================================
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--=========================R A M================================
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--==============================================================
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memRAM : if Mem_use = use_RAM generate
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RAMblk :RAM
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port map(
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WD => WD_D,
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RD => RD,
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WEN => WEN,
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REN => REN,
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WADDR => WADDR,
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RADDR => RADDR,
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RWCLK => clk,
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RESET => reset
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) ;
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end generate;
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memCEL : if Mem_use = use_CEL generate
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RAMblk :RAM_CEL
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port map(
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WD => WD_D,
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RD => RD,
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WEN => WEN,
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REN => REN,
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WADDR => WADDR,
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RADDR => RADDR,
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RWCLK => clk,
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RESET => reset
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) ;
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end generate;
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--==============================================================
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--==============================================================
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ADDRcntr_inst : ADDRcntr
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port map(
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clk => clk,
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reset => reset,
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count => count,
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clr => GO_0,
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Q => RADDR
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);
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MUX2_inst1 :MUX2
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generic map(Input_SZ => Smpl_SZ)
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port map(
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sel => WD_sel,
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IN1 => sample_in,
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IN2 => RD(Smpl_SZ-1 downto 0),
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RES => WD(Smpl_SZ-1 downto 0)
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);
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MUX2_inst2 :MUX2
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generic map(Input_SZ => 8)
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port map(
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sel => WADDR_sel,
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IN1 => WADDR_D,
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IN2 => WADDR_back_D,
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RES => WADDR
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);
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WADDR_backreg :REG
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generic map(size => 8,initial_VALUE =>ChanelsCNT*Cels_count*4-2)
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port map(
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reset => reset,
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clk => SVG_ADDR,
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D => RADDR,
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Q => WADDR_back
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);
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WADDR_backreg2 :REG
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generic map(size => 8)
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port map(
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reset => reset,
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clk => SVG_ADDR,
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D => WADDR_back,
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Q => WADDR_back_D
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);
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WDRreg :REG
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generic map(size => Smpl_SZ)
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port map(
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reset => reset,
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clk => clk,
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D => WD(Smpl_SZ-1 downto 0),
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Q => WD_D(Smpl_SZ-1 downto 0)
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);
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ADDRreg :REG
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generic map(size => 8)
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port map(
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reset => reset,
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clk => clk,
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D => RADDR,
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Q => WADDR_D
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);
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end ar_RAM_CTRLR2;
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