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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- RAM_CEL.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity RAM_CEL is
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port( WD : in std_logic_vector(35 downto 0); RD : out
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std_logic_vector(35 downto 0);WEN, REN : in std_logic;
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WADDR : in std_logic_vector(7 downto 0); RADDR : in
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std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
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) ;
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end RAM_CEL;
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architecture ar_RAM_CEL of RAM_CEL is
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type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0);
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signal RAMarray : RAMarrayT:=(others => X"000000000");
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signal RD_int : std_logic_vector(35 downto 0);
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begin
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RD_int <= RAMarray(to_integer(unsigned(RADDR)));
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process(RWclk,reset)
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begin
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if reset = '0' then
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RD <= (X"000000000");
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rst:for i in 0 to 255 loop
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RAMarray(i) <= (others => '0');
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end loop;
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elsif RWclk'event and RWclk = '1' then
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if REN = '0' then
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RD <= RD_int;
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end if;
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if WEN = '0' then
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RAMarray(to_integer(unsigned(WADDR))) <= WD;
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end if;
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end if;
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end process;
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end ar_RAM_CEL;
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