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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- IIR_CEL_FILTER.vhd
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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library lpp;
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use lpp.iir_filter.all;
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use lpp.FILTERcfg.all;
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use lpp.general_purpose.all;
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--TODO am�liorer la gestion de la RAM et de la flexibilit� du filtre
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entity IIR_CEL_FILTER is
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generic(Sample_SZ : integer := 16);
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port(
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reset : in std_logic;
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clk : in std_logic;
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sample_clk : in std_logic;
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regs_in : in in_IIR_CEL_reg;
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regs_out : in out_IIR_CEL_reg;
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sample_in : in samplT;
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sample_out : out samplT
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);
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end IIR_CEL_FILTER;
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architecture ar_IIR_CEL_FILTER of IIR_CEL_FILTER is
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signal virg_pos : integer;
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begin
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virg_pos <= to_integer(unsigned(regs_in.virgPos));
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CTRLR : IIR_CEL_CTRLR
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generic map (Sample_SZ => Sample_SZ)
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port map(
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reset => reset,
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clk => clk,
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sample_clk => sample_clk,
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sample_in => sample_in,
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sample_out => sample_out,
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virg_pos => virg_pos,
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coefs => regs_in.coefsTB
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);
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end ar_IIR_CEL_FILTER;
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