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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.numeric_std.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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library lpp;
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use lpp.amba_lcd_16x2_ctrlr.all;
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use lpp.LCD_16x2_CFG.all;
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use lpp.lpp_amba.all;
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entity apb_lcd_ctrlr is
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generic (
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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pirq : integer := 0;
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abits : integer := 8);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
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LCD_RS : out STD_LOGIC;
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LCD_RW : out STD_LOGIC;
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LCD_E : out STD_LOGIC;
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LCD_RET : out STD_LOGIC;
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LCD_CS1 : out STD_LOGIC;
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LCD_CS2 : out STD_LOGIC;
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SF_CE0 : out std_logic
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);
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end apb_lcd_ctrlr;
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architecture Behavioral of apb_lcd_ctrlr is
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signal FramBUFF : FRM_Buff_Space;
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signal CMD : std_logic_vector(10 downto 0);
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signal Exec : std_logic;
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signal Ready : std_logic;
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signal LCD_CTRL : LCD_DRVR_CTRL_BUSS;
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constant REVISION : integer := 1;
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constant pconfig : apb_config_type := (
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0 => ahb_device_reg (VENDOR_LPP, LPP_LCD_CTRLR, 0, REVISION, 0),
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1 => apb_iobar(paddr, pmask));
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--type FRM_Buff_El is std_logic_vector(31 downto 0);
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type FRM_Buff_Reg is array(lcd_space_size-1 downto 0) of std_logic_vector(31 downto 0);
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type LCD_ctrlr_Reg is record
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CTRL_Reg : std_logic_vector(31 downto 0);
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FRAME_BUFF : FRM_Buff_Reg;
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end record;
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signal r : LCD_ctrlr_Reg;
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signal Rdata : std_logic_vector(31 downto 0);
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begin
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LCD_data <= LCD_CTRL.LCD_DATA;
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LCD_RS <= LCD_CTRL.LCD_RS;
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LCD_RW <= LCD_CTRL.LCD_RW;
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LCD_E <= LCD_CTRL.LCD_E;
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LCD_RET <= '0';
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LCD_CS1 <= '0';
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LCD_CS2 <= '0';
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SF_CE0 <= '1';
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CMD(7 downto 0) <= r.CTRL_Reg(7 downto 0); --CMD value
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CMD(9 downto 8) <= r.CTRL_Reg(9 downto 8); --CMD tempo value
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r.CTRL_Reg(10) <= Ready;
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Driver0 : LCD_16x2_ENGINE
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generic map(50000)
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Port map(clk,rst,FramBUFF,CMD,Exec,Ready,LCD_CTRL);
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FRM_BF : for i in 0 to lcd_space_size-1 generate
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FramBUFF(i) <= r.FRAME_BUFF(i)(7 downto 0);
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end generate;
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process(rst,clk)
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begin
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if rst = '0' then
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r.CTRL_Reg(9 downto 0) <= (others => '0');
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Exec <= '0';
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elsif clk'event and clk = '1' then
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--APB Write OP
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if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
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case apbi.paddr(7 downto 2) is
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when "000000" =>
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r.CTRL_Reg(9 downto 0) <= apbi.pwdata(9 downto 0);
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Exec <= '1';
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when others =>
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writeC: for i in 1 to lcd_space_size loop
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if TO_INTEGER(unsigned(apbi.paddr(abits-1 downto 2))) =i then
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r.FRAME_BUFF(i-1) <= apbi.pwdata;
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end if;
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Exec <= '0';
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end loop;
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end case;
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else
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Exec <= '0';
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end if;
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--APB READ OP
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if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
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case apbi.paddr(7 downto 2) is
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when "000000" =>
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Rdata <= r.CTRL_Reg;
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when others =>
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readC: for i in 1 to lcd_space_size loop
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if TO_INTEGER(unsigned(apbi.paddr(abits-1 downto 2))) =i then
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Rdata(7 downto 0) <= r.FRAME_BUFF(i-1)(7 downto 0);
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end if;
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end loop;
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end case;
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end if;
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end if;
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apbo.pconfig <= pconfig;
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end process;
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apbo.prdata <= Rdata when apbi.penable = '1' ;
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end Behavioral;
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