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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE std.textio.ALL;
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LIBRARY lpp;
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USE lpp.lpp_amba.ALL;
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USE lpp.iir_filter.ALL;
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LIBRARY gaisler;
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USE gaisler.misc.ALL;
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USE gaisler.memctrl.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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--! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
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PACKAGE lpp_memory IS
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COMPONENT lpp_fifo
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GENERIC (
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tech : INTEGER;
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Mem_use : INTEGER;
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DataSz : INTEGER RANGE 1 TO 32;
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AddrSz : INTEGER RANGE 2 TO 12);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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reUse : IN STD_LOGIC;
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ren : IN STD_LOGIC;
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rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
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wen : IN STD_LOGIC;
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wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
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empty : OUT STD_LOGIC;
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full : OUT STD_LOGIC;
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almost_full : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT lppFIFOxN
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GENERIC (
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tech : INTEGER;
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Mem_use : INTEGER;
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Data_sz : INTEGER RANGE 1 TO 32;
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Addr_sz : INTEGER RANGE 2 TO 12;
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FifoCnt : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
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wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
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wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
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ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
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rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
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empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
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full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
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almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0));
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END COMPONENT;
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COMPONENT APB_FIFO IS
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GENERIC (
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tech : INTEGER := apa3;
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pindex : INTEGER := 0;
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paddr : INTEGER := 0;
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pmask : INTEGER := 16#fff#;
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pirq : INTEGER := 0;
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abits : INTEGER := 8;
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FifoCnt : INTEGER := 2;
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Data_sz : INTEGER := 16;
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Addr_sz : INTEGER := 9;
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Enable_ReUse : STD_LOGIC := '0';
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Mem_use : INTEGER := use_RAM;
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R : INTEGER := 1;
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W : INTEGER := 1
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);
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PORT (
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clk : IN STD_LOGIC; --! Horloge du composant
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rst : IN STD_LOGIC; --! Reset general du composant
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rclk : IN STD_LOGIC;
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wclk : IN STD_LOGIC;
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ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
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REN : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Instruction de lecture en m�moire
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WEN : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Instruction d'�criture en m�moire
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Empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Flag, M�moire vide
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Full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Flag, M�moire pleine
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RDATA : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); --! Registre de donn�es en entr�e
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WDATA : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); --! Registre de donn�es en sortie
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WADDR : OUT STD_LOGIC_VECTOR((FifoCnt*Addr_sz)-1 DOWNTO 0); --! Registre d'addresse (�criture)
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RADDR : OUT STD_LOGIC_VECTOR((FifoCnt*Addr_sz)-1 DOWNTO 0); --! Registre d'addresse (lecture)
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apbi : IN apb_slv_in_type; --! Registre de gestion des entr�es du bus
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apbo : OUT apb_slv_out_type --! Registre de gestion des sorties du bus
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);
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END COMPONENT;
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COMPONENT FIFO_pipeline IS
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GENERIC(
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tech : INTEGER := 0;
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Mem_use : INTEGER := use_RAM;
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fifoCount : INTEGER RANGE 2 TO 32 := 8;
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DataSz : INTEGER RANGE 1 TO 32 := 8;
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abits : INTEGER RANGE 2 TO 12 := 8
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);
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PORT(
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rstn : IN STD_LOGIC;
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ReUse : IN STD_LOGIC;
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rclk : IN STD_LOGIC;
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ren : IN STD_LOGIC;
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rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
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empty : OUT STD_LOGIC;
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raddr : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
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wclk : IN STD_LOGIC;
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wen : IN STD_LOGIC;
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wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
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full : OUT STD_LOGIC;
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waddr : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0)
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);
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END COMPONENT;
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--COMPONENT lpp_fifo IS
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-- GENERIC(
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-- tech : INTEGER := 0;
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-- Mem_use : INTEGER := use_RAM;
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-- Enable_ReUse : STD_LOGIC := '0';
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-- DataSz : INTEGER RANGE 1 TO 32 := 8;
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-- AddrSz : INTEGER RANGE 2 TO 12 := 8
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-- );
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-- PORT(
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-- rstn : IN STD_LOGIC;
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-- ReUse : IN STD_LOGIC; --27/01/12
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-- rclk : IN STD_LOGIC;
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-- ren : IN STD_LOGIC;
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-- rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
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-- empty : OUT STD_LOGIC;
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-- raddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0);
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-- wclk : IN STD_LOGIC;
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-- wen : IN STD_LOGIC;
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-- wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
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-- full : OUT STD_LOGIC;
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-- almost_full : OUT STD_LOGIC;
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-- waddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0)
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-- );
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--END COMPONENT;
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--COMPONENT lppFIFOxN IS
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-- GENERIC(
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-- tech : INTEGER := 0;
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-- Mem_use : INTEGER := use_RAM;
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-- Data_sz : INTEGER RANGE 1 TO 32 := 8;
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-- Addr_sz : INTEGER RANGE 1 TO 32 := 8;
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-- FifoCnt : INTEGER := 1;
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-- Enable_ReUse : STD_LOGIC := '0'
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-- );
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-- PORT(
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-- rstn : IN STD_LOGIC;
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-- wclk : IN STD_LOGIC;
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-- rclk : IN STD_LOGIC;
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-- ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
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-- wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
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-- ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
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-- wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
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-- rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
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-- full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
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-- almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
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-- empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0)
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-- );
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--END COMPONENT;
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COMPONENT FillFifo IS
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GENERIC(
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Data_sz : INTEGER RANGE 1 TO 32 := 16;
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Fifo_cnt : INTEGER RANGE 1 TO 8 := 5
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);
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PORT(
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clk : IN STD_LOGIC;
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raz : IN STD_LOGIC;
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write : OUT STD_LOGIC_VECTOR(Fifo_cnt-1 DOWNTO 0);
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reuse : OUT STD_LOGIC_VECTOR(Fifo_cnt-1 DOWNTO 0);
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data : OUT STD_LOGIC_VECTOR(Fifo_cnt*Data_sz-1 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT Bridge IS
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PORT(
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clk : IN STD_LOGIC;
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raz : IN STD_LOGIC;
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EmptyUp : IN STD_LOGIC;
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FullDwn : IN STD_LOGIC;
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WriteDwn : OUT STD_LOGIC;
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ReadUp : OUT STD_LOGIC
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);
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END COMPONENT;
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COMPONENT ssram_plugin IS
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GENERIC (tech : INTEGER := 0);
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PORT
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(
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clk : IN STD_LOGIC;
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mem_ctrlr_o : IN memory_out_type;
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SSRAM_CLK : OUT STD_LOGIC;
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nBWa : OUT STD_LOGIC;
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nBWb : OUT STD_LOGIC;
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nBWc : OUT STD_LOGIC;
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nBWd : OUT STD_LOGIC;
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nBWE : OUT STD_LOGIC;
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nADSC : OUT STD_LOGIC;
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nADSP : OUT STD_LOGIC;
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nADV : OUT STD_LOGIC;
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nGW : OUT STD_LOGIC;
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nCE1 : OUT STD_LOGIC;
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CE2 : OUT STD_LOGIC;
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nCE3 : OUT STD_LOGIC;
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nOE : OUT STD_LOGIC;
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MODE : OUT STD_LOGIC;
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ZZ : OUT STD_LOGIC
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);
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END COMPONENT;
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END;
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