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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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LIBRARY lpp;
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USE lpp.lpp_memory.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.spectral_matrix_package.ALL;
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USE lpp.lpp_dma_pkg.ALL;
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USE lpp.lpp_Header.ALL;
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USE lpp.lpp_matrix.ALL;
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USE lpp.lpp_matrix.ALL;
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USE lpp.lpp_lfr_pkg.ALL;
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USE lpp.lpp_fft.ALL;
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USE lpp.fft_components.ALL;
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USE lpp.window_function_pkg.ALL;
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ENTITY lpp_lfr_ms_FFT IS
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GENERIC (
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WINDOWS_HAANNING_PARAM_SIZE : INTEGER := 15
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);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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-- IN
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sample_valid : IN STD_LOGIC;
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fft_read : IN STD_LOGIC;
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sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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sample_load : OUT STD_LOGIC;
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--OUT
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fft_pong : OUT STD_LOGIC;
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fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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fft_data_valid : OUT STD_LOGIC;
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fft_ready : OUT STD_LOGIC
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);
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END;
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ARCHITECTURE Behavioral OF lpp_lfr_ms_FFT IS
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SIGNAL data_win : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL data_win_valid : STD_LOGIC;
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SIGNAL data_in_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL data_in_reg_valid : STD_LOGIC;
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BEGIN
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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data_in_reg <= (OTHERS => '0');
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data_in_reg_valid <= '0';
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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data_in_reg <= sample_data;
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data_in_reg_valid <= sample_valid;
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END IF;
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END PROCESS;
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window_hanning: window_function
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GENERIC MAP (
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SIZE_DATA => 16,
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SIZE_PARAM => WINDOWS_HAANNING_PARAM_SIZE,
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NB_POINT_BY_WINDOW => 256)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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restart_window => '0',
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data_in => data_in_reg,
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data_in_valid => data_in_reg_valid,
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data_out => data_win,
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data_out_valid => data_win_valid);
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-----------------------------------------------------------------------------
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-- FFT
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-----------------------------------------------------------------------------
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CoreFFT_1 : CoreFFT
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GENERIC MAP (
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LOGPTS => gLOGPTS,
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LOGLOGPTS => gLOGLOGPTS,
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WSIZE => gWSIZE,
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TWIDTH => gTWIDTH,
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DWIDTH => gDWIDTH,
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TDWIDTH => gTDWIDTH,
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RND_MODE => gRND_MODE,
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SCALE_MODE => gSCALE_MODE,
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PTS => gPTS,
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HALFPTS => gHALFPTS,
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inBuf_RWDLY => gInBuf_RWDLY)
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PORT MAP (
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clk => clk,
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ifiStart => '0', -- '1'
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ifiNreset => rstn,
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ifiD_valid => data_win_valid, -- IN
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ifiRead_y => fft_read,
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ifiD_im => (OTHERS => '0'), -- IN
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ifiD_re => data_win, -- IN
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ifoLoad => sample_load, -- IN
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ifoPong => fft_pong,
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ifoY_im => fft_data_im,
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ifoY_re => fft_data_re,
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ifoY_valid => fft_data_valid,
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ifoY_rdy => fft_ready);
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-----------------------------------------------------------------------------
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END Behavioral;
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