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-- Shift_REG.vhd
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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--! Gestion Reception/Transmission
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entity Shift_REG is
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generic(Data_sz : integer := 10);
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port(
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clk : in std_logic;
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Sclk : in std_logic;
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reset : in std_logic;
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SIN : in std_logic;
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SOUT : out std_logic;
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Serialize : in std_logic;
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Serialized : out std_logic;
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D : in std_logic_vector(Data_sz-1 downto 0);
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Q : out std_logic_vector(Data_sz-1 downto 0)
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);
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end entity;
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architecture ar_Shift_REG of Shift_REG is
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signal REG : std_logic_vector(Data_sz-1 downto 0);
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signal Serialized_int : std_logic;
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signal Serialize_reg : std_logic;
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signal CptBits : std_logic_vector(Data_sz-1 downto 0);
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constant CptBits_trig : std_logic_vector(Data_sz-1 downto 0) := (others => '1');
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signal CptBits_flag : std_logic;
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signal CptBits_flag_reg : std_logic;
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begin
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Serialized <= Serialized_int;
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CptBits_flag <= '1' when CptBits = CptBits_trig else '0';
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process(reset,clk)
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begin
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if reset = '0' then
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Serialized_int <= '1';
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CptBits_flag_reg <= '0';
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Q <= (others => '0');
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elsif clk'event and clk = '1' then
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CptBits_flag_reg <= CptBits_flag;
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if CptBits_flag = '1' and CptBits_flag_reg = '0' then
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Serialized_int <= '1';
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Q <= REG;
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elsif Serialize = '1' then
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Serialized_int <= '0';
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end if;
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end if;
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end process;
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process(reset,Sclk)
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begin
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if reset = '0' then
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CptBits <= (others => '0');
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REG <= (others => '0');
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SOUT <= '1';
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Serialize_reg <= '0';
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elsif Sclk'event and Sclk = '1' then
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Serialize_reg <= Serialized_int;
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if (Serialized_int = '0' and Serialize_reg ='1') then
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REG <= SIN & D(Data_sz-1 downto 1);
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SOUT <= D(0);
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elsif CptBits_flag ='1' then
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REG <= SIN & D(Data_sz-1 downto 1);
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SOUT <= D(0);
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elsif Serialized_int = '0' then
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REG <= SIN & REG(Data_sz-1 downto 1);
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SOUT <= REG(0);
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else
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SOUT <= '1';
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end if;
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if Serialized_int = '0' then
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if CptBits_flag = '1' then
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CptBits <= (others => '0');
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else
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CptBits <= '1' & CptBits(Data_sz-1 downto 1);
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end if;
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else
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CptBits <= (others => '0');
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end if;
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end if;
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end process;
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end ar_Shift_REG;
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