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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE IEEE.std_logic_signed.ALL;
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USE IEEE.MATH_real.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY std;
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USE std.textio.ALL;
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LIBRARY lpp;
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USE lpp.iir_filter.ALL;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.FILTERcfg.ALL;
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USE lpp.lpp_lfr_filter_coeff.ALL;
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USE lpp.general_purpose.ALL;
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USE lpp.data_type_pkg.ALL;
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USE lpp.lpp_lfr_pkg.ALL;
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USE lpp.general_purpose.ALL;
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USE lpp.lpp_sim_pkg.ALL;
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ENTITY testbench IS
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GENERIC(
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tech : INTEGER := 0; --axcel,0
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Mem_use : INTEGER := use_CEL --use_RAM,use_CEL
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);
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END;
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ARCHITECTURE behav OF testbench IS
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CONSTANT ChanelCount : INTEGER := 8;
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CONSTANT Coef_SZ : INTEGER := 9;
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CONSTANT CoefCntPerCel : INTEGER := 6;
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CONSTANT CoefPerCel : INTEGER := 5;
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CONSTANT Cels_count : INTEGER := 5;
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SIGNAL sample : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
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SIGNAL sample_val : STD_LOGIC;
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SIGNAL sample_fx : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
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SIGNAL sample_fx_val : STD_LOGIC;
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SIGNAL TSTAMP : INTEGER := 0;
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL clk_98304Hz : STD_LOGIC := '0';
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SIGNAL clk_98304Hz_r : STD_LOGIC := '0';
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SIGNAL rstn : STD_LOGIC;
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SIGNAL signal_gen : sample_vector(0 to ChanelCount-1,17 downto 0);
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SIGNAL sample_fx_wdata : Samples(ChanelCount-1 DOWNTO 0);
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SIGNAL signal_rec : sample_vector(0 to ChanelCount-1,15 downto 0);
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SIGNAL end_of_simu : STD_LOGIC := '0';
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CONSTANT half_samplig_period : time := 5086263 ps;--INTEGER( REAL(1000**4) / REAL(24576.0*4.0*2)) * 1 ps;
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BEGIN
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-----------------------------------------------------------------------------
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-- CLOCK and RESET
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-----------------------------------------------------------------------------
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PROCESS
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BEGIN -- PROCESS
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WAIT UNTIL clk = '1';
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rstn <= '0';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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rstn <= '1';
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WAIT UNTIL end_of_simu = '1';
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WAIT UNTIL clk = '1';
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assert false report "end of test" severity note;
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-- Wait forever; this will finish the simulation.
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wait;
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END PROCESS;
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-----------------------------------------------------------------------------
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clk_98304Hz_gen:PROCESS
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BEGIN
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IF end_of_simu /= '1' THEN
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clk_98304Hz <= NOT clk_98304Hz;
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WAIT FOR half_samplig_period;
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ELSE
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assert false report "end of test" severity note;
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WAIT;
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END IF;
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END PROCESS;
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clk_25M_gen:PROCESS
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BEGIN
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IF end_of_simu /= '1' THEN
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clk <= NOT clk;
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TSTAMP <= TSTAMP+20;
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WAIT FOR 20 ns;
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ELSE
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assert false report "end of test" severity note;
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WAIT;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-- LPP_LFR_FILTER f0
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-----------------------------------------------------------------------------
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IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
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GENERIC MAP (
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tech => tech,
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Mem_use => Mem_use,
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Sample_SZ => 18,
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Coef_SZ => Coef_SZ,
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Coef_Nb => 25,
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Coef_sel_SZ => 5,
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Cels_count => Cels_count,
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ChanelsCount => ChanelCount,
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FILENAME => "")
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PORT MAP (
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rstn => rstn,
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clk => clk,
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virg_pos => 7,
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coefs => CoefsInitValCst_v2,
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sample_in_val => sample_val,
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sample_in => sample,
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sample_out_val => sample_fx_val,
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sample_out => sample_fx);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- SAMPLE GENERATION
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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sample_val <= '0';
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clk_98304Hz_r <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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clk_98304Hz_r <= clk_98304Hz;
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IF clk_98304Hz = '1' AND clk_98304Hz_r = '0' THEN
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sample_val <= '1';
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ELSE
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sample_val <= '0';
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END IF;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
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SampleLoop : FOR j IN 0 TO 15 GENERATE
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sample_fx_wdata(i)(j) <= sample_fx(i,j);
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signal_rec(i,j) <= sample_fx_wdata(i)(j);
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sample(i,j) <= signal_gen(i,j);
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END GENERATE;
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sample(i,16) <= signal_gen(i,16);
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sample(i,17) <= signal_gen(i,17);
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END GENERATE;
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-----------------------------------------------------------------------------
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-- READ INPUT SIGNALS
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-----------------------------------------------------------------------------
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gen: sig_reader
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GENERIC MAP(
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FNAME => "input.txt",
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WIDTH => ChanelCount,
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RESOLUTION => 18,
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GAIN => 1.0
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)
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PORT MAP(
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clk => sample_val,
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end_of_simu => end_of_simu,
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out_signal => signal_gen
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);
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-----------------------------------------------------------------------------
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-- RECORD OUTPUT SIGNALS
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-----------------------------------------------------------------------------
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rec : sig_recorder
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GENERIC MAP(
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FNAME => "output_fx.txt",
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WIDTH => ChanelCount,
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RESOLUTION => 16
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)
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PORT MAP(
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clk => sample_fx_val,
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end_of_simu => end_of_simu,
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timestamp => TSTAMP,
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input_signal => signal_rec
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);
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END;
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