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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE IEEE.std_logic_signed.ALL;
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USE IEEE.MATH_real.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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library gaisler;
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use gaisler.libdcom.all;
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use gaisler.sim.all;
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use gaisler.uart.all;
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library grlib;
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use grlib.stdlib.all;
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use grlib.amba.all;
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use grlib.devices.all;
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LIBRARY std;
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USE std.textio.ALL;
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LIBRARY lpp;
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USE lpp.general_purpose.ALL;
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USE lpp.lpp_amba.all;
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ENTITY testbench IS
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END;
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ARCHITECTURE behav OF testbench IS
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SIGNAL TSTAMP : INTEGER := 0;
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL rstn : STD_LOGIC;
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--AMBA bus standard interface signals--
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signal apbi : apb_slv_in_type;
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signal apbo : apb_slv_out_vector := (others => apb_none);
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signal ahbsi : ahb_slv_in_type;
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signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
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signal ahbmi : ahb_mst_in_type;
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signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
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signal dui : uart_in_type;
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signal duo : uart_out_type;
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signal dsutx : STD_LOGIC;
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signal dsurx : STD_LOGIC;
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SIGNAL end_of_simu : STD_LOGIC := '0';
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constant lresp : boolean := false;
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SIGNAL SPW_Tickout : std_logic:='0';
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SIGNAL CoarseTime : STD_LOGIC_VECTOR(31 DOWNTO 0):=(others=>'0');
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SIGNAL FineTime : STD_LOGIC_VECTOR(15 DOWNTO 0):=(others=>'0');
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SIGNAL Trigger : STD_LOGIC_VECTOR(3 DOWNTO 0);
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BEGIN
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-----------------------------------------------------------------------------
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-- CLOCK and RESET
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-----------------------------------------------------------------------------
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PROCESS
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BEGIN -- PROCESS
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WAIT UNTIL clk = '1';
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rstn <= '0';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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rstn <= '1';
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WAIT UNTIL end_of_simu = '1';
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WAIT UNTIL clk = '1';
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assert false report "end of test" severity note;
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-- Wait forever; this will finish the simulation.
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wait;
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END PROCESS;
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-----------------------------------------------------------------------------
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clk_25M_gen:PROCESS
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BEGIN
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IF end_of_simu /= '1' THEN
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clk <= NOT clk;
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TSTAMP <= TSTAMP+20;
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WAIT FOR 20 ns;
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ELSE
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assert false report "end of test" severity note;
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WAIT;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-- CoarseTime and FineTime
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-----------------------------------------------------------------------------
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SpwFineTime:PROCESS
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BEGIN
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IF end_of_simu /= '1' THEN
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IF SPW_Tickout = '1' then
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FineTime <= (others=>'0');
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ELSE
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FineTime <= std_logic_vector(UNSIGNED(FineTime) + 1);
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END IF;
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WAIT FOR 15 us;
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ELSE
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assert false report "end of test" severity note;
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WAIT;
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END IF;
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END PROCESS;
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SpwCoarseTime:PROCESS
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BEGIN
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IF end_of_simu /= '1' THEN
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wait until SPW_Tickout = '1';
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CoarseTime <= std_logic_vector(UNSIGNED(CoarseTime) + 1);
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ELSE
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assert false report "end of test" severity note;
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WAIT;
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END IF;
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END PROCESS;
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SPWTickout:PROCESS
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BEGIN
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IF end_of_simu /= '1' THEN
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wait for (1000 ms - 20 ns);
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SPW_Tickout <= '1';
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wait for 20 ns;
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SPW_Tickout <= '0';
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ELSE
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assert false report "end of test" severity note;
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WAIT;
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END IF;
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END PROCESS;
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----------------------------------------------------------------------
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--- AHB CONTROLLER --------------------------------------------------
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----------------------------------------------------------------------
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ahb0 : ahbctrl -- AHB arbiter/multiplexer
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generic map (defmast => 0, split => 1,
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rrobin => 1, ioaddr => 16#FFF#,
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nahbm => 1, nahbs => 1)
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port map (rstn, clk, ahbmi, ahbmo, ahbsi, ahbso);
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dcom0: ahbuart -- Debug UART
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generic map (hindex => 0, pindex => 0, paddr => 0)
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port map (rstn, clk, dui, duo, apbi, apbo(0), ahbmi, ahbmo(0));
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dsutx <= duo.txd;
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dui.rxd <= dsurx;
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----------------------------------------------------------------------
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--- APB Bridge ------------------------------------------------------
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----------------------------------------------------------------------
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apb0 : apbctrl -- AHB/APB bridge
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generic map (hindex => 0, haddr => 16#800#)
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port map (rstn, clk, ahbsi, ahbso(0), apbi, apbo );
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----------------------------------------------------------------------
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--- APB_ADVANCED_TRIGGER_v -> Device Under Test ---------------------
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----------------------------------------------------------------------
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DUT: APB_ADVANCED_TRIGGER_v
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generic map(
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pindex => 1,
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paddr => 1,
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count => 4
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)
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port map(
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rstn => rstn,
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clk => clk,
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apbi => apbi,
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apbo => apbo(1),
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SPW_Tickout => SPW_Tickout,
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CoarseTime => CoarseTime,
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FineTime => FineTime,
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Trigger => Trigger
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);
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dsucom : process
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variable w32 : std_logic_vector(31 downto 0);
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constant txp : time := 160 * 1 ns;
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procedure writeReg(signal dsutx : out std_logic; address : integer; value : integer) is
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begin
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txc(dsutx, 16#c0#, txp); --control byte
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txa(dsutx, (address / (256*256*256)) , (address / (256*256)), (address / (256)), address, txp); --adress
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txa(dsutx, (value / (256*256*256)) , (value / (256*256)), (value / (256)), value, txp); --write data
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end;
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procedure readReg(signal dsurx : in std_logic; signal dsutx : out std_logic; address : integer; value: out std_logic_vector) is
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begin
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txc(dsutx, 16#a0#, txp); --control byte
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txa(dsutx, (address / (256*256*256)) , (address / (256*256)), (address / (256)), address, txp); --adress
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rxi(dsurx, value, txp, lresp); --write data
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end;
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procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
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variable c8 : std_logic_vector(7 downto 0);
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begin
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dsutx <= '1';
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wait for 5000 ns;
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txc(dsutx, 16#55#, txp);
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writeReg(dsutx,16#8000100#,16#00#);
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end;
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begin
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dsucfg(dsutx, dsurx);
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wait for 1000 ms;
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end_of_simu <= '1';
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wait;
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end process;
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all_apbo : FOR I IN 0 TO 15 GENERATE
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apbo_not_used : IF I /= 1 AND I /= 0 GENERATE
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apbo(I) <= apb_none;
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END GENERATE apbo_not_used;
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END GENERATE all_apbo;
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END;
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