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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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-------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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LIBRARY lpp;
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USE lpp.lpp_waveform_pkg.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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ENTITY lpp_waveform_genaddress IS
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GENERIC (
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nb_data_by_buffer_size : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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-------------------------------------------------------------------------
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-- CONFIG
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-------------------------------------------------------------------------
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nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
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addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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-------------------------------------------------------------------------
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-- CTRL
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-------------------------------------------------------------------------
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empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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-------------------------------------------------------------------------
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-- STATUS
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-------------------------------------------------------------------------
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status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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-------------------------------------------------------------------------
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-- ADDR DATA OUT
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-------------------------------------------------------------------------
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data_f0_data_out_valid_burst : OUT STD_LOGIC;
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data_f1_data_out_valid_burst : OUT STD_LOGIC;
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data_f2_data_out_valid_burst : OUT STD_LOGIC;
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data_f3_data_out_valid_burst : OUT STD_LOGIC;
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data_f0_data_out_valid : OUT STD_LOGIC;
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data_f1_data_out_valid : OUT STD_LOGIC;
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data_f2_data_out_valid : OUT STD_LOGIC;
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data_f3_data_out_valid : OUT STD_LOGIC;
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data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END lpp_waveform_genaddress;
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ARCHITECTURE beh OF lpp_waveform_genaddress IS
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SIGNAL addr_data_f0_s : STD_LOGIC_VECTOR(29 DOWNTO 0);
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SIGNAL addr_data_f1_s : STD_LOGIC_VECTOR(29 DOWNTO 0);
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SIGNAL addr_data_f2_s : STD_LOGIC_VECTOR(29 DOWNTO 0);
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SIGNAL addr_data_f3_s : STD_LOGIC_VECTOR(29 DOWNTO 0);
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-----------------------------------------------------------------------------
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-- Valid gen
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-----------------------------------------------------------------------------
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SIGNAL addr_burst_avail : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL data_out_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL data_out_valid_burst : STD_LOGIC_VECTOR(3 DOWNTO 0);
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-----------------------------------------------------------------------------
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-- Register
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-----------------------------------------------------------------------------
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SIGNAL data_addr_v_pre : Data_Vector(3 DOWNTO 0, 29 DOWNTO 0);
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SIGNAL data_addr_v_reg : Data_Vector(3 DOWNTO 0, 29 DOWNTO 0);
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SIGNAL data_addr_v_base : Data_Vector(3 DOWNTO 0, 29 DOWNTO 0);
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SIGNAL data_addr_pre : STD_LOGIC_VECTOR(29 DOWNTO 0); -- TODO
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SIGNAL data_addr_reg : STD_LOGIC_VECTOR(29 DOWNTO 0); -- TODO
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SIGNAL data_addr_base : STD_LOGIC_VECTOR(29 DOWNTO 0); -- TODO
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-----------------------------------------------------------------------------
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--
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-----------------------------------------------------------------------------
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SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
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TYPE addr_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(29 DOWNTO 0);
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SIGNAL addr_v_p : addr_VECTOR(3 DOWNTO 0);
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SIGNAL addr_v_b : addr_VECTOR(3 DOWNTO 0);
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SIGNAL addr_avail: addr_VECTOR(3 DOWNTO 0);
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BEGIN -- beh
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-----------------------------------------------------------------------------
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-- valid gen
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-----------------------------------------------------------------------------
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data_f0_data_out_valid <= data_out_valid(0);
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data_f1_data_out_valid <= data_out_valid(1);
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data_f2_data_out_valid <= data_out_valid(2);
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data_f3_data_out_valid <= data_out_valid(3);
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data_f0_data_out_valid_burst <= data_out_valid_burst(0);
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data_f1_data_out_valid_burst <= data_out_valid_burst(1);
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data_f2_data_out_valid_burst <= data_out_valid_burst(2);
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data_f3_data_out_valid_burst <= data_out_valid_burst(3);
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all_bit_data_valid_out : FOR I IN 3 DOWNTO 0 GENERATE
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addr_avail(I) <= (addr_v_b(I) + nb_data_by_buffer - addr_v_p(I));
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addr_burst_avail(I) <= '1' WHEN (addr_v_p(I)(3 DOWNTO 0) = "0000")
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AND (UNSIGNED(addr_avail(I)) > 15)
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ELSE '0';
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data_out_valid(I) <= '0' WHEN (status_full_s(I) = '1' AND status_full_ack(I) = '0') ELSE
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'0' WHEN empty(I) = '1' ELSE
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'0' WHEN addr_burst_avail(I) = '1' ELSE
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'0' WHEN (run = '0') ELSE
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'1';
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data_out_valid_burst(I) <= '0' WHEN (status_full_s(I) = '1' AND status_full_ack(I) = '0') ELSE
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'0' WHEN empty(I) = '1' ELSE
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'0' WHEN addr_burst_avail(I) = '0' ELSE
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'0' WHEN empty_almost(I) = '1' ELSE
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'0' WHEN (run = '0') ELSE
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'1';
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END GENERATE all_bit_data_valid_out;
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-----------------------------------------------------------------------------
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-- Register
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-----------------------------------------------------------------------------
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all_data_bit : FOR J IN 29 DOWNTO 0 GENERATE
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all_data_addr : FOR I IN 3 DOWNTO 0 GENERATE
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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data_addr_v_reg(I, J) <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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IF run = '1' AND status_full_ack(I) = '0' THEN
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data_addr_v_reg(I, J) <= data_addr_v_pre(I, J);
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ELSE
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data_addr_v_reg(I, J) <= data_addr_v_base(I, J);
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END IF;
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END IF;
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END PROCESS;
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data_addr_v_pre(I, J) <= data_addr_v_reg(I, J) WHEN data_ren(I) = '1' ELSE data_addr_pre(J);
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END GENERATE all_data_addr;
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data_addr_reg(J) <= data_addr_v_reg(0, J) WHEN data_ren(0) = '0' ELSE
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data_addr_v_reg(1, J) WHEN data_ren(1) = '0' ELSE
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data_addr_v_reg(2, J) WHEN data_ren(2) = '0' ELSE
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data_addr_v_reg(3, J);
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data_addr_v_base(0, J) <= addr_data_f0_s(J);
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data_addr_v_base(1, J) <= addr_data_f1_s(J);
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data_addr_v_base(2, J) <= addr_data_f2_s(J);
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data_addr_v_base(3, J) <= addr_data_f3_s(J);
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data_f0_addr_out(J+2) <= data_addr_v_reg(0, J) ;
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data_f1_addr_out(J+2) <= data_addr_v_reg(1, J) ;
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data_f2_addr_out(J+2) <= data_addr_v_reg(2, J) ;
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data_f3_addr_out(J+2) <= data_addr_v_reg(3, J) ;
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END GENERATE all_data_bit;
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addr_data_f0_s <= addr_data_f0(31 DOWNTO 2);
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addr_data_f1_s <= addr_data_f1(31 DOWNTO 2);
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addr_data_f2_s <= addr_data_f2(31 DOWNTO 2);
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addr_data_f3_s <= addr_data_f3(31 DOWNTO 2);
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data_f0_addr_out(1 DOWNTO 0) <= "00";
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data_f1_addr_out(1 DOWNTO 0) <= "00";
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data_f2_addr_out(1 DOWNTO 0) <= "00";
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data_f3_addr_out(1 DOWNTO 0) <= "00";
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-----------------------------------------------------------------------------
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-- ADDER
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-----------------------------------------------------------------------------
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data_addr_pre <= data_addr_reg + 1;
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-----------------------------------------------------------------------------
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-- FULL STATUS
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-----------------------------------------------------------------------------
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all_status : FOR I IN 3 DOWNTO 0 GENERATE
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all_bit_addr : FOR J IN 29 DOWNTO 0 GENERATE
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addr_v_p(I)(J) <= data_addr_v_pre(I, J);
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addr_v_b(I)(J) <= data_addr_v_base(I, J);
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END GENERATE all_bit_addr;
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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status_full_s(I) <= '0';
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status_full_err(I) <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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IF run = '1' AND status_full_ack(I) = '0' THEN
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IF addr_v_p(I) = addr_v_b(I) + nb_data_by_buffer THEN
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status_full_s(I) <= '1';
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IF status_full_s(I) = '1' AND data_ren(I) = '0' THEN
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status_full_err(I) <= '1';
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END IF;
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END IF;
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ELSE
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status_full_s(I) <= '0';
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status_full_err(I) <= '0';
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END IF;
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END IF;
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END PROCESS;
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END GENERATE all_status;
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status_full <= status_full_s;
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END beh;
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