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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Jean-christophe PELLION
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.lpp_memory.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.lpp_waveform_pkg.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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ENTITY lpp_waveform_fifo_withoutLatency IS
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GENERIC(
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tech : INTEGER := 0
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);
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PORT(
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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---------------------------------------------------------------------------
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run : IN STD_LOGIC;
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---------------------------------------------------------------------------
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empty_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is lesser than 16 * 32b
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empty : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0);
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data_ren : IN STD_LOGIC_VECTOR( 3 DOWNTO 0);
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rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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---------------------------------------------------------------------------
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full_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b
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full : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0);
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data_wen : IN STD_LOGIC_VECTOR( 3 DOWNTO 0);
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wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END ENTITY;
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ARCHITECTURE ar_lpp_waveform_fifo_withoutLatency OF lpp_waveform_fifo_withoutLatency IS
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SIGNAL empty_almost_s : STD_LOGIC_VECTOR( 3 DOWNTO 0);
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SIGNAL empty_s : STD_LOGIC_VECTOR( 3 DOWNTO 0);
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SIGNAL data_ren_s : STD_LOGIC_VECTOR( 3 DOWNTO 0);
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SIGNAL rdata_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
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BEGIN
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lpp_waveform_fifo_latencyCorrection_0: lpp_waveform_fifo_latencyCorrection
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GENERIC MAP (
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tech => tech)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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run => run,
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empty_almost => empty_almost(0),
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empty => empty(0),
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data_ren => data_ren(0),
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rdata => rdata_0,
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empty_almost_fifo => empty_almost_s(0),
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empty_fifo => empty_s(0),
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data_ren_fifo => data_ren_s(0),
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rdata_fifo => rdata_s);
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lpp_waveform_fifo_latencyCorrection_1: lpp_waveform_fifo_latencyCorrection
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GENERIC MAP (
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tech => tech)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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run => run,
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empty_almost => empty_almost(1),
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empty => empty(1),
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data_ren => data_ren(1),
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rdata => rdata_1,
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empty_almost_fifo => empty_almost_s(1),
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empty_fifo => empty_s(1),
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data_ren_fifo => data_ren_s(1),
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rdata_fifo => rdata_s);
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lpp_waveform_fifo_latencyCorrection_2: lpp_waveform_fifo_latencyCorrection
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GENERIC MAP (
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tech => tech)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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run => run,
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empty_almost => empty_almost(2),
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empty => empty(2),
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data_ren => data_ren(2),
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rdata => rdata_2,
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empty_almost_fifo => empty_almost_s(2),
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empty_fifo => empty_s(2),
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data_ren_fifo => data_ren_s(2),
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rdata_fifo => rdata_s);
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lpp_waveform_fifo_latencyCorrection_3: lpp_waveform_fifo_latencyCorrection
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GENERIC MAP (
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tech => tech)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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run => run,
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empty_almost => empty_almost(3),
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empty => empty(3),
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data_ren => data_ren(3),
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rdata => rdata_3,
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empty_almost_fifo => empty_almost_s(3),
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empty_fifo => empty_s(3),
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data_ren_fifo => data_ren_s(3),
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rdata_fifo => rdata_s);
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lpp_waveform_fifo_1: lpp_waveform_fifo
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GENERIC MAP (
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tech => tech)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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run => run,
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empty_almost => empty_almost_s,
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empty => empty_s,
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data_ren => data_ren_s,
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rdata => rdata_s,
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full_almost => full_almost,
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full => full,
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data_wen => data_wen,
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wdata => wdata);
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END ARCHITECTURE;
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