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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Jean-christophe PELLION
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.lpp_waveform_pkg.ALL;
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USE lpp.general_purpose.ALL;
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ENTITY lpp_waveform_fifo_arbiter IS
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GENERIC(
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tech : INTEGER := 0;
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nb_data_by_buffer_size : INTEGER := 11
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);
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PORT(
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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---------------------------------------------------------------------------
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run : IN STD_LOGIC;
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nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
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---------------------------------------------------------------------------
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-- SNAPSHOT INTERFACE (INPUT)
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---------------------------------------------------------------------------
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data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
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time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
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---------------------------------------------------------------------------
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-- FIFO INTERFACE (OUTPUT)
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---------------------------------------------------------------------------
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data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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---------------------------------------------------------------------------
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-- TIME INTERFACE (OUTPUT)
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---------------------------------------------------------------------------
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time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
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time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
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);
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END ENTITY;
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ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS
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TYPE state_type_fifo_arbiter IS (IDLE,DATA1,DATA2,DATA3,LAST);
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SIGNAL state : state_type_fifo_arbiter;
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-----------------------------------------------------------------------------
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-- DATA MUX
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-----------------------------------------------------------------------------
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TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL data_0 : WORD_VECTOR(2 DOWNTO 0);
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SIGNAL data_1 : WORD_VECTOR(2 DOWNTO 0);
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SIGNAL data_2 : WORD_VECTOR(2 DOWNTO 0);
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SIGNAL data_3 : WORD_VECTOR(2 DOWNTO 0);
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SIGNAL data_sel : WORD_VECTOR(2 DOWNTO 0);
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-----------------------------------------------------------------------------
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-- RR and SELECTION
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-----------------------------------------------------------------------------
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SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL sel_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL sel_reg : STD_LOGIC;
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SIGNAL sel_ack : STD_LOGIC;
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SIGNAL no_sel : STD_LOGIC;
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-----------------------------------------------------------------------------
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-- REG
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-----------------------------------------------------------------------------
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SIGNAL count_enable : STD_LOGIC;
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SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
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SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
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SIGNAL time_sel : STD_LOGIC_VECTOR(47 DOWNTO 0);
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BEGIN
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-----------------------------------------------------------------------------
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-- CONTROL
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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count_enable <= '0';
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data_in_ack <= (OTHERS => '0');
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data_out_wen <= (OTHERS => '1');
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sel_ack <= '0';
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state <= IDLE;
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time_out <= (OTHERS => '0');
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time_out_new <= (OTHERS => '0');
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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count_enable <= '0';
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data_in_ack <= (OTHERS => '0');
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data_out_wen <= (OTHERS => '1');
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sel_ack <= '0';
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time_out_new <= (OTHERS => '0');
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IF run = '0' THEN
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state <= IDLE;
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time_out <= (OTHERS => '0');
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ELSE
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CASE state IS
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WHEN IDLE =>
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IF no_sel = '0' THEN
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state <= DATA1;
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END IF;
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WHEN DATA1 =>
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count_enable <= '1';
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IF UNSIGNED(count) = 0 THEN
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time_out <= time_sel;
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time_out_new <= sel;
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END IF;
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data_out_wen <= NOT sel;
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data_out <= data_sel(0);
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state <= DATA2;
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WHEN DATA2 =>
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data_out_wen <= NOT sel;
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data_out <= data_sel(1);
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state <= DATA3;
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WHEN DATA3 =>
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data_out_wen <= NOT sel;
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data_out <= data_sel(2);
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state <= LAST;
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data_in_ack <= sel;
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WHEN LAST =>
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state <= IDLE;
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sel_ack <= '1';
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WHEN OTHERS => NULL;
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END CASE;
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END IF;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- DATA MUX
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-----------------------------------------------------------------------------
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all_word: FOR J IN 2 DOWNTO 0 GENERATE
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all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE
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data_0(J)(I) <= data_in(0,I+32*J);
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data_1(J)(I) <= data_in(1,I+32*J);
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data_2(J)(I) <= data_in(2,I+32*J);
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data_3(J)(I) <= data_in(3,I+32*J);
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END GENERATE all_data_bit;
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END GENERATE all_word;
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data_sel <= data_0 WHEN sel(0) = '1' ELSE
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data_1 WHEN sel(1) = '1' ELSE
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data_2 WHEN sel(2) = '1' ELSE
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data_3;
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all_time_bit: FOR I IN 47 DOWNTO 0 GENERATE
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time_sel(I) <= time_in(0,I) WHEN sel(0) = '1' ELSE
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time_in(1,I) WHEN sel(1) = '1' ELSE
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time_in(2,I) WHEN sel(2) = '1' ELSE
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time_in(3,I);
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END GENERATE all_time_bit;
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-----------------------------------------------------------------------------
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-- RR and SELECTION
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-----------------------------------------------------------------------------
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all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE
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valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I);
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END GENERATE all_input_rr;
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RR_Arbiter_4_1 : RR_Arbiter_4
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PORT MAP (
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clk => clk,
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rstn => rstn,
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in_valid => valid_in_rr,
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out_grant => sel_s);
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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sel <= "0000";
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sel_reg <= '0';
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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IF run = '0' THEN
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sel <= "0000";
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sel_reg <= '0';
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ELSE
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IF sel_reg = '0' OR sel_ack = '1' THEN
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sel <= sel_s;
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IF sel_s = "0000" THEN
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sel_reg <= '0';
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ELSE
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sel_reg <= '1';
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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no_sel <= '1' WHEN sel = "0000" ELSE '0';
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-----------------------------------------------------------------------------
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-- REG
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-----------------------------------------------------------------------------
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reg_count_i: lpp_waveform_fifo_arbiter_reg
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GENERIC MAP (
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data_size => nb_data_by_buffer_size,
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data_nb => 4)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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run => run,
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max_count => nb_data_by_buffer,
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enable => count_enable,
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sel => sel,
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data => count,
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data_s => count_s);
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END ARCHITECTURE;
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